/****************************************************************************** * * Title : timUir.c * Version 0.0 * * Description: callback functions(TIM registers access). * Related files: timUir.uir * * Author: Lukas Tomasek, tomasekl@fzu.cz * ******************************************************************************/ /****************************************************************************** * Header files * ******************************************************************************/ #include #include #include "timUir.h" #include "vmeHpiUtility.h" #include "uirUtility.h" #include "globalDefinitions.h" #include "hostUtility.h" #include "fileUtility.h" /****************************************************************************** * Definitions * ******************************************************************************/ /****************************************************************************** * Macros * ******************************************************************************/ /****************************************************************************** * Static Function Declarations * ******************************************************************************/ static void readBit(int panel, int control, int bitNumber); /****************************************************************************** * LW_CVI callback functions * ******************************************************************************/ /*============================================================================= * tim() *============================================================================= * * * */ int CVICALLBACK tim (int panel, int control, int event, void *callbackData, int eventData1, int eventData2){ UINT32 relVmeAddress, trigCount, bcCount, value; int bit, i, j, index, status; ERROR_ID errorId; char file[300]; long fileSize; char *buffer; char string[300]; if(event==EVENT_VAL_CHANGED){ switch(control){ case TIMP_TIM_REGS: GetCtrlVal(panel, control, &relVmeAddress); SetCtrlVal(panel, TIMP_WORD_ADDRESS, relVmeAddress); status = GetCtrlIndex (panel, control, &index); errorId=loadTimRegFile(panel, index); ERROR_CHECK(errorId, loadTimRegFile()); break; case TIMP_WRITE_DATA_WORD: GetCtrlVal(panel, control, &value); SetCtrlVal(panel, TIMP_BUTT_0, READ_BIT(value, 0)); SetCtrlVal(panel, TIMP_BUTT_1, READ_BIT(value, 1)); SetCtrlVal(panel, TIMP_BUTT_2, READ_BIT(value, 2)); SetCtrlVal(panel, TIMP_BUTT_3, READ_BIT(value, 3)); SetCtrlVal(panel, TIMP_BUTT_4, READ_BIT(value, 4)); SetCtrlVal(panel, TIMP_BUTT_5, READ_BIT(value, 5)); SetCtrlVal(panel, TIMP_BUTT_6, READ_BIT(value, 6)); SetCtrlVal(panel, TIMP_BUTT_7, READ_BIT(value, 7)); SetCtrlVal(panel, TIMP_BUTT_8, READ_BIT(value, 8)); SetCtrlVal(panel, TIMP_BUTT_9, READ_BIT(value, 9)); SetCtrlVal(panel, TIMP_BUTT_10, READ_BIT(value,10)); SetCtrlVal(panel, TIMP_BUTT_11, READ_BIT(value,11)); SetCtrlVal(panel, TIMP_BUTT_12, READ_BIT(value,12)); SetCtrlVal(panel, TIMP_BUTT_13, READ_BIT(value,13)); SetCtrlVal(panel, TIMP_BUTT_14, READ_BIT(value,14)); SetCtrlVal(panel, TIMP_BUTT_15, READ_BIT(value,15)); break; case TIMP_BUTT_0: readBit(panel, control, 0); break; case TIMP_BUTT_1: readBit(panel, control, 1); break; case TIMP_BUTT_2: readBit(panel, control, 2); break; case TIMP_BUTT_3: readBit(panel, control, 3); break; case TIMP_BUTT_4: readBit(panel, control, 4); break; case TIMP_BUTT_5: readBit(panel, control, 5); break; case TIMP_BUTT_6: readBit(panel, control, 6); break; case TIMP_BUTT_7: readBit(panel, control, 7); break; case TIMP_BUTT_8: readBit(panel, control, 8); break; case TIMP_BUTT_9: readBit(panel, control, 9); break; case TIMP_BUTT_10: readBit(panel, control, 10); break; case TIMP_BUTT_11: readBit(panel, control, 11); break; case TIMP_BUTT_12: readBit(panel, control, 12); break; case TIMP_BUTT_13: readBit(panel, control, 13); break; case TIMP_BUTT_14: readBit(panel, control, 14); break; case TIMP_BUTT_15: readBit(panel, control, 15); break; } }else{ if(event==EVENT_COMMIT){ GetCtrlVal(panel, TIMP_WORD_ADDRESS, &relVmeAddress); switch(control){ case TIMP_READ_WORD: errorId=vmeReadElement(BASE_ADDRESS(TIM_SLOT_NUMBER)+relVmeAddress, &value, sizeof(UINT16)); ERROR_CHECK(errorId, vmeReadElement()); if(errorId!=SUCCESS) break; SetCtrlVal(panel, TIMP_READ_DATA_WORD, value&0xFFFF); SetCtrlVal(panel, TIMP_RBIT_0, READ_BIT(value, 0)); SetCtrlVal(panel, TIMP_RBIT_1, READ_BIT(value, 1)); SetCtrlVal(panel, TIMP_RBIT_2, READ_BIT(value, 2)); SetCtrlVal(panel, TIMP_RBIT_3, READ_BIT(value, 3)); SetCtrlVal(panel, TIMP_RBIT_4, READ_BIT(value, 4)); SetCtrlVal(panel, TIMP_RBIT_5, READ_BIT(value, 5)); SetCtrlVal(panel, TIMP_RBIT_6, READ_BIT(value, 6)); SetCtrlVal(panel, TIMP_RBIT_7, READ_BIT(value, 7)); SetCtrlVal(panel, TIMP_RBIT_8, READ_BIT(value, 8)); SetCtrlVal(panel, TIMP_RBIT_9, READ_BIT(value, 9)); SetCtrlVal(panel, TIMP_RBIT_10, READ_BIT(value,10)); SetCtrlVal(panel, TIMP_RBIT_11, READ_BIT(value,11)); SetCtrlVal(panel, TIMP_RBIT_12, READ_BIT(value,12)); SetCtrlVal(panel, TIMP_RBIT_13, READ_BIT(value,13)); SetCtrlVal(panel, TIMP_RBIT_14, READ_BIT(value,14)); SetCtrlVal(panel, TIMP_RBIT_15, READ_BIT(value,15)); break; case TIMP_SEND_CONT_L1A: // Enable Randomizer errorId=vmeWriteElement(0x0040, BASE_ADDRESS(TIM_SLOT_NUMBER)+0x42, sizeof(UINT16)); errorId=vmeWriteElement(0x02, BASE_ADDRESS(TIM_SLOT_NUMBER)+0x0, sizeof(UINT16)); ERROR_CHECK(errorId, vmeWriteElement()); break; case TIMP_STOP_CONT_L1A: // Stop Randomizer errorId=vmeWriteElement(0x0000, BASE_ADDRESS(TIM_SLOT_NUMBER)+0x42, sizeof(UINT16)); errorId=vmeWriteElement(0x0, BASE_ADDRESS(TIM_SLOT_NUMBER)+0x0, sizeof(UINT16)); ERROR_CHECK(errorId, vmeWriteElement()); break; case TIMP_SEND_ECR_2: // Stop Randomizer errorId=vmeWriteElement(0x0000, BASE_ADDRESS(TIM_SLOT_NUMBER)+0x42, sizeof(UINT16)); errorId=vmeWriteElement(0x0, BASE_ADDRESS(TIM_SLOT_NUMBER)+0x0, sizeof(UINT16)); Sleep(50); // Wait to clear triggers ERROR_CHECK(errorId, vmeWriteElement()); // Send ECR errorId=vmeWriteElement(0x4, BASE_ADDRESS(TIM_SLOT_NUMBER)+0x2, sizeof(UINT16)); errorId=vmeWriteElement(0x0, BASE_ADDRESS(TIM_SLOT_NUMBER)+0x2, sizeof(UINT16)); ERROR_CHECK(errorId, vmeWriteElement()); // Enable Randomizer Sleep(50); // Wait to clear triggers errorId=vmeWriteElement(0x0040, BASE_ADDRESS(TIM_SLOT_NUMBER)+0x42, sizeof(UINT16)); errorId=vmeWriteElement(0x2A, BASE_ADDRESS(TIM_SLOT_NUMBER)+0x0, sizeof(UINT16)); ERROR_CHECK(errorId, vmeWriteElement()); break; case TIMP_SEND_BCR_2: // Stop Randomizer errorId=vmeWriteElement(0x0000, BASE_ADDRESS(TIM_SLOT_NUMBER)+0x42, sizeof(UINT16)); errorId=vmeWriteElement(0x0, BASE_ADDRESS(TIM_SLOT_NUMBER)+0x0, sizeof(UINT16)); Sleep(50); // Wait to clear triggers ERROR_CHECK(errorId, vmeWriteElement()); // Send BCR errorId=vmeWriteElement(0x8, BASE_ADDRESS(TIM_SLOT_NUMBER)+0x2, sizeof(UINT16)); errorId=vmeWriteElement(0x0, BASE_ADDRESS(TIM_SLOT_NUMBER)+0x2, sizeof(UINT16)); ERROR_CHECK(errorId, vmeWriteElement()); // Enable Randomizer Sleep(50); // Wait to clear triggers errorId=vmeWriteElement(0x0040, BASE_ADDRESS(TIM_SLOT_NUMBER)+0x42, sizeof(UINT16)); errorId=vmeWriteElement(0x2A, BASE_ADDRESS(TIM_SLOT_NUMBER)+0x0, sizeof(UINT16)); ERROR_CHECK(errorId, vmeWriteElement()); break; case TIMP_SET_CLK_1K: errorId=vmeWriteElement(0x0F16, BASE_ADDRESS(TIM_SLOT_NUMBER)+0x6, sizeof(UINT16)); SetCtrlVal(panel, TIMP_TRIG_FREQ, "1kHz"); ERROR_CHECK(errorId, vmeWriteElement()); break; case TIMP_SET_CLK_10K: errorId=vmeWriteElement(0x0F0E, BASE_ADDRESS(TIM_SLOT_NUMBER)+0x6, sizeof(UINT16)); SetCtrlVal(panel, TIMP_TRIG_FREQ, "10kHz"); ERROR_CHECK(errorId, vmeWriteElement()); break; case TIMP_SET_CLK_20K: errorId=vmeWriteElement(0x0F0B, BASE_ADDRESS(TIM_SLOT_NUMBER)+0x6, sizeof(UINT16)); SetCtrlVal(panel, TIMP_TRIG_FREQ, "20kHz"); ERROR_CHECK(errorId, vmeWriteElement()); break; case TIMP_SET_CLK_50K: errorId=vmeWriteElement(0x0F07, BASE_ADDRESS(TIM_SLOT_NUMBER)+0x6, sizeof(UINT16)); SetCtrlVal(panel, TIMP_TRIG_FREQ, "50kHz"); ERROR_CHECK(errorId, vmeWriteElement()); break; case TIMP_SET_CLK_100K: errorId=vmeWriteElement(0x0F06, BASE_ADDRESS(TIM_SLOT_NUMBER)+0x6, sizeof(UINT16)); SetCtrlVal(panel, TIMP_TRIG_FREQ, "100kHz"); ERROR_CHECK(errorId, vmeWriteElement()); break; case TIMP_SET_CLK_120K: errorId=vmeWriteElement(0x0F05, BASE_ADDRESS(TIM_SLOT_NUMBER)+0x6, sizeof(UINT16)); SetCtrlVal(panel, TIMP_TRIG_FREQ, "120kHz"); ERROR_CHECK(errorId, vmeWriteElement()); break; case TIMP_SET_CLK_150K: errorId=vmeWriteElement(0x0F04, BASE_ADDRESS(TIM_SLOT_NUMBER)+0x6, sizeof(UINT16)); SetCtrlVal(panel, TIMP_TRIG_FREQ, "150kHz"); ERROR_CHECK(errorId, vmeWriteElement()); break; case TIMP_SET_CLK_200K: errorId=vmeWriteElement(0x0F03, BASE_ADDRESS(TIM_SLOT_NUMBER)+0x6, sizeof(UINT16)); SetCtrlVal(panel, TIMP_TRIG_FREQ, "200kHz"); ERROR_CHECK(errorId, vmeWriteElement()); break; case TIMP_SET_CLK_300K: errorId=vmeWriteElement(0x0F02, BASE_ADDRESS(TIM_SLOT_NUMBER)+0x6, sizeof(UINT16)); SetCtrlVal(panel, TIMP_TRIG_FREQ, "300kHz"); ERROR_CHECK(errorId, vmeWriteElement()); break; case TIMP_WRITE_WORD: GetCtrlVal(panel, TIMP_WRITE_DATA_WORD, &value); errorId=vmeWriteElement(value, BASE_ADDRESS(TIM_SLOT_NUMBER)+relVmeAddress, sizeof(UINT16)); ERROR_CHECK(errorId, vmeWriteElement()); break; case TIMP_SEND_L1A: errorId=vmeWriteElement(0x2, BASE_ADDRESS(TIM_SLOT_NUMBER)+0x2, sizeof(UINT16)); errorId=vmeWriteElement(0x0, BASE_ADDRESS(TIM_SLOT_NUMBER)+0x2, sizeof(UINT16)); ERROR_CHECK(errorId, vmeWriteElement()); break; case TIMP_SETUP_SEQ: GetCtrlVal(panel, TIMP_L1A_QTY, &trigCount); GetCtrlVal(panel, TIMP_BC_QTY, &bcCount); // Reset TIM // errorId=vmeWriteElement(0x8000, BASE_ADDRESS(TIM_SLOT_NUMBER)+0x2, sizeof(UINT16)); // Reset Command // errorId=vmeWriteElement(0x0, BASE_ADDRESS(TIM_SLOT_NUMBER)+0x2, sizeof(UINT16)); // Clear CMND Reg // Clear Sequencer RAM for(i=0; i<0x1000; ++i){ errorId=vmeWriteElement(0x0, BASE_ADDRESS(TIM_SLOT_NUMBER)+0x8000+(i*2), sizeof(UINT16)); } // Load Sequencer RAM for(i=0; i