/******************************************************************************
 *
 *  Title  : uirUtility.c
 *  Version 0.0
 *
 *  Description: user interface utility routines.
 *
 *  Author: Lukas Tomasek, tomasekl@fzu.cz
 *
 ******************************************************************************/


/******************************************************************************
 *                              Header files                                  *
 ******************************************************************************/

#include <stdio.h>

#include "uirUtility.h"
#include "errorHandler.h"
#include "hostUtility.h"
#include "comRegDfns.h"
#include "globalDefinitions.h"
#include "fileUtility.h"
#include "timUir.h"
#include "fpgaUir.h"
#include "vmeHpiUtility.h"
#include "flashUtility.h"

#ifdef LAB_WINDOWS_CVI
#include <userint.h>
#include "mainUir.h"
#endif /* LAB_WINDOWS_CVI */

/******************************************************************************
 *                               Definitions                                  *
 ******************************************************************************/

/******************************************************************************
 *                                 Macros                                     *
 ******************************************************************************/

/*=============================================================================
 *                           displayRodStatusRegs()
 *=============================================================================
 *
 *
 *
 */
void displayRodStatusReg0(struct HOST *host) {

	ERROR_ID errorId=SUCCESS;
	int valueChanged;
	char errorMessage[200];
	int bit;
	int oldValue;
	int status;


	GetCtrlVal(host->panel.parent, ROD_ROD_STAT_REG0, &oldValue);

	if(host->rodStatusReg[0]!=oldValue){

		GET_AND_SET_CTRL_VAL(host->panel.parent, ROD_ROD_STAT_REG0, host->rodStatusReg[0], &oldValue);
		bit=(int) READ_BIT(host->rodStatusReg[0], SR_RUNNING);
		GET_AND_SET_CTRL_VAL(host->panel.parent, ROD_STAT_REG_0, bit, &oldValue);
		bit=(int) READ_BIT(host->rodStatusReg[0], SR_BUSY);
		GET_AND_SET_CTRL_VAL(host->panel.parent, ROD_STAT_REG_1, bit, &oldValue);
		bit=(int) READ_BIT(host->rodStatusReg[0], SR_EXECUTING);
		GET_AND_SET_CTRL_VAL(host->panel.parent, ROD_STAT_REG_2, bit, &oldValue);
		bit=(int) READ_BIT(host->rodStatusReg[0], SR_PAUSED);
		GET_AND_SET_CTRL_VAL(host->panel.parent, ROD_STAT_REG_3, bit, &oldValue);
		bit=(int) READ_BIT(host->rodStatusReg[0], SR_OUT_LIST_RDY);
		GET_AND_SET_CTRL_VAL(host->panel.parent, ROD_STAT_REG_4, bit, &oldValue);
		bit=(int) READ_BIT(host->rodStatusReg[0], SR_DSP_ACK);
		GET_AND_SET_CTRL_VAL(host->panel.parent, ROD_STAT_REG_5, bit, &oldValue);
		bit=(int) READ_BIT(host->rodStatusReg[0], SR_TXT_BUFF_NE(ERR_BUFF));
		GET_AND_SET_CTRL_VAL(host->panel.parent, ROD_STAT_REG_6, bit, &oldValue);
		bit=(int) READ_BIT(host->rodStatusReg[0], SR_TXT_BUFF_NE(INFO_BUFF));
		GET_AND_SET_CTRL_VAL(host->panel.parent, ROD_STAT_REG_7, bit, &oldValue);
		bit=(int) READ_BIT(host->rodStatusReg[0], SR_TXT_BUFF_NE(DIAG_BUFF));
		GET_AND_SET_CTRL_VAL(host->panel.parent, ROD_STAT_REG_8, bit, &oldValue);
		bit=(int) READ_BIT(host->rodStatusReg[0], SR_TXT_BUFF_NE(XFER_BUFF));
		GET_AND_SET_CTRL_VAL(host->panel.parent, ROD_STAT_REG_9, bit, &oldValue);

		bit=(int) READ_BIT(host->rodStatusReg[0], SR_DMA_ACCESS_ACK);
		GET_AND_SET_CTRL_VAL(host->panel.parent, ROD_STAT_REG_10, bit, &oldValue);
		bit=(int) READ_BIT(host->rodStatusReg[0], SR_DMA_ACCESS_ERR);
		GET_AND_SET_CTRL_VAL(host->panel.parent, ROD_STAT_REG_11, bit, &oldValue);

	}

	return;
}

/*=============================================================================
 *                             displayVmeCommandReg0()
 *=============================================================================
 *
 *
 */

void displayVmeCommandReg0(struct HOST *host){

	ERROR_ID errorId=SUCCESS;
	char errorMessage[200];
	int bit;
	int oldValue;
	int status;


	GET_AND_SET_CTRL_VAL(host->panel.parent, ROD_VME_COMM_REG0, host->vmeCommandReg[0], &oldValue);

	bit=(int) READ_BIT(host->vmeCommandReg[0], CR_IN_LIST_RDY);
	GET_AND_SET_CTRL_VAL(host->panel.parent, ROD_COMMAND_REG_0, bit, &oldValue);

	bit=(int) READ_BIT(host->vmeCommandReg[0], CR_PAUSE);
	GET_AND_SET_CTRL_VAL(host->panel.parent, ROD_COMMAND_REG_1, bit, &oldValue);
	bit=(int) READ_BIT(host->vmeCommandReg[0], CR_RESUME);
	GET_AND_SET_CTRL_VAL(host->panel.parent, ROD_COMMAND_REG_2, bit, &oldValue);

	bit=(int) READ_BIT(host->vmeCommandReg[0], CR_ABORT);
	GET_AND_SET_CTRL_VAL(host->panel.parent, ROD_COMMAND_REG_3, bit, &oldValue);

	bit=(int) READ_BIT(host->vmeCommandReg[0], CR_TXT_BUFF_RR(ERR_BUFF));
	GET_AND_SET_CTRL_VAL(host->panel.parent, ROD_COMMAND_REG_4, bit, &oldValue);
	bit=(int) READ_BIT(host->vmeCommandReg[0], CR_TXT_BUFF_RR(INFO_BUFF));
	GET_AND_SET_CTRL_VAL(host->panel.parent, ROD_COMMAND_REG_5, bit, &oldValue);
	bit=(int) READ_BIT(host->vmeCommandReg[0], CR_TXT_BUFF_RR(DIAG_BUFF));
	GET_AND_SET_CTRL_VAL(host->panel.parent, ROD_COMMAND_REG_6, bit, &oldValue);
	bit=(int) READ_BIT(host->vmeCommandReg[0], CR_TXT_BUFF_RR(XFER_BUFF));
	GET_AND_SET_CTRL_VAL(host->panel.parent, ROD_COMMAND_REG_7, bit, &oldValue);

	bit=(int) READ_BIT(host->vmeCommandReg[0], CR_DMA_ACCESS_REQ);
	GET_AND_SET_CTRL_VAL(host->panel.parent, ROD_COMMAND_REG_10, bit, &oldValue);

	return;

}

/*=============================================================================
 *                               viewBinFile()
 *=============================================================================
 *
 *
 *
 */

ERROR_ID viewBinFile(char fileName[PATHNAME_LENGTH]){

	ERROR_ID errorId;
	char viewFile[PATHNAME_LENGTH];
	long size;
	int status;

	strcpy(viewFile, global.mainDir);
	strcat(viewFile, BIN_VIEWER);
	strcat(viewFile, fileName);
	status = LaunchExecutable(viewFile);
	if(status!=0){
		programError(__FILE__, __LINE__, PROGRAM_ERROR, "LaunchExecutable()", status, "");
		return(PROGRAM_ERROR);
	}
	return(SUCCESS);
}
/*=============================================================================
 *                               loadTimRegFile()
 *=============================================================================
 *
 *
 *
 */
ERROR_ID loadTimRegFile(int panel, int index){

	int status;
	ERROR_ID errorId;
	char file[300];
	unsigned int fileSize;
	char *buffer;
	char string[300];

	/* load text file - reg. description */
	strcpy(file, global.mainDir);
	strcat(file, TIM_REG_TXT_FILE_SUBDIR);
	sprintf(string, "reg%d.txt", index);
	strcat(file, string);
	errorId=getFileSize (file, &fileSize);
	ERROR_CHECK(errorId, getFileSize());
	if(errorId!=SUCCESS) return(PROGRAM_ERROR);
	buffer=malloc(fileSize+1);
	if(buffer==NULL){
		ERROR_CHECK(PROGRAM_ERROR, malloc());
		return(PROGRAM_ERROR);
	}
	errorId=readFromBinFile(file, buffer, fileSize);
	ERROR_CHECK(errorId, getFileSize());
	if(errorId==SUCCESS){
		buffer[fileSize]='\0';
		status=ResetTextBox (panel, TIMP_TEXTBOX, buffer);
		UIR_STATUS_CHECK(status, ResetTextBox());
	}
	free(buffer);

	return(errorId);
}

/*=============================================================================
 *                               loadRodRegFile()
 *=============================================================================
 *
 *
 *
 */
ERROR_ID loadRodRegFile(int panel, int control, int registerBaseId){

	int status;
	ERROR_ID errorId;
	char file[300];
	long fileSize;
	char *buffer;
	char string[300];

	/* load text file - reg. description */
	strcpy(file, global.mainDir);
	strcat(file, ROD_REG_TXT_FILE_SUBDIR);
	sprintf(string, "regID_%X.txt", registerBaseId);
	strcat(file, string);
	status=GetFileSize (file, &fileSize);
	if(status==-1){
		/* no file exists - clear box */
		status=ResetTextBox (panel, control, "\0");
		UIR_STATUS_CHECK(status, ResetTextBox());
		return(SUCCESS);
	}
	if(status!=0){
		ERROR_CHECK(PROGRAM_ERROR, GetFileSize());
		return(PROGRAM_ERROR);
	}
	buffer=malloc(fileSize+1);
	if(buffer==NULL){
		ERROR_CHECK(PROGRAM_ERROR, malloc());
		return(PROGRAM_ERROR);
	}
	errorId=readFromBinFile(file, buffer, fileSize);
	ERROR_CHECK(errorId, getFileSize());
	if(errorId==SUCCESS){
		buffer[fileSize]='\0';
		status=ResetTextBox (panel, control, buffer);
		UIR_STATUS_CHECK(status, ResetTextBox());
	}
	free(buffer);

	return(errorId);
}

/*=============================================================================
 *                               updateBitField()
 *=============================================================================
 *
 *  update bits and current value fields in DSP monitor panel
 *
 */

void updateBitField(int panel) {
	UINT32 reg, value;
	

	GetCtrlVal(panel, DSPMONP_REGISTERS_RING_READ, &reg);
	switch (reg) {
		case STATUS_REG_0: GetCtrlVal(panel, DSPMONP_STATUS_REG_0, &value); break; 
		case STATUS_REG_1:  GetCtrlVal(panel, DSPMONP_STATUS_REG_1, &value); break;
		case STATUS_REG_2: GetCtrlVal(panel, DSPMONP_STATUS_REG_2, &value); break;
		case COMMAND_REG_0: GetCtrlVal(panel, DSPMONP_COMMAND_REG_0, &value); break;

		case DIAGNOSTIC_REG: GetCtrlVal(panel, DSPMONP_DIAGNOSTIC_REG, &value); break;
		case TRAPSTAT_REG_0: GetCtrlVal(panel, DSPMONP_TRAPSTAT_REG_0, &value); break;
		case TRAPSTAT_REG_1: GetCtrlVal(panel, DSPMONP_TRAPSTAT_REG_1, &value); break;
		case LOOP_REG: GetCtrlVal(panel, DSPMONP_LOOP_REG, &value); break;

		case HCMD_STAT_REG_0: GetCtrlVal(panel, DSPMONP_HCMD_STAT_REG_0, &value); break;
		case HCMD_STAT_REG_1: GetCtrlVal(panel, DSPMONP_HCMD_STAT_REG_1, &value); break;
		case HSTAT_REG_0: GetCtrlVal(panel, DSPMONP_HSTAT_REG_0, &value); break;
		case HSTAT_REG_1: GetCtrlVal(panel, DSPMONP_HSTAT_REG_1, &value); break;

		case RESERVED_REG_0: GetCtrlVal(panel, DSPMONP_RESERVED_REG_0, &value); break;
		case RESERVED_REG_1: GetCtrlVal(panel, DSPMONP_RESERVED_REG_1, &value); break;
		case RESERVED_REG_2: GetCtrlVal(panel, DSPMONP_RESERVED_REG_2, &value); break;
		case RESERVED_REG_3: GetCtrlVal(panel, DSPMONP_RESERVED_REG_3, &value); break;

		case RESERVED_REG_4: GetCtrlVal(panel, DSPMONP_RESERVED_REG_4, &value); break;
		case RESERVED_REG_5: GetCtrlVal(panel, DSPMONP_RESERVED_REG_5, &value); break;
		//dpsf case RESERVED_REG_6: GetCtrlVal(panel, DSPMONP_RESERVED_REG_6, &value); break;
		case TASK_STATE_REG: GetCtrlVal(panel, DSPMONP_TASK_STATE_REG, &value); break;

		case HCMD_REG: GetCtrlVal(panel, DSPMONP_HCMD_REG, &value); break;
		case TRAP_CMD_STAT: GetCtrlVal(panel, DSPMONP_TRAP_CMD_STAT, &value); break;
		//dpsf: case INTR_DSP_HSHK_WR: GetCtrlVal(panel, DSPMONP_INTR_DSP_HSHK_WR, &value); break;
		//dpsf: case INTR_DSP_HSHK_RD: GetCtrlVal(panel, DSPMONP_INTR_DSP_HSHK_RD, &value); break;
		default: break;
	}


	//SetCtrlVal(panel, DSPMONP_EDIT_FIELD, value);
	SetCtrlVal(panel, DSPMONP_CURR_VAL, value);
	SetCtrlVal(panel, DSPMONP_RBIT_0, READ_BIT(value, 0));
	SetCtrlVal(panel, DSPMONP_RBIT_1, READ_BIT(value, 1));
	SetCtrlVal(panel, DSPMONP_RBIT_2, READ_BIT(value, 2));
	SetCtrlVal(panel, DSPMONP_RBIT_3, READ_BIT(value, 3));
	SetCtrlVal(panel, DSPMONP_RBIT_4, READ_BIT(value, 4));
	SetCtrlVal(panel, DSPMONP_RBIT_5, READ_BIT(value, 5));
	SetCtrlVal(panel, DSPMONP_RBIT_6, READ_BIT(value, 6));
	SetCtrlVal(panel, DSPMONP_RBIT_7, READ_BIT(value, 7));
	SetCtrlVal(panel, DSPMONP_RBIT_8, READ_BIT(value, 8));
	SetCtrlVal(panel, DSPMONP_RBIT_9, READ_BIT(value, 9));
	SetCtrlVal(panel, DSPMONP_RBIT_10, READ_BIT(value, 10));
	SetCtrlVal(panel, DSPMONP_RBIT_11, READ_BIT(value, 11));
	SetCtrlVal(panel, DSPMONP_RBIT_12, READ_BIT(value, 12));
	SetCtrlVal(panel, DSPMONP_RBIT_13, READ_BIT(value, 13));
	SetCtrlVal(panel, DSPMONP_RBIT_14, READ_BIT(value, 14));
	SetCtrlVal(panel, DSPMONP_RBIT_15, READ_BIT(value, 15));
	SetCtrlVal(panel, DSPMONP_RBIT_16, READ_BIT(value, 16));
	SetCtrlVal(panel, DSPMONP_RBIT_17, READ_BIT(value, 17));
	SetCtrlVal(panel, DSPMONP_RBIT_18, READ_BIT(value, 18));
	SetCtrlVal(panel, DSPMONP_RBIT_19, READ_BIT(value, 19));
	SetCtrlVal(panel, DSPMONP_RBIT_20, READ_BIT(value, 20));
	SetCtrlVal(panel, DSPMONP_RBIT_21, READ_BIT(value, 21));
	SetCtrlVal(panel, DSPMONP_RBIT_22, READ_BIT(value, 22));
	SetCtrlVal(panel, DSPMONP_RBIT_23, READ_BIT(value, 23));
	SetCtrlVal(panel, DSPMONP_RBIT_24, READ_BIT(value, 24));
	SetCtrlVal(panel, DSPMONP_RBIT_25, READ_BIT(value, 25));
	SetCtrlVal(panel, DSPMONP_RBIT_26, READ_BIT(value, 26));
	SetCtrlVal(panel, DSPMONP_RBIT_27, READ_BIT(value, 27));
	SetCtrlVal(panel, DSPMONP_RBIT_28, READ_BIT(value, 28));
	SetCtrlVal(panel, DSPMONP_RBIT_29, READ_BIT(value, 29));
	SetCtrlVal(panel, DSPMONP_RBIT_30, READ_BIT(value, 30));
	SetCtrlVal(panel, DSPMONP_RBIT_31, READ_BIT(value, 31));

}


/*=============================================================================
 *                               refreshDspRegs()
 *=============================================================================
 *
 *  refreshFpgaStatus
 *
 */
#define  NUMBER_OF_DSP_REGS	  24

ERROR_ID refreshDspRegs(struct HOST *host){

	ERROR_ID errorId;
	UINT32 dspRegs[NUMBER_OF_DSP_REGS];
	int status;
	const int panel=host->panel.dspMonitor;
	unsigned int oldValue;
	unsigned int value;
	int dspType; /* MDSP=-1, Slave0=0, Slave1=1, Slave2=2, Slave3=3 */
	UINT32 address;
	unsigned int revision;

	GetCtrlVal(panel, DSPMONP_DSP_TYPE, &dspType);
	
	if(dspType==-1){ /* MDSP */
		
		errorId=RWmaster(READ, host->slotNumber, IDREGS_BASE, dspRegs, NUMBER_OF_DSP_REGS, HPIA_AUTOINCREMENT, 0);
		ERROR_CHECK(errorId, RWmaster(READ rodStatusRegs));
		if(errorId!=SUCCESS) return(errorId);
	
	}else{ /* slave */
	
		GetCtrlVal(host->panel.parent, ROD_ROD_REV, &revision);
		if(revision==0xE) address=0x00010000;
		else address=IDREGS_BASE;
		errorId=RWslave(READ, host->slotNumber, dspType, address, dspRegs, NUMBER_OF_DSP_REGS, 0);
		ERROR_CHECK(errorId, RWmaster(READ rodStatusRegs));
		if(errorId!=SUCCESS){
			return(errorId);
		}	
		
	}

	GET_AND_SET_CTRL_VAL(panel, DSPMONP_STATUS_REG_0, dspRegs[0], &oldValue);
	GET_AND_SET_CTRL_VAL(panel, DSPMONP_STATUS_REG_1, dspRegs[1], &oldValue);
	GET_AND_SET_CTRL_VAL(panel, DSPMONP_STATUS_REG_2, dspRegs[2], &oldValue);
	GET_AND_SET_CTRL_VAL(panel, DSPMONP_COMMAND_REG_0, dspRegs[3], &oldValue);

	GET_AND_SET_CTRL_VAL(panel, DSPMONP_DIAGNOSTIC_REG, dspRegs[4], &oldValue);
	GET_AND_SET_CTRL_VAL(panel, DSPMONP_TRAPSTAT_REG_0, dspRegs[5], &oldValue);
	GET_AND_SET_CTRL_VAL(panel, DSPMONP_TRAPSTAT_REG_1, dspRegs[6], &oldValue);
	GET_AND_SET_CTRL_VAL(panel, DSPMONP_LOOP_REG, dspRegs[7], &oldValue);

	GET_AND_SET_CTRL_VAL(panel, DSPMONP_HCMD_STAT_REG_0, dspRegs[8], &oldValue);
	GET_AND_SET_CTRL_VAL(panel, DSPMONP_HCMD_STAT_REG_1, dspRegs[9], &oldValue);
	GET_AND_SET_CTRL_VAL(panel, DSPMONP_HSTAT_REG_0, dspRegs[10], &oldValue);
	GET_AND_SET_CTRL_VAL(panel, DSPMONP_HSTAT_REG_1, dspRegs[11], &oldValue);

	GET_AND_SET_CTRL_VAL(panel, DSPMONP_RESERVED_REG_0, dspRegs[12], &oldValue);
	GET_AND_SET_CTRL_VAL(panel, DSPMONP_RESERVED_REG_1, dspRegs[13], &oldValue);
	GET_AND_SET_CTRL_VAL(panel, DSPMONP_RESERVED_REG_2, dspRegs[14], &oldValue);
	GET_AND_SET_CTRL_VAL(panel, DSPMONP_RESERVED_REG_3, dspRegs[15], &oldValue);

	GET_AND_SET_CTRL_VAL(panel, DSPMONP_RESERVED_REG_4, dspRegs[16], &oldValue);
	GET_AND_SET_CTRL_VAL(panel, DSPMONP_RESERVED_REG_5, dspRegs[17], &oldValue);
	GET_AND_SET_CTRL_VAL(panel, DSPMONP_RESERVED_REG_6, dspRegs[18], &oldValue);
	GET_AND_SET_CTRL_VAL(panel, DSPMONP_TASK_STATE_REG, dspRegs[19], &oldValue);

	GET_AND_SET_CTRL_VAL(panel, DSPMONP_HCMD_REG, dspRegs[20], &oldValue);
	GET_AND_SET_CTRL_VAL(panel, DSPMONP_TRAP_CMD_STAT, dspRegs[21], &oldValue);
	GET_AND_SET_CTRL_VAL(panel, DSPMONP_INTR_DSP_HSHK_WR, dspRegs[22], &oldValue);
	GET_AND_SET_CTRL_VAL(panel, DSPMONP_INTR_DSP_HSHK_RD, dspRegs[23], &oldValue);

	updateBitField(panel);

	return(errorId);
}

/*=============================================================================
 *                               refreshFpgaStatus()
 *=============================================================================
 *
 *  refreshFpgaStatus
 *
 */
#define ROUTER_STATUS(dspNumber) \
	errorId=RWmaster(READ, host->slotNumber, 0x00402400+0x40*(dspNumber), routerReg, NUMBER_OF_ROUTER_REG, HPIA_AUTOINCREMENT, 0);\
	ERROR_CHECK(errorId, RWmaster());\
	if(errorId!=SUCCESS) return(errorId);\
	GET_AND_SET_CTRL_VAL(panel, ROD_TRAP_EN_DSP##dspNumber, READ_BIT(routerReg[3], 0), &oldValue);/*TRAP_EN_DSP*/\
	if(routerReg[0]&0x20) value=8; else value=routerReg[0]&0x7;\
	GET_AND_SET_CTRL_VAL(panel, ROD_TRAP##dspNumber, value, &oldValue); /*Trap */\
	GET_AND_SET_CTRL_VAL(panel, ROD_TRAP_ON##dspNumber, READ_BIT(routerReg[3], 4), &oldValue); /*Trap  on*/\
	GET_AND_SET_CTRL_VAL(panel, ROD_TRAP_EF##dspNumber, READ_BIT(routerReg[3], 2), &oldValue); /*Trap  EF*/\
	GET_AND_SET_CTRL_VAL(panel, ROD_TRAP_FF##dspNumber, READ_BIT(routerReg[3], 3), &oldValue); /*Trap  FF*/\
	GET_AND_SET_CTRL_VAL(panel, ROD_TRAP_LD##dspNumber, READ_BIT(routerReg[3], 6), &oldValue); /*Trap  LD*/\
	GET_AND_SET_CTRL_VAL(panel, ROD_FORMAT##dspNumber, READ_BIT(routerReg[0], 6)*2+READ_BIT(routerReg[0], 3),&oldValue); /*Trap  LD*/


ERROR_ID refreshFpgaStatus(struct HOST *host){

#define  NUMBER_OF_ROD_CONTROLLER_REGS 6
#define  FPGA_STAT_ADDR           0x00404410
#define  NUMBER_OF_FE_MASK_REGS        4
#define  FE_MASK_ADDR             0x00404430
#define  NUMBER_OF_ROUTER_REG	  4

	ERROR_ID errorId;
	UINT32 fpgaStatusReg[NUMBER_OF_ROD_CONTROLLER_REGS];
	UINT32 feMaskReg[NUMBER_OF_FE_MASK_REGS];
	UINT32 routerReg[NUMBER_OF_ROUTER_REG];
	int status;
	const int panel=host->panel.parent;
	unsigned int oldValue;
	unsigned int value;

	// get FPGA status -
 	errorId=RWmaster(READ, host->slotNumber, FPGA_STAT_ADDR, fpgaStatusReg, NUMBER_OF_ROD_CONTROLLER_REGS, HPIA_AUTOINCREMENT, 0);
	ERROR_CHECK(errorId, RWmaster(fpgaStatusRegs));
	if(errorId!=SUCCESS) return(errorId);

	value=READ_BIT(fpgaStatusReg[5], 31);   // Pixel or SCT ROD
	GET_AND_SET_CTRL_VAL(panel, ROD_PIXEL_NOT_SCT, value, &oldValue);

	value=READ_BIT(fpgaStatusReg[0], 27);   // data path
	GET_AND_SET_CTRL_VAL(panel, ROD_DATA_PATH, value, &oldValue);

	GET_AND_SET_CTRL_VAL(panel, ROD_MODE, fpgaStatusReg[2]&0xF, &oldValue); // Rod Mode

	value=READ_BIT(fpgaStatusReg[0], 26);   // rod test path
	GET_AND_SET_CTRL_VAL(panel, ROD_TEST_PATH, value, &oldValue);
	
	value=READ_BIT(fpgaStatusReg[0], 18);   // 
	GET_AND_SET_CTRL_VAL(panel, ROD_CAL_SIGNAL_DEC, value, &oldValue);

	// FE CMD Output
	value=READ_BIT(fpgaStatusReg[0], 0);   // FE CMD OUT Enabled
	GET_AND_SET_CTRL_VAL(panel, ROD_FE_CMD_OUT, value, &oldValue);

	value=READ_BIT(fpgaStatusReg[0], 1);
	GET_AND_SET_CTRL_VAL(panel, ROD_MDSP_SP0, value, &oldValue); //MDSP_SP0 or TIM

	// get mask
 	errorId=RWmaster(READ, host->slotNumber, FE_MASK_ADDR, feMaskReg, NUMBER_OF_FE_MASK_REGS, HPIA_AUTOINCREMENT, 0);
	ERROR_CHECK(errorId, RWmaster(feMaskRegs));
	if(errorId!=SUCCESS) return(errorId);

	GET_AND_SET_CTRL_VAL(panel, ROD_MASK0_0, feMaskReg[0], &oldValue); //lower 32bits
	GET_AND_SET_CTRL_VAL(panel, ROD_MASK0_1, feMaskReg[1]&0xFFFF, &oldValue); //upper 16bits
	GET_AND_SET_CTRL_VAL(panel, ROD_MASK1_0, feMaskReg[2], &oldValue);  //lower 32bits
	GET_AND_SET_CTRL_VAL(panel, ROD_MASK1_1, feMaskReg[3]&0xFFFF, &oldValue);  //upper 16bits

	value=(!READ_BIT(fpgaStatusReg[0], 4))&&READ_BIT(fpgaStatusReg[0] , 5);   // FE CMD Pulse Counter Status
	GET_AND_SET_CTRL_VAL(panel, ROD_FE_CMD_PULSE_COUNT, value, &oldValue);

	value=(fpgaStatusReg[4]>>22)&0xFF ;   // FE CMD Pulse Counter 8bits
	GET_AND_SET_CTRL_VAL(panel, ROD_FE_CMD_PLS_COUNTER, value, &oldValue);

	value=READ_BIT(fpgaStatusReg[0], 3);   // FE Occupancy Counters
	GET_AND_SET_CTRL_VAL(panel, ROD_FE_OCCUP, value, &oldValue);

	value=READ_BIT(fpgaStatusReg[4], 30);   // FE Occupancy Counters All Zero
	GET_AND_SET_CTRL_VAL(panel, ROD_ALL_ZERO, value, &oldValue);
	
	value=READ_BIT(fpgaStatusReg[4], 31);   // Cmd mask ready
	GET_AND_SET_CTRL_VAL(panel, ROD_CMD_MASK_READY, value, &oldValue);
	

	value=(!READ_BIT(fpgaStatusReg[0], 7))&&READ_BIT(fpgaStatusReg[0] , 8);   // Trigger Signal Decoder
	GET_AND_SET_CTRL_VAL(panel, ROD_TRG_SIGNAL_DEC, value, &oldValue);

	value=(!READ_BIT(fpgaStatusReg[0], 9))&&READ_BIT(fpgaStatusReg[0] , 10);  // Formatter ModeBit Encoder
	GET_AND_SET_CTRL_VAL(panel, ROD_FORM_MB, value, &oldValue);

	value=READ_BIT(fpgaStatusReg[4] , 8);  // FIFO 0 full
	GET_AND_SET_CTRL_VAL(panel, ROD_FIFO_0_FULL, value, &oldValue);

	value=READ_BIT(fpgaStatusReg[4] , 10);  // FIFO 1 full
	GET_AND_SET_CTRL_VAL(panel, ROD_FIFO_1_FULL, value, &oldValue);

	// header trailer limit
	value=READ_BIT(fpgaStatusReg[4] , 11); // HT limit form 0
	GET_AND_SET_CTRL_VAL(panel, ROD_HT_LIMIT_0, value, &oldValue);
	value=READ_BIT(fpgaStatusReg[4] , 12); // HT limit form 1
	GET_AND_SET_CTRL_VAL(panel, ROD_HT_LIMIT_1, value, &oldValue);

	// ROD busy
	value=READ_BIT(fpgaStatusReg[4] , 13); // busy form 0
	GET_AND_SET_CTRL_VAL(panel, ROD_ROD_BUSY_0, value, &oldValue);
	value=READ_BIT(fpgaStatusReg[4] , 14); // busy form 0
	GET_AND_SET_CTRL_VAL(panel, ROD_ROD_BUSY_1, value, &oldValue);

	value=(!READ_BIT(fpgaStatusReg[0], 11))&&READ_BIT(fpgaStatusReg[0] , 12);  // EFB DynMask Encoder
	GET_AND_SET_CTRL_VAL(panel, ROD_EFB_DM, value, &oldValue);

	value=READ_BIT(fpgaStatusReg[4] , 16);  // FIFO full
	GET_AND_SET_CTRL_VAL(panel, ROD_FIFO_EFB_FULL, value, &oldValue);
	
	value=READ_BIT(fpgaStatusReg[4] , 17);  // Event ID Empty Error
	GET_AND_SET_CTRL_VAL(panel, ROD_EVID_ERROR, value, &oldValue);

	value=(!READ_BIT(fpgaStatusReg[0], 15))&&READ_BIT(fpgaStatusReg[0] , 16);  //Test Bench I/O
	GET_AND_SET_CTRL_VAL(panel, ROD_TEST_BENCH, value, &oldValue);

	value=READ_BIT(fpgaStatusReg[0], 17);  //Test Bench I/O Run
	GET_AND_SET_CTRL_VAL(panel, ROD_TEST_BENCH_RUN, value, &oldValue);

	// EM fifo
	value=READ_BIT(fpgaStatusReg[4] , 18); // EM fifo 0 empty
	GET_AND_SET_CTRL_VAL(panel, ROD_EM_EMPTY_0, value, &oldValue);
	value=READ_BIT(fpgaStatusReg[4] , 19); // EM fifo 0 full
	GET_AND_SET_CTRL_VAL(panel, ROD_EM_FULL_0, value, &oldValue);
	value=READ_BIT(fpgaStatusReg[4] , 20); // EM fifo 1 empty
	GET_AND_SET_CTRL_VAL(panel, ROD_EM_EMPTY_1, value, &oldValue);
	value=READ_BIT(fpgaStatusReg[4] , 21); // EM fifo 1 full
	GET_AND_SET_CTRL_VAL(panel, ROD_EM_FULL_1, value, &oldValue);

	value=(!READ_BIT(fpgaStatusReg[0], 24))&&READ_BIT(fpgaStatusReg[0] , 25); //Debug FIFO I/O
	GET_AND_SET_CTRL_VAL(panel, ROD_DEBUG_FIFO, value, &oldValue);

	// FIFO enable
	value=(!READ_BIT(fpgaStatusReg[1], 0))&&(!READ_BIT(fpgaStatusReg[1], 1))&&(!READ_BIT(fpgaStatusReg[1], 2)); //Form MB/EFB DM
	GET_AND_SET_CTRL_VAL(panel, ROD_FORM_MB_EFB, value, &oldValue);

	value=!READ_BIT(fpgaStatusReg[1], 7); //Corrective Trigger
	GET_AND_SET_CTRL_VAL(panel, ROD_CORR_TRIGGER, value, &oldValue);

	value=(!READ_BIT(fpgaStatusReg[1], 4))&&(!READ_BIT(fpgaStatusReg[1], 5)); //DEBUG_MEM
	GET_AND_SET_CTRL_VAL(panel, ROD_DEBUG_MEM, value, &oldValue);

	value=!READ_BIT(fpgaStatusReg[1], 3); //IN_MEM
	GET_AND_SET_CTRL_VAL(panel, ROD_IN_MEM, value, &oldValue);


	value=(!READ_BIT(fpgaStatusReg[1], 6)); //INTERNAL_TIM
	GET_AND_SET_CTRL_VAL(panel, ROD_INTERNAL_TIM, value, &oldValue);

	//Router status
	ROUTER_STATUS(0); // DSP0
	ROUTER_STATUS(1); // DSP1
	ROUTER_STATUS(2); // DSP2
	ROUTER_STATUS(3); // DSP3

	return(errorId);
}
/*=============================================================================
 *                               displayCmdListExecBusy()
 *=============================================================================
 *
 *
 *
 */

void displayCmdListExecBusy(struct HOST *host){

	int status;
	int value=host->cmdListExecState|host->primListReady;

	SetCtrlVal(host->panel.commandListStatus, CLISTP_BUSY, value);
	switch(host->slotNumber){
		case 5 : SetCtrlVal(global.panel.main, MAIN_CMDLISTEXEC_5,  value); break;
		case 6 : SetCtrlVal(global.panel.main, MAIN_CMDLISTEXEC_6,  value); break;
		case 7 : SetCtrlVal(global.panel.main, MAIN_CMDLISTEXEC_7,  value); break;
		case 8 : SetCtrlVal(global.panel.main, MAIN_CMDLISTEXEC_8,  value); break;
		case 9 : SetCtrlVal(global.panel.main, MAIN_CMDLISTEXEC_9,  value); break;
		case 10: SetCtrlVal(global.panel.main, MAIN_CMDLISTEXEC_10, value); break;
		case 11: SetCtrlVal(global.panel.main, MAIN_CMDLISTEXEC_11, value); break;
		case 12: SetCtrlVal(global.panel.main, MAIN_CMDLISTEXEC_12, value); break;
		case 13: SetCtrlVal(global.panel.main, MAIN_CMDLISTEXEC_13, value); break;
		case 14: SetCtrlVal(global.panel.main, MAIN_CMDLISTEXEC_14, value); break;
		case 15: SetCtrlVal(global.panel.main, MAIN_CMDLISTEXEC_15, value); break;
		case 16: SetCtrlVal(global.panel.main, MAIN_CMDLISTEXEC_16, value); break;
		case 17: SetCtrlVal(global.panel.main, MAIN_CMDLISTEXEC_17, value); break;
		case 18: SetCtrlVal(global.panel.main, MAIN_CMDLISTEXEC_18, value); break;
		case 19: SetCtrlVal(global.panel.main, MAIN_CMDLISTEXEC_19, value); break;
		case 20: SetCtrlVal(global.panel.main, MAIN_CMDLISTEXEC_20, value); break;
		case 21: SetCtrlVal(global.panel.main, MAIN_CMDLISTEXEC_21, value); break;

	}

	return;

}

/*=============================================================================
 *                               updateFlashPanelState()
 *=============================================================================
 *
 *
 *
 */


#define UPDATE_SIZES(controlName) \
		GetCtrlVal(panel, controlName##_FILE, fileName);\
		status=GetFileSize (fileName, &fileSize);\
		if(status!=0){\
			return -1;\
		}\
		SetCtrlVal(panel, controlName##_SIZE, fileSize);\
		GetCtrlVal(panel, controlName##_START_ADDR, &address);\
		/* last addr */\
		if(fileSize>0) address+=fileSize-1;\
		SetCtrlVal(panel, controlName##_END_ADDR, address);\


ERROR_ID updateFlashPanelState (int panel){

	int status;
	ERROR_ID errorId;
	long fileSize;
	char fileName[PATHNAME_LENGTH];

	UINT32 mdspAddr, address;
	UINT32 numSectors;

	UPDATE_SIZES(PAN_FLASH_LOCATION);
	UPDATE_SIZES(PAN_FLASH_RRIF);
	UPDATE_SIZES(PAN_FLASH_FORM);
	UPDATE_SIZES(PAN_FLASH_EFB);
	UPDATE_SIZES(PAN_FLASH_ROUTER);

	GetCtrlVal(panel, PAN_FLASH_DSP_PRG_FILE, fileName);

	status=GetFileSize (fileName, &fileSize);
	if(status!=0){
		return -1;
	}
	SetCtrlVal(panel, PAN_FLASH_DSP_PRG_SIZE, fileSize);

	GetCtrlVal(panel, PAN_FLASH_DSP_PRG_START_ADDR, &mdspAddr);
	/* last addrr */
	mdspAddr+=fileSize-1;
	SetCtrlVal(panel, PAN_FLASH_DSP_PRG_END_ADDR, mdspAddr);
	

	return SUCCESS;


}


/******************************************************************************/