#if (defined(SIM))
#ifndef SIMULATION_H	 /* multiple inclusion protection */
#define SIMULATION_H
#include "memoryPartitions.h"

void simPreInit(void);  //Runs before the main initialization routine.
void simInit1(void);    //For quick tests
void simSetup(void);    //performs setup of the async interrupt
void simInit(void);     //More simulation setup.

//Check for actions which are taken by the FPGAs on certain register accesses:
void simFpgaCheck(UINT8 fRead, UINT32 reg, UINT32 wid, UINT32 bit, UINT32 val);

//Arm the simulation routines so that the will simulate passage of an 'event':
void simTriggerArm(UINT32 sdsp);

/* Two macros which allow pausing & resuming the DSP timers quickly (these
   are faster than the CSL function calls TIMER_pause/resume). */
#define pauseTimer(i)   (*((UINT32 *) (0x01940000 +(i<<18)))&= ~0x80);
#define resumeTimer(i)  (*((UINT32 *) (0x01940000 +(i<<18)))|=  0x80);

#if (defined(I_AM_MASTER_DSP))
	//Inlined versions of the SDSP comm. register fxns:
	static inline uint32 getSdspRegI(UINT32 sdsp, UINT32 addr) {
		uint32 *sdspAddr;
		//the mask removes any part of the address which is > 32 words:
		sdspAddr= (UINT32 *) (SIM_SDSP_REG_BASE(sdsp) +(addr & 0x7f));
		return *sdspAddr;
	}
#endif

#endif   /* Multiple inclusion protection */
#endif