/************************************************************************************* * memoryPartitions.h * * synopsis: Defines the memory partitions in the DSP memory space. * Declares routine for initializing memory. * Should be included in the DSP and the VME host code. * * In Project->Options->Compiler it is POSSIBLE to define * TI_EVM: EVM DSP has smaller SDRAMs than the ROD DSPs. This option partitions * memory accordingly. * MAP_0: probably never used, ROD DSPs are wired for MAP_1, see peripherals * manual 10-5 * SIM: If defined, handles some aspects of the DSP's environment (for SDSPs, * this is the MDSP's responses to their communication register settings; * for the MDSP this is the host's & SDSPs' responses. * * Damon Fasching, UW Madison fasching@wisconsin.cern.ch * Douglas Ferguson, UW Madison (510) 486-5230 dpferguson@lbl.gov * * modifications/bugs * - Updated to reflect changes in the project organization. When BIOS was * introduced, the program memory sections must be defined inside the config * database; the MEMORY section of the linker command file is no longer used & * is taken out. External code & data are combined and put the XPROG memory * section (FARDATA gone). The default positions and sizes of the 4 text, and * the primitive & reply buffers, have changed. 6701s now have 32M of external * memory; 6201 still has 16M. 26.04.02 dpsf * * n.b. Bios has now been removed as it is memory hungry & not * essential. dpsf * * - Inter-DSP communication buffers put in SDRAM & communication registers moved * to the beginning of internal memory (IDREG segment in the configuration * database file) The 2 handshake registers have been left in internal memory * with the other registers. A new section of memory, IDATA, has been created * for important program variables; they should now remain relatively fixed in * one spot instead of floating about in the program IDRAM while code is added * & modified, as they did before. This is intended to be used with the * DATA_SECTION pragma (see Optimizing C Compiler User's Guide, 7.6.4). Use of * the pragma makes variables inaccessible to routines in other files, so * use with care. (They can still be accessed by calling a function to return a * pointer to them). 05.06.02 dpsf * * - Added EXPERT, HCMD, HSTAT, TRAPREQ & TRAPSTAT registers for general purpose * use, histogramming, and event trapping respectively. New defined locations in * memory were added for the (suggested) base in memory of histograms & the * trapping buffer as well. 20.06.02 dpsf * * - New memory section MODULE_DATA was added for storage of new module * configuration structures on the master. 03.07.02 dpsf * * - Master & slave DSPs now have different size primitive & reply buffers. The * compilation constants HOST_(PRM/REP)_BFR_(BASE/SZ) in memoryPartitions.h have * been replaced with different sets for the two DSP types. 10.12.02 dpsf * * - Removed unused options such as COMPACT compilation flag & DSP * map 0 (ROD will use Map 1 only). 22.02.04 dpsf * * - Re-organization for use with the new ROD memory map & cleanup. 02.03.04 dpsf ************************************************************************************* * NOTE: The segment sizes defined in this file for use in positioning registers and * other program items (which are not explicitly declared as variables) must * agree with the corresponding memory segment length and base, set in the * linker command file. **Otherwise overwrites are possible** The memory order of * the segments defined there should be maintained as well. These segment sizes are: * * IDREGS_SZ, IDATA_SZ, IDRAM_MEM_SZ, BURST_SZ, XPROG_SZ, and * (master only) MODULE_DATA_SZ * * IDRAM_SZ is the total size of the DSP IDRAM. * (IDRAM_MEM is used here for the memory section IDRAM in the linker command file). ************************************************************************************/ #ifndef MEMORY_PARTITIONS #define MEMORY_PARTITIONS #include "processor.h" /* * On the Rev. B & C RODs, each DSP has 0x10000 bytes (64K) of internal program memory, * IPRAM, starting at 0x0, and 0x10000 bytes of internal data memory, IDRAM, starting * at 0x80000000 and 0x1000000 bytes (16M) SDRAM starting at 0x2000000 or 0x3000000. * On a Rev. E ROD, the SDSPs have a total of 256 KB internal memeory, which is shared * between program code & data, and 128 MB memory located on two of the CE spaces. The * MDSP is the same as the one on the previous revisions. * * Some of this is used for buffers and communication mailboxes whose addresses and * sizes are defined below. * * table of available memory spaces * Rev. B or C: * * mem space base address what's there for each device * * MAP 1 EVM MDSP SDSPs * EMIF CE0 0x00400000 256KB SBSRAM FPGA registers ------ * EMIF CE1 0x01400000 boot ROM router * EMIF CE2 0x02000000 4MB SDRAM 16MB SDRAM 16MB SDRAM * EMIF CE3 0x03000000 4MB SDRAM 16MB SDRAM * IPRAM 0x00000000 64KB internal program memory * IDRAM 0x80000000 64KB intermal data memory * * Rev. E or F SDSP (MDSP same as above): * MAP 1 SDSPs * EMIF CE0 0x80000000 ------ * EMIF CE1 0x90000000 router * EMIF CE2 0xA0000000 128 MB SDRAM * EMIF CE3 0xB0000000 128 MB SDRAM * IP/IDRAM 0x00000000 256 KB internal memory */ /************************************************************************************ * Base addresses of the available memories ************************************************************************************/ /* internal program, internal data and 4 EMIF chip enables for off chip memories */ #if defined(I_AM_MASTER_DSP) #define CE0_BASE (0x00400000) #define CE1_BASE (0x01400000) #define IPRAM_BASE (0x00000000) #define CE2_BASE (0x02000000) #define CE3_BASE (0x03000000) #define IDRAM_BASE (0x80000000) #endif #define SDSP_CE0_BASE_REVBC (0x00400000) #define SDSP_CE1_BASE_REVBC (0x01400000) #define SDSP_IPRAM_BASE_REVBC (0x00000000) #define SDSP_CE2_BASE_REVBC (0x02000000) #define SDSP_CE3_BASE_REVBC (0x03000000) #define SDSP_IDRAM_BASE_REVBC (0x80000000) #define SDSP_CE0_BASE_REVE (0x80000000) #define SDSP_CE1_BASE_REVE (0x90000000) #define SDSP_IPRAM_BASE_REVE (0x00000000) #define SDSP_CE2_BASE_REVE (0xa0000000) #define SDSP_CE3_BASE_REVE (0xb0000000) #define SDSP_IDRAM_BASE_REVE ((SDSP_IPRAM_BASE_REVE) +(SDSP_IPRAM_SZ_REVE)) #if defined(I_AM_SLAVE_DSP) #if (defined(REV_B)||defined(REV_C)) #define CE0_BASE (SDSP_CE0_BASE_REVBC) #define CE1_BASE (SDSP_CE1_BASE_REVBC) #define IPRAM_BASE (SDSP_IPRAM_BASE_REVBC) #define CE2_BASE (SDSP_CE2_BASE_REVBC) #define CE3_BASE (SDSP_CE3_BASE_REVBC) #define IDRAM_BASE (SDSP_IDRAM_BASE_REVBC) #elif defined(REV_E) #define CE0_BASE (SDSP_CE0_BASE_REVE) #define CE1_BASE (SDSP_CE1_BASE_REVE) #define IPRAM_BASE (SDSP_IPRAM_BASE_REVE) #define SRAM_BASE (0x00000000) #define CE2_BASE (SDSP_CE2_BASE_REVE) #define CE3_BASE (SDSP_CE3_BASE_REVE) #define IDRAM_BASE (SDSP_IDRAM_BASE_REVE) #endif #endif /* SDRAM: EVM has 2 4MB SDRAMs at CE2 and CE3; ROD has 16 MB SDRAM at CE2 + another 16M at CE3 for 6701s */ #ifdef TI_EVM #define SDRAM0_BASE (CE2_BASE) #define SDRAM1_BASE (CE3_BASE) #else #if defined(I_AM_MASTER_DSP) #define SDRAM0_BASE (CE2_BASE) #define SDRAM1_BASE ((CE2_BASE) + (SDRAM0_SZ)) #endif #define SDSP_SDRAM0_BASE_REVBC (SDSP_CE2_BASE_REVBC) #define SDSP_SDRAM1_BASE_REVBC (SDSP_CE3_BASE_REVBC) #define SDSP_SDRAM0_BASE_REVE (SDSP_CE2_BASE_REVE) #define SDSP_SDRAM1_BASE_REVE (SDSP_CE3_BASE_REVE) #if defined(I_AM_SLAVE_DSP) #if (defined(REV_B)||defined(REV_C)) #define SDRAM0_BASE (SDSP_SDRAM0_BASE_REVBC) #define SDRAM1_BASE (SDSP_SDRAM1_BASE_REVBC) #elif defined(REV_E) #define SDRAM0_BASE (SDSP_SDRAM0_BASE_REVE) #define SDRAM1_BASE (SDSP_SDRAM1_BASE_REVE) #endif #endif #endif /* The master DSP has a boot ROM at CE1; slaves each have a router FIFO */ #ifndef TI_EVM #if (defined(I_AM_MASTER_DSP) || defined(I_AM_HOST)) #define BOOT_ROM_BASE (CE1_BASE) #define BOOT_ROM_SZ (0x80000) /* boot ROM is 512K */ #elif (defined(I_AM_SLAVE_DSP)) #define ROUTER_FIFO_BASE (CE1_BASE) #define ROUTER_FIFO_SZ (0x1000) /* 1K words */ #endif #endif /************************************************************************************* * Sizes of the available memories. ************************************************************************************/ #if defined(I_AM_MASTER_DSP) /* 64KB of internal program memory and 64KB of internal data memory */ #define IPRAM_SZ (0x10000) #define IDRAM_SZ (0x10000) #define CE1_SZ (0x80000) #endif #define SDSP_IPRAM_SZ_REVBC (0x10000) #define SDSP_IDRAM_SZ_REVBC (0x10000) #define SDSP_IPRAM_SZ_REVE (0x10000) #define SDSP_IDRAM_SZ_REVE (0x10000) #if defined(I_AM_SLAVE_DSP) #if (defined(REV_B)||defined(REV_C)) #define IPRAM_SZ (SDSP_IPRAM_SZ_REVBC) #define IDRAM_SZ (SDSP_IDRAM_SZ_REVBC) #elif defined(REV_E) #define IPRAM_SZ (SDSP_IPRAM_SZ_REVE) #define IDRAM_SZ (SDSP_IDRAM_SZ_REVE) #endif #endif #if (defined(I_AM_SLAVE_DSP)&&defined(REV_E)) #define SRAM_SZ_NO_CACHE (0x40000) #define SRAM_SZ_16K_CACHE (0x3c000) #define SRAM_SZ_32K_CACHE (0x38000) #define SRAM_SZ_48K_CACHE (0x34000) #define SRAM_SZ_64K_CACHE (0x30000) #endif #ifdef TI_EVM #define SDRAM0_SZ (0x400000) #define SDRAM1_SZ (0x400000) #else #if defined(I_AM_MASTER_DSP) /* 16 MB of SDRAM available on the ROD divided into two halves both on CE2 */ #define SDRAM0_SZ (0x800000) #define SDRAM1_SZ (0x800000) #endif /* Rev. B & C: 16 MB of SDRAM on CE2 & CE3. Rev. E: 128 MB SDRAM. */ #define SDSP_SDRAM_SZ_REVBC 0x01000000 #define SDSP_SDRAM_SZ_REVE 0x08000000 #if defined(I_AM_SLAVE_DSP) #if (defined(REV_B)||defined(REV_C)) #define SDRAM0_SZ (SDSP_SDRAM_SZ_REVBC) #define SDRAM1_SZ (SDSP_SDRAM_SZ_REVBC) #elif defined(REV_E) #define SDRAM0_SZ (SDSP_SDRAM_SZ_REVE) #define SDRAM1_SZ (SDSP_SDRAM_SZ_REVE) #endif #endif #endif /************************************************************************************ * IDRAM items ************************************************************************************ * IDREGS_SZ bytes of IDRAM are reserved for communications registers. * * IDATA_SZ bytes are reserved for important variables for which it's desirable they * be kept (for monitoring) in a fixed location. Note that this method has a * minor drawback in that the variables become 'far' data objects. To access them * they must be declared "extern far", and the access will be slightly slower. * * IDRAM_MEM_SZ bytes are reserved for the linker to place general heap, stack and * 'near' data objects (arrays and structures which are not declared * 'far'). * * BURST_SZ bytes of IDRAM are reserved for the program to store data for immediate * use. On the slaves it is a temporary store for data retrieved from the * router FPGA via DMA. This data typically is processed and added to histograms * being accumulated in the SDRAM. On the master it typically is a temporary store * for data being transmitted to the front end electronics. * * **** THESE SIZES MUST BE THE SAME AS THE LENGTH PARAMETER OF THE CORRESPONDING * MEMORY SECTION IN THE LINKER COMMAND FILE **** * * NOTE: If the memory section sizes are mistaken, the error will sometimes be caught * by the compiler at compile time. Another check is done at run time inside * checkMemBounds.c. Most larger data objects like the primitive buffers, text * buffers, and external burst buffers do not have variables and memory segments * declared for them; for these the space is 'virtually' allocated here and checked * in chekMemBounds.c * */ #if defined(I_AM_MASTER_DSP) #define IDREGS_SZ (0x0080) #define IDATA_SZ (0x0800) #define IDRAM_MEM_SZ (0x7780) #define BURST_SZ (0x8000) #endif #define SDSP_IDREGS_SZ (0x0080) #define SDSP_IDATA_SZ (0x0800) #define SDSP_IDRAM_MEM_SZ (0x7780) #define SDSP_BURST_SZ_REVBC (0x8000) #define SDSP_BURST_SZ_REVE (0x8000) #if defined(I_AM_SLAVE_DSP) #define IDREGS_SZ (SDSP_IDREGS_SZ) #define IDATA_SZ (SDSP_IDATA_SZ) #define IDRAM_MEM_SZ (SDSP_IDRAM_MEM_SZ) #if (defined(REV_B)||defined(REV_C)) #define BURST_SZ (SDSP_BURST_SZ_REVBC) #elif defined(REV_E) #define BURST_SZ (SDSP_BURST_SZ_REVE) #endif #endif #define IDREGS_BASE (IDRAM_BASE) #define IDATA_BASE ((IDREGS_BASE) + (IDREGS_SZ)) /* IDRAM_BASE is kept for the physical memory base: */ #define IDRAM_MEM_BASE ((IDATA_BASE) + (IDATA_SZ)) #define BURST_BFR_BASE ((IDRAM_MEM_BASE) + (IDRAM_MEM_SZ)) #define IDRAM_ALLOCATED ((IDREGS_SZ)+(IDATA_SZ)+(IDRAM_MEM_SZ)+(BURST_SZ)) /************************************************************************************ * SDRAM0 items ************************************************************************************ *** THIS MUST BE THE SAME AS THE LENGTH PARAMETER OF MEMORY SECTION XPROG IN * THE LINKER COMMAND FILE. *****/ #if defined(I_AM_MASTER_DSP) #define XPROG_SZ (0x40000) #endif #define SDSP_XPROG_SZ (0x40000) #if defined(I_AM_SLAVE_DSP) #define XPROG_SZ (SDSP_XPROG_SZ) #endif /* The ERR, INFO, DIAG and XFER buffers are the text buffers for sending messages * upstream to the host processor. Slave text buffers are communicated to the host * via the master XFER buffer. The XFER buffer is not used on the slaves. * The HOST_PRM and HOST_REP buffers are for primitive lists from the host and the * associated reply data. Host to slave primitive and associated reply data are * transferred via the master DSP. The inter-DSP transfer buffers are small buffers * used for sending simple primitive lists from DSP to DSP (master to slave and * vice-versa). Note that in COMPACT mode the buffers are actually in IDRAM. */ #define TXT_BFR_SZ (0x8000) #define INTR_DSP_PRM_BFR_SZ (0x800) #define INTR_DSP_REP_BFR_SZ (0x800) #if (defined(I_AM_MASTER_DSP) || defined(I_AM_HOST)) #define MDSP_PRM_BFR_SZ (0x50000) #define MDSP_REP_BFR_SZ (0x50000) #endif #define SDSP_PRM_BFR_SZ (0x20000) #define SDSP_REP_BFR_SZ (0x20000) #if ( (defined(I_AM_MASTER_DSP)) || (defined(I_AM_HOST)) \ || (defined(I_AM_SLAVE_DSP)&&(defined(REV_B)||defined(REV_C))) ) #define ERR_BFR_BASE ((SDRAM0_BASE) + (XPROG_SZ)) #define INFO_BFR_BASE ((ERR_BFR_BASE) + (TXT_BFR_SZ)) #define DIAG_BFR_BASE ((INFO_BFR_BASE) + (TXT_BFR_SZ)) #define XFER_BFR_BASE ((DIAG_BFR_BASE) + (TXT_BFR_SZ)) #define END_TEXT_BUFF ((XFER_BFR_BASE) + (TXT_BFR_SZ)) #define INTR_DSP_PRM_BFR_BASE_SND (END_TEXT_BUFF) #define INTR_DSP_REP_BFR_BASE_SND ((INTR_DSP_PRM_BFR_BASE_SND)+(INTR_DSP_PRM_BFR_SZ)) #define INTR_DSP_PRM_BFR_BASE_PRC ((INTR_DSP_REP_BFR_BASE_SND)+(INTR_DSP_REP_BFR_SZ)) #define INTR_DSP_REP_BFR_BASE_PRC ((INTR_DSP_PRM_BFR_BASE_PRC)+(INTR_DSP_PRM_BFR_SZ)) #define END_IDSP_BUFF ((INTR_DSP_REP_BFR_BASE_PRC)+(INTR_DSP_PRM_BFR_SZ)) #define FREEMEM0_BASE (END_IDSP_BUFF) #define FREEMEM0_SZ 0x0000 #elif (defined(I_AM_SLAVE_DSP)&&defined(REV_E)) #define ERR_BFR_BASE ((SDRAM0_BASE) + (XPROG_SZ)) #define INFO_BFR_BASE ((ERR_BFR_BASE) + (TXT_BFR_SZ)) #define DIAG_BFR_BASE ((INFO_BFR_BASE) + (TXT_BFR_SZ)) #define XFER_BFR_BASE ((DIAG_BFR_BASE) + (TXT_BFR_SZ)) #define END_TEXT_BUFF ((XFER_BFR_BASE) + (TXT_BFR_SZ)) #define INTR_DSP_PRM_BFR_BASE_SND (END_TEXT_BUFF) #define INTR_DSP_REP_BFR_BASE_SND ((INTR_DSP_PRM_BFR_BASE_SND)+(INTR_DSP_PRM_BFR_SZ)) #define INTR_DSP_PRM_BFR_BASE_PRC ((INTR_DSP_REP_BFR_BASE_SND)+(INTR_DSP_REP_BFR_SZ)) #define INTR_DSP_REP_BFR_BASE_PRC ((INTR_DSP_PRM_BFR_BASE_PRC)+(INTR_DSP_PRM_BFR_SZ)) #define END_IDSP_BUFF ((INTR_DSP_REP_BFR_BASE_PRC)+(INTR_DSP_PRM_BFR_SZ)) #define FREEMEM0_BASE (END_IDSP_BUFF) #define FREEMEM0_SZ 0x0000 #endif #if (defined(I_AM_MASTER_DSP) || defined(I_AM_HOST)) #define MDSP_PRM_BFR_BASE ((FREEMEM0_BASE) + (FREEMEM0_SZ)) #define MDSP_REP_BFR_BASE ((MDSP_PRM_BFR_BASE) + (MDSP_PRM_BFR_SZ)) #define CMD_BUFFER_BASE ((MDSP_REP_BFR_BASE) + (MDSP_REP_BFR_SZ)) #define CMD_BUFFER_SZ 0x8000 #define SDRAM0_FREE_BASE ((CMD_BUFFER_BASE) +(CMD_BUFFER_SZ)) #endif #define SDSP_PRM_BFR_BASE ((FREEMEM0_BASE) + (FREEMEM0_SZ)) #define SDSP_REP_BFR_BASE ((SDSP_PRM_BFR_BASE) + (SDSP_PRM_BFR_SZ)) #if (defined(I_AM_SLAVE_DSP)) #define XBURST_BFR_BASE ((SDSP_REP_BFR_BASE)+(SDSP_REP_BFR_SZ)) #define XBURST_BFR_SZ (0x38000) #define BURST_BFR_RESERVED_BASE ((XBURST_BFR_BASE) +(XBURST_BFR_SZ)) #define BURST_BFR_RESERVED_SZ (0x8000) #define HISTOGRAM_DEFAULT_BASE ((BURST_BFR_RESERVED_BASE) +(BURST_BFR_RESERVED_SZ)) #define HISTOGRAM_DEFAULT_BASE_1 (CE3_BASE) #if (defined(REV_B) || defined(REV_C)) #define FIT_DEFAULT_BASE 0x03c00000 //4 MB before memory top. #elif (defined(REV_E)) #define FIT_DEFAULT_BASE 0xb7400000 //4 MB before memory top. #endif #endif #if defined(I_AM_MASTER_DSP) #define SDRAM0_ALLOCATED ((SDRAM0_FREE_BASE) -(SDRAM0_BASE)) #elif defined(I_AM_SLAVE_DSP) #define SDRAM0_ALLOCATED ((HISTOGRAM_DEFAULT_BASE) -(SDRAM0_BASE)) #endif #define MODULE_DATA_BASE 0x02400000 #if defined(SCT_ROD) #define MODULE_DATA_SZ 0x00080000 /* .5 MB */ #elif defined(PIXEL_ROD) #define MODULE_DATA_SZ 0x00b00000 /* 11 MB */ #endif /* default position for trapped events is in high memory: whereas the burst buffers are always needed for trapping events, this is potentially reserved memory for gathering trapped events; it is intended to be a suggestion when running the event trapping task. */ #if (defined(I_AM_MASTER_DSP) || defined(I_AM_HOST)) #define SLV_SDRAM1_BASE (0x03000000) #define SLV_SDRAM1_SZ (0x01000000) /* needed by VME host */ #define EVENT_TRAP_DEFAULT_SZ (0x20000) #define EVENT_TRAP_DEFAULT_BASE ((SLV_SDRAM1_BASE) +(SLV_SDRAM1_SZ) \ -(EVENT_TRAP_DEFAULT_SZ)) #else #define EVENT_TRAP_DEFAULT_SZ (0x20000) #define EVENT_TRAP_DEFAULT_BASE ((SDRAM1_BASE) +(SDRAM1_SZ) \ -(EVENT_TRAP_DEFAULT_SZ)) #endif /* SDRAM1: Free space for application defined data on SCT RODs; for Pixel RODs the module database takes up the last 4 MB of SDRAM0 & the first 7 MB of SDRAM1 (see above) & the upper 1 MB is free space. (this is handled by memory sections now). */ #define SDRAM1_FREE_BASE (SDRAM1_BASE) #define SDRAM1_ALLOCATED 0 #if defined(TI_EVM) /* need a histogram base for SDRAM1 */ #define HISTOGRAM_BASE1 ((SDRAM1_BASE) +(0x40000)) #endif /************************************************************************************ * Rod FPGA memory mapped items from CE0 (FPGA area simulated during simulation): ************************************************************************************/ #if defined(I_AM_MASTER_DSP) /* base address for memory mapped registers and FIFOs */ #define REG_BASE (CE0_BASE) /* offsets into each device These are FPGA-centric offsets, i.e. from the MDSP point of view they need to be left shifted 2 bits (words -> bytes). This is done where needed in the files containing the access routines. */ #define FMT_BASE (0x0) #define EFB_BASE (0x800) #define RTR_BASE (0x900) #define RCF_BASE (0x1000) #define FIFO_BASE (0x1800) #define BOC_BASE (0x2000) #define SDSP_BASE (0xE0000) #define LED_OFFSET 0x100 #define HEARTBEAT_ADR ((UINT32 *)(((RCF_BASE + LED_OFFSET) << 2) + REG_BASE)) /* If simulating the ROD, the SDSP communication registers and other memory sections must be simulated- these are put in some extra memory allocated by the GEL mapSet6201 function 1 MB above the FPGA register base (CE0). */ #define SIM_SDSP_REG_BASE(sdsp) (REG_BASE +0x100000 -0xa0*4 +0xa0*(sdsp)) #define SIM_SDSP_IMEM_BASE(sdsp) (REG_BASE +0x100000 +0x40000*(sdsp)) #define SIM_SDSP_XMEM0_BASE(sdsp) (REG_BASE +0x200000 +0x200000*(sdsp)) //For items in high SDSP CE0 or CE1 memory. Note that these memories wrap. #define SIM_SDSP_XMEM1_BASE(sdsp) (REG_BASE +0xa00000 +0x100000*(sdsp)) #elif defined(I_AM_SLAVE_DSP) #define ROUTER_FIFO_ADDR (CE1_BASE) #endif #endif