/************************************************************************************ * the event manager control structure: Set of basic variables within the event * manager. Many of these registers are set * asynchronously by the DMA ISR, and thus should only be monitored within other * routines unless there are special reasons to do so (like a frame buffer overflow). * The fixed parameters FRAME_SIZE and FRAMES_PER_BLOCK define the structure of * the frame sets. The frame size is the size of frame transfers from the router; * this is now fixed. While the # of frames per block can be changed if appropriate * adjustments are made to the burst buffer lengths, doing so would require extensive * changes to other areas as well (such as the event queue structure and the frame * set registers. It would also defeat the word-boundary design of these registers, * making them harder to access & much harder to monitor. * * Fields: * * running: Indicates whether the event manager is running or not. * isrState: The current state of the ISR (NEWEVENT, DATA, or SLOWDATA). * eventFrameCount: The number of frames in the current event. * format: The event data format (TRAP_FMT_NORMAL or TRAP_FMT_ERROR). * * i/xFrameCount: The number of currently occupied (valid) frames in the internal * and external frame buffers. * i/xFrameRelease: When frames are released after the event has been processed, * these variables tell the ISR (the next time it runs) how many * frames to release from the frame buffers. * * update: Indicates to the non-ISR frame updating code that the ISR ran while * it was still occupied releasing an event's frames, and that it should * subtract the values used by the ISR from the frame release variables. * This prevents conflicts between the ISR & the rest of the code. * i/xFrameUpdate: If the ISR runs while non-ISR code was busy releasing frames, it * places the values it actually used in updating the buffer frame * counts, and will expect that the non-ISR code will modify the * frame-release counts accordingly, so that the next time it runs * the correct variables are used. * * cf: Points to the internal buffer frame in which the next data from the router * will be placed. * xcf: After a frame arrives, if all internal frames are currently full with valid * data, xcf point to the frame inside the external burst buffer, to which the * frame will be transferred. The internal buffer frame is then left unused, so * that it can receive the next frame. * releaseFrames: Indicates whether the event manager should release frames for * re-use as soon as the last pending operation has finished with * them. If data processing is frame-based and incoming events arrive frequently, * or events can be very large (histogramming), this helps to avoid buffer * overflows. * permitBackPressure: Used by the master DSP to set the router control bit which * allows it to apply back-pressure to the EFB, typically done * in calibration mode. It is sent on to the slaves as a flag. * * headerError: Flag indicating a serious error. If set, the DMA ISR expected a * header but found other data instead. The event manager will halt. * * overflow: If all frames in the internal & external frame buffers are occupied, * and a new frame arrives, the ISR will enter an overflow state. When * this occurs, it will dump any more frames which arrive while it is in overflow. * Exit from the overflow state is only possible when all the frames in external * memory have been processed. * endOverflow: Flag which signals the ISR that it can resume normal processing. * framesLost: Countains the total number of frames which were discarded while the * ISR was in overflow. * * sLink: Indicates that the router is in sLink mode. (Trap matching is * overridden; data is passed on to DSPs using only the modulus & * remainder formula). In this case trap 0's function ID (input to eventTrapSetup) * is used to indicate the tasks which should process the trapped events. * dataMode: Indicates that the router is set in data mode instead of event mode. * Frames cannot be counted on to always begin on a frame boundary, and * the router does not send data until it has accumulated 0x100 words. * autoFlush: Diagnostic bit which instructs the event manager to automatically * flush the frame buffers once they fill up, even if the frames are * not yet processed. * trapStray: Flag indicating whether or not "stray" events (see below) are * marked for trapping on the iteration past the limit, or are * removed. * * strayCount: The number of stray events seen so far. Should be small and get * incremented infrequently, so this wraps at 256. * nTrailerWords: Indicates the number of words in the event trailer (depends on * the event format). * * asmGuard: Protection for the assembly language routines which use the C * structures (the routines check the value of this word & exit if * an unexpected value is found). * buffPtr[2]: Pointers to the start of the internal & external frame buffers * buffLen[2]: The length of the internal & external frame buffers. * lastFrameWordPtr: Points to the trailer marker word in the current frame. * queuePtr: Pointer to the start of the event queue. * * trapParams[2]: A set of six variables in a structure, indicating what is * being done with the router's two trap registers: * * config: The configuration of the trap, ie. what sort of events is it * trapping, if any. Types can be TRAP_CFG_(ATLAS,TIM, or ROD)_EVT, * or TRAP_CFG_IDLE for none. If only one trap is used, it must be trap #0. * * match: The 8 bit event ID which triggers the trap, if the remainder in * the modulus/remainder register agrees with the current remainder. * * exclusionFlag: If set, the trap will match anything *but* what is set in * the trap match register. Currently not implemented. * * function: The function(s) of this trap, ie. what task(s) will handle it. * The functions are additive and are defined in primParams.h * * modulus/remainder: Determine the frequency of event trapping inside the * router. If an event matches the trap's match, then it * will be sent on to the SDSP if (# matches)%(modulus) == remainder. * Note that the router VHDL requires that the 1st event passed on have * a remainder of 1. * * nEventsTot: The total number of events which have been collected since * initialization. * frameCount: The number of times the ISR has been called. * nOverflowEvents: The number of events which have been lost in overflow. * eventLimit: The number of events to collect. 0 means continue until stopped. * * conflict: The number of times the frame release code has been interrupted * by the ISR. * noConflict: The number of times the frame release code has run without any * conflict. * reserveDataLen: The size of data (in words) inside the event manager's * reserve buffer. Once here, the data cannot be taken out. It * is for stray event observation only. The reserve buffer cannot hold large * events (>32k); these are discarded. * reserveDataPtr: Pointer to the current writing frame in the reserve data * buffer. This 32 frame buffer in external memory wraps like * the other two, and will over-write any data in it if necessary. * * ---------------------------------------------------------------------------------- * the event queue: organizes the trapped events. Event Manager routines transfer * events to and from different sub-queues within the event queue, * deleting an event when it has no more operations pending, and freeing up its * frames for re-filling. This sub-structure of the event queue contains the * actual event data. To avoid any possible conflicts between the asynchronous ISR * and the routines which manage the queue, the queue is structured as a FIFO. The * routines have control over reading from and pointing of the front end of the * pipe, while the ISR controls writing to the back end. * * EvtData Fields (8 words per event): * * data1: Packed data word containing the starting frame and # of frames in both * the internal & external frame buffers. Fields are defined below. * data2: Packed data word containing the event length and flags which indicate * if the event contains errors and which tasks will process it. * data3: Packed data word containing the frame numbers of the last two event * frames, for easy access to the end of the event. * * unpacked data. To be removed: * i/xStartFrame, i/xFrameCount, error, length. * startFrame: The frame in which the event begins. This is not necessarily * constant, but could move if an overflow occurs. The starting frame * is in the burst buffer if startFrame= [0,31]; startFrame= [32,63] indicates * the first external burst buffer, etc. (up to 7) * * nFrames: The number of frames in the event. * * flags: Four event flags: bit 0== contiguous, bit 1= wrapped, bit 2= not * contained within one frame set (32 frames or 32K), bit 7= exception * frame release flag. Contiguous means that the event's frames are all in * ascending order in one or two groups (nice). Wrapped means that the event * arrived at the end of burst memory in the 31st frame. The DMA engine then * resets, so if free frames are available in the beginning of the buffer, the * next frames will go there. If an event is wrapped and finds enough space at * the beginning of the buffer to complete there, it is also marked as contiguous. * If the high bit is set, then the closing operation of the event has requested * that the event manager clean up the frames (if release_frames is set, see * above.) * * id: The internal id number assigned to the event, as shown in the * frameSummary registers. * * nErrors: Count of the number of errors inside the event; obtained from * the event fragment trailer. * * routerError: Indicates a router error. * * not used: * type: The type of the trapped event, as given by either fragment header * word 7 for ATLAS events, or a field in word 8 for ROD & TIM events. * * * operations: The scheduled operations for the trapped event; one bit per * operation. The bits are the same as are given for the queue * constants below. (Q_HISTOGRAM, etc.) * * opsPending: The pending operations for the trapped event; one bit per * operation. * EvtQueue Fields: * * nEvents: The total number of events in the queue. * readPtr: Points to the queue start (current output of the pipe). * writePtr: Points to the queue end (current input to the pipe). * * EvtData eventData[0x100]: The queue's event data structure array. * * Douglas Ferguson ************************************************************************************/ #ifndef EVENT_MANAGER_STRUCT #define EVENT_MANAGER_STRUCT #include "memoryPartitions.h" #include "router.h" #if (defined(I_AM_SLAVE_DSP)&&(defined(REV_B)||defined(REV_C))) #include #endif //Event Manager structures & defined constants #define FRAME_SIZE 0x100 /* in words */ #define FRAMES_PER_BLOCK 32 /* 1 block == 1 event set */ #if (defined(REV_E)) #define EDMA_BURST_ID 4 //The CIPR/CIER IDs of the burst DMA interrupt. #endif struct EvtMgrCtrl { UINT8 running, isrState, eventFrameCount, format, iFrameCnt, xFrameCnt, iFrameMax, xFrameMax, headerError, overflow, xMinIdx, xMaxIdx, sLink, dataMode, releaseFrames, permitBackPressure, autoFlush, trapStray, strayCount, nTrailerWords, pin4MaskDown, iFrameThres, cf, xcf, intOnly, unused[3]; /* Important to keep the locations of the following pointers relative to the start of the structure fixed (they are used in assemby language, which does not know about C structure specifics, and can only be give a pointer to the start of the structure). */ UINT32 asmGuard, *buffPtr[2], buffLen[2], *lastFrameWordPtr; UINT32 *queuePtr; RouterTrapParams trapParams[2]; UINT32 nEventsTot, frameCount, nOverflowEvents, nOverflowFrames, eventLimit, reserveDataLen, reserveDataPtr, unused1[3]; }; struct EventData { UINT32 data1, data2, data3; UINT8 iStartFrame, iFrameCnt, xStartFrame, xFrameCnt, error, unused; UINT16 length; UINT8 startFrame, nFrames, flags, id; UINT32 nErrors, routerError; }; /* Data1 definition. Each field is 8 bits wide: */ #define EVT_MGR_IFRAME_O 24 #define EVT_MGR_IFCNT_O 16 #define EVT_MGR_XFRAME_O 8 #define EVT_MGR_XFCNT_O 0 /* Data2 definition: */ #define EVT_MGR_OVERFLOW_O 31 #define EVT_MGR_EVT_ERR_O 30 #define EVT_MGR_HEADER_ERR_O 29 #define EVT_MGR_TRAILER_ERR_O 28 #define EVT_MGR_DATA_ERR_O 27 #define EVT_MGR_LINK_ERR_O 26 /* The trapping mask is used by the task manager to decide whether a given task will process this event or not. It contains 1 bit per potential task */ #define EVT_MGR_TRAP_O 16 #define EVT_MGR_TRAPMASK 0x001f0000 #define EVT_MGR_TRAP_FXN_HISTOGRAM 0 #define EVT_MGR_TRAP_FXN_TRAP 1 #define EVT_MGR_TRAP_FXN_OCCUPANCY 2 #define EVT_MGR_TRAP_FXN_ERRORCNT 3 #define EVT_MGR_TRAP_FXN_RESYNCH 4 #define EVT_MGR_EVTLEN_O 0 #define EVT_MGR_EVTLEN_W 16 /* Data3 definition. Data3 has 2 8-bit fields that contain the last two event frames in an event. The last frame= current frame buffer frame when event ends; the previous frame is gotten from the stored value of data3 before it is updated. */ #define EVT_MGR_CFRAME_O 24 #define EVT_MGR_LFRAME_O 16 struct EventQueue { UINT8 nEvents, readPtr, writePtr, unused; struct EventData eventData[0x100]; }; #define OBSERVATION_STRAY_MASK 0x40 #if defined(I_AM_SLAVE_DSP) //Inlined event manager functions: extern far struct EvtMgrCtrl evtMgrCtrl; #if (defined(REV_B)||defined(REV_C)) extern DMA_Handle hBurstDataDmaCh; extern DMA_Config burstDmaConfig; #endif static inline void eventManager(void); static inline void setDmaRegs(UINT8 frame); /************************************************************************************ * eventManager * * synopsis: After the tasks have finished processing the events, the event * manager handles frame release & other cleanup tasks. The routine is * written as an inlined routine to avoid the overhead of a function * call. * * author: Douglas Ferguson ************************************************************************************/ static inline void eventManager() { } /************************************************************************************ * setDmaRegs * * synopsis: Rev. B and C RODs use a 32 frame DMA transfer with pin 4 interrupts * at the beginning of each frame, and a reload from 2 global reload * registers at the end of the whole transfer, which reload the DMA registers. * After transferring a frame, the frame counter and destination pointer of the * DMA engine have automatically decremented (by 1 frame) & incremented (to the * starting address of the next frame); if the DMA counters must be manually set, * we must be careful to set the number of remaining frames to transfer correctly. * For a Rev. E ROD (using EDMA), it is different: interrupts are only possible * after a transfer has completed, so we must use single frame transfers. The * element count will reload from the EDMA channel's reload register (which assumes * the function of the global count reload register). The destination address will * not increment automatically to the start of the next frame, nor will it wrap, * so these functions are accomplished manually. * * author: Douglas Ferguson ************************************************************************************/ static inline void setDmaRegs(UINT8 frame) { #if (defined(REV_B)||defined(REV_C)) /* Transfer counter: number of frames and number of elements per frame */ burstDmaConfig.src= ROUTER_FIFO_ADDR; burstDmaConfig.dst= (BURST_BFR_BASE +(frame<<10)); burstDmaConfig.xfrcnt= DMA_XFRCNT_RMK((FRAMES_PER_BLOCK-frame), FRAME_SIZE); DMA_config(hBurstDataDmaCh, &burstDmaConfig); #elif (defined(REV_E)) /* Set the source of the frame transfer (EDMA evt 4) directly, for speed. The EDMA event is linked to channel 4. See the EDMA chapter in the TMS320C6000 Peripherals Reference Guide for more details. */ *((UINT32 *) 0x01a0006c)= BURST_BFR_BASE +(frame<<10); #endif return; } #endif /* SDSP */ #endif /* Multiple inclusion protection. */