#include #include #include "resources.h" /* The serial port handles are declared outside the function for access by the primitives & routines that process serial data */ MCBSP_Handle serPort0Handle, serPort1Handle; #pragma CODE_SECTION(initSerialPorts, "xcode"); /************************************************************************************ * initSerialPorts: * * synopsis: (MDSP) Initialize the two serial ports on the MDSP for comunication * to the controller FPGA. The serial streams are used to configure or * control the front end SCT and Pixel chips. This interface can also be used to * send trigger commands to the front ends. The two master DSP serial ports are * initialized; after initialization they will be transmitting the content of the * 32b transmit data registers over and over. It contains zero so the output will * be in the low state. Some receiver pins are used as GPIO: CLKRP0 => yellow LED, * CLKRP1 => green LED, and FSRP0 => red LED. * * (SDSP) The serial ports are used (both receive & transmit) for GPIO: * FSXP0 & FSRP0 are general purpose, CLKXP1 => yellow LED, CLKXP0 => enable the * router, and DXSTAT1 => set the ext. pin 4 mask (forces router to wait while the * DSP finishes the ISR routine). * * modifications: * - Enable general purpose i/o the receiver (RIOEN= 1); the CHIP-ENABLE signal * in now ported in through the serial ports (on both dr0 & dr1) & reads/writes * to the slave's HPI poll this before proceeding. 05.11.02 dpsf * - The SDSP initSlaveMcbsp routine has been renamed to initSerialPorts, * and both routines put in the same file. ************************************************************************************/ #if defined(I_AM_MASTER_DSP) void initSerialPorts(void) { UINT32 pcr[2], rcr, xcr, srgr, xcer, mcr, spcr, rcer; /* register init values */ /* get port 0 and 1 handles for use with the chip support libary calls */ serPort0Handle= MCBSP_open(MCBSP_DEV0, MCBSP_OPEN_RESET); serPort1Handle= MCBSP_open(MCBSP_DEV1, MCBSP_OPEN_RESET); /* define the Pin Control Register values: the reason there are two is so that the red LED is controlled by the state of FSR1 only (if either serial port's FSR is high, the LED is on). */ pcr[0]= MCBSP_PCR_RMK( /* PCR make value call */ 0x0, /* XIOEN: CLKS is input and DX is output */ 0x1, /* RIOEN: DR and CLKR pins are general purpose i/o */ 0x1, /* FSXM: frame sync frm sample rate generator */ 0x1, /* FSRM: FSR is used as general purpose output */ 0x1, /* CLKXM: CLKX is output driven by sample rate generator */ 0x1, /* CLKRM: CLKR is used as general purpose output */ 0x0, /* CLKS_STAT: not used satus of CLKS pin */ 0x0, /* DXSTAT: not used status of DX pin */ 0x0, /* FSXP: frame sync pulse is active high */ 0x1, /* FSRP: general purpose output */ 0x0, /* CLKXP: transmit on rising edge */ 0x1 /* CLKRP: general purpose output */ ); pcr[1]= MCBSP_PCR_RMK( /* PCR make value call */ 0x0, /* XIOEN: CLKS is input and DX is output */ 0x1, /* RIOEN: DR and CLKR pins are general purpose i/o */ 0x1, /* FSXM: frame sync frm sample rate generator */ 0x1, /* FSRM: FSR is used as general purpose output */ 0x1, /* CLKXM: CLKX is output driven by sample rate generator */ 0x1, /* CLKRM: CLKR is used as general purpose output */ 0x0, /* CLKS_STAT: not used satus of CLKS pin */ 0x0, /* DXSTAT: not used status of DX pin */ 0x0, /* FSXP: frame sync pulse is active high */ 0x0, /* FSRP: general purpose output */ 0x0, /* CLKXP: transmit on rising edge */ 0x1 /* CLKRP: general purpose output */ ); /* define the Reciever Control Register values (disabled) */ rcr= MCBSP_RCR_RMK(0,0,0,0, 0,0,0,0); /* define the Transmit Control Register values */ xcr= MCBSP_XCR_RMK( /* XCR make value call */ 0x0, /* XPHASE single phase frame */ 0x0, /* XFRLEN2 not used one word per phase */ 0x0, /* XWDLEN2 not used 8b per phase */ 0x0, /* XCOMPAND not used MSB first */ 0x1, /* XFIG unexpected frame sync ignored */ 0x0, /* XDATADLY zero bit delay */ 0x0, /* XFRLEN1 one word per phase */ 0x5 /* XWDLEN1 transmit length 32b */ ); /* define the Sample Rate Generator Register values */ srgr= MCBSP_SRGR_RMK( /* SRGR make value call */ 0x0, /* GSYNC rising edge CLKS generates CLKG and FSG */ 0x0, /* CLKSP rising edge CLKS drives CLKG and FSG */ 0x0, /* CLKSM sample rate gen clk is CLKS */ 0x0, /* FSGM tram frame sync is from sample rate generator */ 0x1F, /* FPER frame width is 32 bits */ 0x0, /* FWID frame pulse FSG is 1 clk40 wide */ 0x0 /* CLKGDV devide clk40 by 1 */ ); /* define the multichannel Transmit Channel Enable Register value (disabled) */ xcer= MCBSP_XCER_RMK(0x0000, 0x0000); /* define the multichannel Reciever Channel Enable Register value (disabled) */ rcer= MCBSP_RCER_RMK(0x0000, 0x0000); /* define the Multchannel Control Register (disabled) */ mcr= MCBSP_MCR_RMK(0,0,0,0,0,0); /* define the Serial Port Control Register value */ spcr= MCBSP_SPCR_RMK( /* SPCR make value call */ 0x1, /* FRST frame sync is on */ 0x1, /* GRST reset of sample rate generater is off */ 0x3, /* XINTM generated by XSYCERR */ 0x0, /* XSYNCERR transmission error bit */ 0x1, /* XRST enable transmitter */ 0x0, /* DLB digital loopback mode disabled */ 0x0, /* RJUST not used right justified, zero fill */ 0x0, /* CLKSTP clock stop mode disabled */ 0x3, /* RINTM gen RSYNERR, RSYNCERR is off */ 0x0, /* RSYNCERR receiver error bit */ 0x0 /* RRST serial port receiver is reset */ ); /* set up serial ports and start transmitting data*/ MCBSP_configArgs(serPort0Handle, spcr, rcr, xcr, srgr, mcr, rcer, xcer, pcr[0]); MCBSP_configArgs(serPort1Handle, spcr, rcr, xcr, srgr, mcr, rcer, xcer, pcr[1]); return; } /************************************************************************************/ #elif defined(I_AM_SLAVE_DSP) void initSerialPorts(void){ UINT32 pcr[2], rcr, xcr, srgr, xcer, mcr, spcr, rcer; /* SP registers */ /* get port 0 and 1 handles for use with the chip support library calls */ serPort0Handle= MCBSP_open(MCBSP_DEV0, MCBSP_OPEN_RESET); serPort1Handle= MCBSP_open(MCBSP_DEV1, MCBSP_OPEN_RESET); /* define the Pin Control Register values */ pcr[0]= MCBSP_PCR_RMK( /* PCR make value call */ 0x1, /* XIOEN: Transmitter pins are used for gen. purpose I/O */ 0x1, /* RIOEN: Receiver pins are used for GPIO */ 0x1, /* FSXM FSX0 is a GPIO output. */ 0x1, /* FSRM FSR0 is a GPIO output. */ 0x1, /* CLKXM: CLKX is output driven by CLKXP */ 0x0, /* CLKRM not used: reciever clk input */ 0x0, /* CLKSSTAT not used: status of CLKS pin */ 0x0, /* DXSTAT drives DX pin (not used) */ 0x0, /* FSXP GPIO */ 0x0, /* FSRP GPIO */ 0x0, /* CLKXP GPIO output: inital value 0 (1=> trigger router) */ 0x0 /* CLKRP not used: sample on falling edge */ ); pcr[1]= MCBSP_PCR_RMK( /* PCR make value call */ 0x1, /* XIOEN: Transmitter pins are used for GPIO */ 0x1, /* RIOEN: Receiver pins are used for GPIO */ 0x1, /* FSXM FSX1 is a GPIO output. */ 0x0, /* FSRM FSR1 is a GPIO input. */ 0x1, /* CLKXM: CLKX is output driven by CLKXP */ 0x0, /* CLKRM not used: reciever clk input */ 0x0, /* CLKSSTAT not used: status of CLKS pin */ 0x0, /* DXSTAT drives DX pin (always output in GPIO): init 0 note: this is used to mask interrupts from the router. */ 0x0, /* FSXP not used: transmit frame sync polarity is active high */ 0x0, /* FSRP signal from RCF */ 0x1, /* CLKXP GPIO output: Rev. B/C yellow LED (inverted) */ 0x0 /* CLKRP not used: sample on falling edge */ ); /* define the Receiver Control Register values (disabled) */ #if (defined(REV_B)||defined(REV_C)) rcr= MCBSP_RCR_RMK(0,0,0,0, 0,0,0,0); #elif (defined(REV_E)) rcr= MCBSP_RCR_RMK(0,0,0,0, 0,0,0,0, 0); #endif /* define the Transmit Control Register values (disabled) */ #if (defined(REV_B)||defined(REV_C)) xcr= MCBSP_XCR_RMK(0,0,0,0, 0,0,0,0); #elif (defined(REV_E)) xcr= MCBSP_XCR_RMK(0,0,0,0, 0,0,0,0, 0); #endif /* define the Sample Rate Generator Register values (disabled) */ srgr= MCBSP_SRGR_RMK(0,0,0,0, 0,0,0); /* define the multichannel Transmit Channel Enable Register value (disabled) */ xcer= MCBSP_XCER_RMK(0x0000, 0x0000); /* define the multichannel Reciever Channel Enable Register value (disabled) */ rcer= MCBSP_RCER_RMK(0x0000, 0x0000); /* define the Multchannel Control Register (disabled) */ mcr= MCBSP_MCR_RMK(0,0,0,0,0,0); #if (defined(REV_B)||defined(REV_C)) spcr= MCBSP_SPCR_RMK( /* SPCR make value call */ 0x0, /* FRST not used: frame sync is on */ 0x0, /* GRST not used: reset of sample rate generater is off */ 0x0, /* XINTM not used: generated by XSYCERR, XSYCER is off */ 0x0, /* XSYNCERR transmission error bit */ 0x0, /* XRST: enable gen pur I/O when XION=1 */ 0x0, /* DLB not used: digital loopback mode disabled */ 0x0, /* RJUST not used: right justified, zero fill */ 0x0, /* CLKSTP not used: clock stop mode disabled */ 0x0, /* RINTM not used: gen RSYNERR, RSYNCERR is off */ 0x0, /* RSYNCERR receiver error bit */ 0x0 /* RRST serial port receiver is reset */ ); #elif (defined(REV_E)) spcr= MCBSP_SPCR_RMK( /* SPCR make value call */ 0x0, /* FREE not used: free running mode is determined by SOFT*/ 0x0, /* SOFT not used: will halt SP on an emulation halt */ 0x0, /* FRST not used: frame sync is on */ 0x0, /* GRST not used: reset of sample rate generater is off */ 0x0, /* XINTM not used: generated by XSYCERR, XSYCER is off */ 0x0, /* XSYNCERR transmission error bit */ 0x0, /* XRST: enable gen pur I/O when XION=1 */ 0x0, /* DLB not used: digital loopback mode disabled */ 0x0, /* RJUST not used: right justified, zero fill */ 0x0, /* CLKSTP not used: clock stop mode disabled */ 0x0, /* DXENA not used: DX Enabler is off */ 0x0, /* RINTM not used: gen RSYNERR, RSYNCERR is off */ 0x0, /* RSYNCERR receiver error bit */ 0x0 /* RRST serial port receiver is reset */ ); #endif /* set up serial ports and start transmitting data*/ MCBSP_configArgs(serPort0Handle, spcr, rcr, xcr, srgr, mcr, rcer, xcer, pcr[0]); MCBSP_configArgs(serPort1Handle, spcr, rcr, xcr, srgr, mcr, rcer, xcer, pcr[1]); return; } #endif