/************************************************************************************ * initEmif.c * * synopsis: Initialization routine for the EMIF. Will initialize for the MDSP * if I_AM_MASTER_DSP is #defined or for the a SDSP if I_AM_SLAVE_DSP * is #defined. * * Damon Fasching, UW Madison fasching@wisconsin.cern.ch * * bugs/modifications: * - Fixed the verification of SSCRT bit in slave gcr. Was setting it * to 1 and checking for 0; should have been checking for 1. 4-11-01 dpf * - Um, got that backwards. Should set to 0 and check for 0. Almost out * of iterations...When in doubt read the manual..again. NOW it works 4-13-01 dpf * - Added NO_HOLD_SLAVE flag for configuring CE0 as SBSRAM. This is due * to missing pull-up (resistor) on the asynchronous ACK pin of slaves * 0, 1 and 2. The job for those slaves should be compiled with flag * -dBUGGY_SLAVE on the prototype ROD. The LEDs and HALT_OUTPUT can not * be set in this configuration! The ROD should have the pull-ups in * place and this flag can be removed. At that time, restore the #ifdef * '#ifdef TI_EVM' which is commented out below and comment out the * complicated #if which follows. 4-18-01 dpf * - Changed the EMIF Global Control Register (both master & slave) settings * from EMIF_GBLCTL_NOHOLD_1 to EMIF_GBLCTL_NOHOLD_0 since the production * rods do not need it set any more. 09.05.02 dpsf * - Changed the Master DSP's CE0 read & write strobe widths to 0x1f * so that they work correctly with the new controller VHDL. 11.11.02 dpsf * - Added function initSlvEmif, so that the master DSP can initialize the * slave's EMIF registers at power-up & reset (and thus the entire memories * of the SDSPs are available at all times). Note that only the external * SDRAM memory is enabled; the SDSP must still execute initEmif while * initializing to set up the global control register & CE0 space. 12.12.02 dpsf * - MDSP initialization now done early on in the boot.c routine, to allow * the auto_init routine to initialize any MDSP variable, whether or not * it is in IDRAM. The code here will serve as a reference. 22.12.04 dpsf ************************************************************************************/ #include #include #include #include "fxnProto.h" #include "utilities.h" #include "errorCodes.h" #include "comRegDfns.h" //dpsf needed for RR7 #pragma CODE_SECTION(initEmif, "icode"); #ifdef I_AM_MASTER_DSP #pragma CODE_SECTION(initSlvEmif, "xcode"); #endif /* set up memory type at each Chip Enable space */ /* SEE FUNCTION HEADER COMMENT DATED 4-18-01 dpf */ #if (defined(TI_EVM) || (defined(I_AM_SLAVE_DSP) && defined(NO_HOLD_SLAVE))) #define CE0_MTYPE EMIF_CECTL_MTYPE_SBSRAM32 #else #define CE0_MTYPE EMIF_CECTL_MTYPE_ASYNC32 /* master: RRIF; slaves: LEDs & haltOutput xxx */ #endif #ifndef TI_EVM #ifdef I_AM_MASTER_DSP #define CE1_MTYPE EMIF_CECTL_MTYPE_ASYNC8 /* boot ROM */ #elif I_AM_SLAVE_DSP #define CE1_MTYPE EMIF_CECTL_MTYPE_SBSRAM32 /* router FPGA */ #endif #endif #define CE2_MTYPE EMIF_CECTL_MTYPE_SDRAM32 /* 16 MByte SDRAM */ #define CE3_MTYPE EMIF_CECTL_MTYPE_SDRAM32 /* 16 MByte SDRAM on slaves */ #if (defined(TI_EVM)) #define CE0_RD_HLD 0x0 /* don't care for SBSRAM */ #define CE0_RD_SUP 0x0 /* don't care for SBSRAM */ #define CE0_RD_STR 0x0 /* don't care for SBSRAM */ #define CE0_WR_HLD 0x0 /* don't care for SBSRAM */ #define CE0_WR_SUP 0x0 /* don't care for SBSRAM */ #define CE0_WR_STR 0x0 /* don't care for SBSRAM */ #elif (defined(I_AM_MASTER_DSP)) #define CE0_RD_HLD 0x3 /* rrif read hold time in CLKOUT1 units (= CPU clk) */ #define CE0_RD_SUP 0xf /* rrif read setup time in CLKOUT1 units (= CPU clk) */ #define CE0_RD_STR 0x1f /* rrif read strobe time in CLKOUT1 units (= CPU clk) */ #define CE0_WR_HLD 0x3 /* rrif write hold time in CLKOUT1 units (= CPU clk) */ #define CE0_WR_SUP 0x1 /* rrif write setup time in CLKOUT1 units (= CPU clk) */ #define CE0_WR_STR 0x1f /* rrif write strobe time in CLKOUT1 units (= CPU clk) */ /* #define CE0_RD_STR 0xF * rrif read strobe time in CLKOUT1 units (= CPU clk) */ /* #define CE0_WR_STR 0x1e * rrif write strobe time in CLKOUT1 units (= CPU clk) */ #define CE1_RD_HLD 0x3 /* boot rom read hold time in CLKOUT1 units (= CPU clk) */ #define CE1_RD_SUP 0xf /* boot rom read setup time in CLKOUT1 units (= CPU clk) */ #define CE1_RD_STR 0x3f /* boot rom read strobe time in CLKOUT1 units (= CPU clk) */ #define CE1_WR_HLD 0x3 /* boot rom write hold time in CLKOUT1 units (= CPU clk) */ #define CE1_WR_SUP 0xf /* boot rom write setup time in CLKOUT1 units (= CPU clk) */ #define CE1_WR_STR 0x3f /* boot rom write strobe time in CLKOUT1 units (= CPU clk) */ #elif (defined(I_AM_SLAVE_DSP)) #ifdef COMMENTED #define CE0_RD_HLD 0x1 /* led read hold time in CLKOUT1 units (= CPU clk) */ #define CE0_RD_SUP 0x2 /* led read setup time in CLKOUT1 units (= CPU clk) */ #define CE0_RD_STR 0x4 /* led read strobe time in CLKOUT1 units (= CPU clk) */ #define CE0_WR_HLD 0x1 /* led write hold time in CLKOUT1 units (= CPU clk) */ #define CE0_WR_SUP 0x2 /* led write setup time in CLKOUT1 units (= CPU clk) */ #define CE0_WR_STR 0x4 /* led write strobe time in CLKOUT1 units (= CPU clk) */ #endif #define CE1_RD_HLD 0x0 /* don't care for SBSRAM */ #define CE1_RD_SUP 0x0 /* don't care for SBSRAM */ #define CE1_RD_STR 0x0 /* don't care for SBSRAM */ #define CE1_WR_HLD 0x0 /* don't care for SBSRAM */ #define CE1_WR_SUP 0x0 /* don't care for SBSRAM */ #define CE1_WR_STR 0x0 /* don't care for SBSRAM */ #endif /* SDRAM timing characteristics (only actually matter for asynchronous memory access, which is not the case here). */ #define SDRAM_RD_HLD 0x3 #define SDRAM_RD_SUP 0xf #define SDRAM_RD_STR 0x3f #define SDRAM_WR_HLD 0x3 #define SDRAM_WR_SUP 0xf #define SDRAM_WR_STR 0x3f #define SDRAM_REFRESH_PER 0x400 /* 1024 CLKOUT2 units (1/2 CPU clk). The maximum */ /* period for the micron part is 15.625 us = 0x4E2 */ #define SDRAM_TRC_PER (2*0x6) /* REFR cmnd to ACTV, MRS, or REFR cmnd in CLKOUT2 */ #define SDRAM_TRP_PER (2*0x2) /* DCAB cmnd to ACTV, MRS, or REFR cmnd in CLKOUT2 */ #define SDRAM_TRCD_PER (2*0x2) /* ACTV cmnd to READ or WRT cmnd in CLKOUT2 */ /************************************************************************************/ //dpsf: Done in boot.c now. #if 1 INT32 initEmif() {return SUCCESS; } #else INT32 initEmif() { INT32 returnCode = SUCCESS; UINT32 gblctl= 0x0, ce0ctl= 0x0, ce1ctl= 0x0, ce2ctl= 0x0, ce3ctl= 0x0; UINT32 sdctl= 0x0, sdtim= 0x0; #if ( (defined(I_AM_SLAVE_DSP))&&(defined(REV_E)) ) UINT32 sdext= 0x0; #endif /* set up the EMIF global control register */ #if defined(I_AM_MASTER_DSP) gblctl= EMIF_GBLCTL_RMK(EMIF_GBLCTL_NOHOLD_DISABLE, EMIF_GBLCTL_SDCEN_ENABLE, EMIF_GBLCTL_SSCEN_DISABLE, EMIF_GBLCTL_CLK1EN_DISABLE, EMIF_GBLCTL_CLK2EN_DISABLE, EMIF_GBLCTL_SSCRT_DEFAULT, EMIF_GBLCTL_RBTR8_HPRI); #elif (defined(I_AM_SLAVE_DSP)&&(defined(REV_B)||defined(REV_C))) gblctl= EMIF_GBLCTL_RMK(EMIF_GBLCTL_NOHOLD_DISABLE, EMIF_GBLCTL_SDCEN_ENABLE, EMIF_GBLCTL_SSCEN_ENABLE, EMIF_GBLCTL_CLK1EN_DISABLE, EMIF_GBLCTL_CLK2EN_DISABLE, EMIF_GBLCTL_SSCRT_CPUOVR2, EMIF_GBLCTL_RBTR8_HPRI); #elif (defined(I_AM_SLAVE_DSP)&&defined(REV_E)) //gblctl= EMIF_GBLCTL_RMK(EMIF_GBLCTL_NOHOLD_DISABLE,EMIF_GBLCTL_EKEN_ENABLE, // EMIF_GBLCTL_CLK1EN_DISABLE, // EMIF_GBLCTL_CLK2EN_ENABLE); gblctl= 0x3768; WRITE_REG(RESERVED_REG_7, gblctl+0x100000); #endif /* set up the EMIF ce0 space control register * master: RRIF * slaves: unused */ #ifndef I_AM_SLAVE_DSP ce0ctl= EMIF_CECTL_RMK(CE0_WR_SUP, CE0_WR_STR, CE0_WR_HLD, CE0_RD_SUP, CE0_RD_STR, CE0_MTYPE, CE0_RD_HLD); #endif /* set up the EMIF ce1 space control register * master: boot ROM * slaves: router */ #ifndef TI_EVM #if ( (defined(I_AM_MASTER_DSP))||((defined(REV_B))||(defined(REV_C))) ) ce1ctl= EMIF_CECTL_RMK(CE1_WR_SUP, CE1_WR_STR, CE1_WR_HLD, CE1_RD_SUP, CE1_RD_STR, CE1_MTYPE, CE1_RD_HLD); #elif (defined(REV_E)) //ce1ctl= EMIF_CECTL_RMK(CE1_WR_SUP, CE1_WR_STR, CE1_WR_HLD, // CE1_RD_SUP, EMIF_CECTL_TA_DEFAULT, // CE1_RD_STR, CE1_MTYPE, CE1_RD_HLD); ce1ctl= 0xffffff43; #endif #endif /* set up the EMIF ce2 and ce3 space control registers for 32 bit SDRAM * On the ROD, CE3 is not used; there are two SDRAM modules both at CE2. * On the EVM, there are SDRAMs at CE2 and CE3. */ #if ( (defined(I_AM_MASTER_DSP))||((defined(REV_B))||(defined(REV_C))) ) ce2ctl= EMIF_CECTL_RMK(SDRAM_WR_SUP, SDRAM_WR_STR, SDRAM_WR_HLD, SDRAM_RD_SUP, SDRAM_RD_STR, CE2_MTYPE, SDRAM_RD_HLD); ce3ctl= EMIF_CECTL_RMK(SDRAM_WR_SUP, SDRAM_WR_STR, SDRAM_WR_HLD, SDRAM_RD_SUP, SDRAM_RD_STR, CE3_MTYPE, SDRAM_RD_HLD); #elif (defined(REV_E)) ce2ctl= EMIF_CECTL_RMK(SDRAM_WR_SUP, SDRAM_WR_STR, SDRAM_WR_HLD, SDRAM_RD_SUP, EMIF_CECTL_TA_DEFAULT, SDRAM_RD_STR, CE2_MTYPE, SDRAM_RD_HLD); ce3ctl= EMIF_CECTL_RMK(SDRAM_WR_SUP, SDRAM_WR_STR, SDRAM_WR_HLD, SDRAM_RD_SUP, EMIF_CECTL_TA_DEFAULT, SDRAM_RD_STR, CE3_MTYPE, SDRAM_RD_HLD); #endif /* set up the EMIF SDRAM control register */ #if ( (defined(I_AM_MASTER_DSP))||((defined(REV_B))||(defined(REV_C))) ) sdctl= EMIF_SDCTL_RMK(EMIF_SDCTL_SDWID_2X16BIT, EMIF_SDCTL_RFEN_ENABLE, EMIF_SDCTL_INIT_YES, SDRAM_TRCD_PER, SDRAM_TRP_PER, SDRAM_TRC_PER); #elif (defined(REV_E)) sdctl= EMIF_SDCTL_RMK(EMIF_SDCTL_SDBSZ_4BANKS, EMIF_SDCTL_SDRSZ_13ROW, EMIF_SDCTL_SDCSZ_10COL, EMIF_SDCTL_RFEN_ENABLE, EMIF_SDCTL_INIT_YES, SDRAM_TRCD_PER, SDRAM_TRP_PER, SDRAM_TRC_PER); #endif /* assign the refresh period */ #if ( (defined(I_AM_MASTER_DSP))||((defined(REV_B))||(defined(REV_C))) ) sdtim= EMIF_SDTIM_RMK(SDRAM_REFRESH_PER); #elif (defined(REV_E)) sdtim= EMIF_SDTIM_RMK(EMIF_SDTIM_XRFR_DEFAULT, SDRAM_REFRESH_PER); #endif /* For Rev. E SDSPs, set the SDRAM Extension Register parameters: */ #if ( (defined(I_AM_SLAVE_DSP))&&(defined(REV_E)) ) sdext= EMIF_SDEXT_RMK(EMIF_SDEXT_WR2RD_DEFAULT,EMIF_SDEXT_WR2DEAC_DEFAULT, EMIF_SDEXT_WR2WR_DEFAULT,EMIF_SDEXT_R2WDQM_DEFAULT, EMIF_SDEXT_RD2WR_DEFAULT,EMIF_SDEXT_RD2DEAC_DEFAULT, EMIF_SDEXT_RD2RD_DEFAULT,EMIF_SDEXT_THZP_DEFAULT, EMIF_SDEXT_TWR_DEFAULT,EMIF_SDEXT_TRRD_DEFAULT, EMIF_SDEXT_TRAS_DEFAULT,EMIF_SDEXT_TCL_DEFAULT); #endif /* Finally load the registers here. */ #if ( (defined(I_AM_MASTER_DSP))||((defined(REV_B))||(defined(REV_C))) ) EMIF_configArgs(gblctl, ce0ctl, ce1ctl, ce2ctl, ce3ctl, sdctl, sdtim); #elif (defined(REV_E)) EMIF_configArgs(gblctl, ce0ctl, ce1ctl, ce2ctl, ce3ctl, sdctl, sdtim, sdext); #endif return returnCode; } #endif #ifdef I_AM_MASTER_DSP /************************************************************************************/ INT32 initSlvEmif(UINT8 sdsp) { INT32 returnCode = SUCCESS; UINT32 ceCtl[4]= {0x0, 0x0, 0x0, 0x0}; UINT32 sdCtl= 0x0, sdTim= 0x0, hpic= 0x0; UINT8 rodRev; /* The MDSP must set the SDSP EMIF CE Space Control and timing registers according to the ROD type (6701 for rev. B & C, 6713 for rev. E & F). The RMK macros will not work here (for 6713), so the register value is set up here with a constant. Note that the only fields that actually have any impact in the SDSP are the memory type and, for the 6713, turn-around time fields. A complete description of all the fields is given in the TMS320C6000 Peripherals Reference Guide. (Also see the constants at the top of this file). */ rodRev= getRodRev(); if ((rodRev == 0xe) || (rodRev == 0xf)) { ceCtl[1]= 0xffffff43; ceCtl[2]= ceCtl[3]= 0xffffff33; sdCtl= 0x6a226000; sdTim= 0x01000250; } else if ((rodRev == 0xb)||(rodRev == 0xc)) { ceCtl[1]= 0x40; ceCtl[2]= ceCtl[3]= 0xffff3f33; sdCtl= 0x0744c000; sdTim= SDRAM_REFRESH_PER; } else { newError(&returnCode, PARAM_ERROR, FATAL_ERR, "initSlvEmif", "Bad ROD revision number!\n", __FILE__, __LINE__); return returnCode; } #if ((!defined(SIM)) && (!defined(TI_EVM))) /* Now start the CPU by setting DSPINT bit of HPIC; DSPINT is autoreset. * Must keep HWOB bit set as well. */ hpic= (1 << _HPI_HPIC_HWOB_SHIFT); hpic|= (hpic <