/************************************************************************************ * accessRegister.c * * synopsis: Routines for reading and writing to the registers in the master DSPs * memory map. These registers are described by the rodRegister[] array of * ROD_REG structures. Each register in the memory map is described by an * element of the rodRegister array; the array is indexed by the register * IDs which are defined in registerIndices.h. The rodRegister structure * keeps the address of the register. * This file also includes the routine which initializes the rodRegister * array with the addresses of each register. * * in this file: struct ROD_REG rodRegister[], readRegister, writeRegister, * initRegisterArray * * related files: * registerIndices.h: Defines rodRegister[] array indices for registers in the * master DSP's memory map; these also serve as IDs in * the rwRegField primitve. * * Damon Fasching, UW Madison fasching@wisconsin.cern.ch * Douglas Ferguson, UW Madison (510) 486-5230 dpferguson@lbl.gov * * modifications/bugs * - updated the rodRegister array to reflect the new router & BOC * structures; placed rodRegister in SDRAM since it was getting too * big... 25.04.02 dpsf * - Changed the BOC status - serial number addresses to reflect the * latest BOC map. 25.03.03 PWP * - Added routine writeRegisterDirect, which does a faster direct write to * the RRIF register (not a read/modify/write), in new accessRegister.h * (the routine is inlined) 26.03.03 dpsf * - Updated the formatter registers here and in registerIndices.h to * match the new formatter VHDL code. 02.04.03 dpsf ************************************************************************************/ #include #include #include #include #include "resources.h" #include "comRegDfns.h" #include "registerIndices.h" #include "memoryPartitions.h" #include "accessRegister.h" #include "simulation.h" extern char genStr[]; #pragma CODE_SECTION(readRegister, "icode"); #pragma CODE_SECTION(writeRegister, "icode"); #pragma CODE_SECTION(initRegisterArray, "xcode"); /* using the DATA_SECTION pragma, the rodRegister array is only accessible to * the routines in this file (no problem, since they are the only ones supposed * to access it anyway). see the Optimizing C Compiler User's Guide, pg. 7-9. * The variable will be declared far (TI keyword), and then extern declarations * in other files seem not to find them correctly. bug? dpsf */ #pragma DATA_SECTION(rodRegister, "xpdata"); RodReg rodRegister[(LAST_ROD_REG)+1]; /************************************************************************************ * readRegister * * synopsis: Reads a register field. The value of the field from bit 'offset' to * bit ('offset' + 'width' - 1) of register 'id' is returned in the 'width' * least significant bits of the '*value' argument. The upper bits of * '*value' are set to 0. * * arguments: * IN: id = the index of the rodRegister[] element to read. * width = width of field to read. * offset = LSB of field being read. * *value = the value read from rodRegister['id'] * * modifications/bugs * - Added a confirmation message if a bit inside the diagnostic register * is set. 27.06.02 dpsf ************************************************************************************/ INT32 readRegister(UINT32 id, UINT32 width, UINT32 offset, UINT32 *value) { INT32 returnCode = SUCCESS; if (id > (LAST_ROD_REG)) { newError(&returnCode, ROD_REG_DNE, FATAL_ERR, "readRegister", "Register index out of range\n", __FILE__, __LINE__); return returnCode; } *value= (*rodRegister[id].address >> offset) & (N_BIT_MASK(width)); if (GET_RBIT(DIAGNOSTIC_REG, DR_DISP_ROD_REG_ID)) { sprintf(genStr,"%s0x%04x%s0x%08x%s%02d%s%02d%s0x%08x%s", "Reading from register ID ", id," (addr= ", (UINT32) rodRegister[id].address, "), with width and offset: ", width, ", ", offset,". The returned value is: ", *value,".\n"); newInformation(__FILE__, __LINE__, genStr); } simFpgaReadM(id, width, offset, *value); //Simulation: Check access return returnCode; } /************************************************************************************ * writeRegister * * synopsis: Function to write a register field. The 'width' least significant bits * of the 'value' argument will overwrite the field from bit 'offset' to * bit ('offset' + 'width' - 1) of register 'id'. The bits outside the * defined field are not affected. * * arguments: * IN: id = the index of the rodRegister[] element to write. * width = width of field to write. * offset = LSB of field being written. * value = the value to write to from rodRegister['id'] * * modifications/bugs * - Added a confirmation message if a bit inside the diagnostic register * is set. 27.06.02 dpsf ************************************************************************************/ INT32 writeRegister(UINT32 id, UINT32 width, UINT32 offset, UINT32 value) { INT32 returnCode = SUCCESS; UINT32 oldValue, newValue; if (id > (LAST_ROD_REG)) { newError(&returnCode, ROD_REG_DNE, FATAL_ERR, "writeRegister", "Register index %d out of range\n", __FILE__, __LINE__); return returnCode; } oldValue= *rodRegister[id].address; newValue= *rodRegister[id].address= (oldValue & (FIELD_OFF(offset,width))) |(FIELD_VAL(offset,width,value)); if (GET_RBIT(DIAGNOSTIC_REG, DR_DISP_ROD_REG_ID)) { sprintf(genStr,"%s0x%08x%s0x%04x%s0x%08x%s%02d%s%02d%s0x%08x, 0x%08x%s", "Writing ",value," to register ID ", id," (addr= ", (UINT32) rodRegister[id].address, "), with width and offset: ", width, ", ", offset,". The old & new values are: ", oldValue, newValue,".\n"); newInformation(__FILE__, __LINE__, genStr); } simFpgaWriteM(id, width, offset, value); //Simulation: Check access return returnCode; } /************************************************************************************ * GENERAL COMMENTS * * The macro ADDRESS(x) below allows accessing rod_bus registers from the host by * the name of the register rather than by its number or absolute address. The names * are defined in registerIndices.h, a file used in both the host and DSP builds * * For example, FORMAT_VRSN_LSB is defined as 0 in registerIndices.h. If the host * wants to write to it, the string FORMAT_VRSN_LSB is inserted into the parameter * list of the rwRegField primitive. This is passed along as a 0 in the parameter * list received by the master DSP. The initialization function below contains the * line * * rodRegister[FORMAT_VRSN_LSB].address = ADDRESS(FORMAT_VRSN_LSB); * * which with * * #define ADDRESS(x) ((UINT32 *)((REG_BASE) + ((A_##x)<<2))) * * and the definition of FORMAT_VRSN_LSB in registerIndices.h becomes * * rodRegister[0].address = ((UINT32 *)((REG_BASE) + ((A_FORMAT_VRSN_LSB)<<2))) * = ((UINT32 *)(0x400000 + 0x2220)) * * The FORMAT_VRSN_LSB parameter sent by the host function becomes the '0' used to * index the rodRegister array above, which is then passed to the readRegister or * writeRegister routines above. This method allows the host to write to any register * in the rod memory space by passing simple nmenonics, w/o being aware of the address * map. It is necessary to enforce the sequential method of defining the indicies in * registerInidicies.h. * * NOTE: The 2 bit shift is due to the fact that the 19 address pins on the EMIF of * the DSP are assigned to A21-A2 by the DSP while the RRIF decodes them internally * as A19-A0. The addresses below are in RRIF internal notation and should match the * addresses coded in the VHDL. The ADDRESS macro shifts them into DSP internal * notation for use within this program. * * SLAVE DSP HPI ADDRESS ENCODING * * For slave HPI access, the control leads are mapped to the EMIF address lines. * Most of them are fixed during the access and are therefore part of the address. * These are * HCNTL0 and HCNTL1 => bits 0|1 = 00 / 01 / 10 / 11 for HPIC / HPIA / HPID_I / HPID * HBE0_N and HBE1_N => bits 3|4 = 00 for both halfwords of a full word read on HPID; * = xx for HPID writes and HPIC and HPIA access * HAS_N => bit 6 = 1 (inactive) (don't think we need this) * HDS1_N and HDS2_N => bits 8|9 = 10 or 01, exactly 1 must be active during access * HHWIL, bit 2, is different for the first and second halfwords and therefore each * value of HHWIL is given a different address. * * INDEX CODES FOR REGISTER ARRAYS * * The addresses below are more complicated for registers which are indexed, i.e. * those which are part of an 'array' of registers. See for example the definitions * of ERROR_FLAGS(x,y) in registerIndices.h and of A_ERROR_FLAGS(f,fl) below, where * 'f' is the formatter number and 'fl' is link number within a formatter. * * In the following #define statements: * fmt = formatter FPGA number (0-7) * efb = efb engine number (0-1) * lnk = link (0-11 within fmt, 0-47 within efb, 0-95 in rrif) * bnk = event mem bank index * slv = slave DSP number * msk = FE link mask index; each mask is 32 bits so there are 3 masks for 96 links * clnk = control link number * sdlnk = 24 channels of strobe delay per BOC * dmLut = efb dynamic mask LUT number * hwrd = halfword for slave HPI access ************************************************************************************/ #define A_FMT_LINK_EN(fmt) (FMT_BASE +(fmt<<8) +0x0000) #define A_FMT_EXP_MODE_EN(fmt) (FMT_BASE +(fmt<<8) +0x0001) #define A_FMT_CONFIG_MODE_EN(fmt) (FMT_BASE +(fmt<<8) +0x0002) #define A_FMT_EDGE_MODE_EN(fmt) (FMT_BASE +(fmt<<8) +0x0003) #define A_FMT_READOUT_TIMEOUT(fmt) (FMT_BASE +(fmt<<8) +0x0004) #define A_FMT_DATA_OVERFLOW_LIMIT(fmt) (FMT_BASE +(fmt<<8) +0x0005) #define A_FMT_HEADER_TRAILER_LIMIT(fmt) (FMT_BASE +(fmt<<8) +0x0006) #define A_FMT_ROD_BUSY_LIMIT(fmt) (FMT_BASE +(fmt<<8) +0x0007) #define A_FMT_PXL_LINK_L1A_CNT(fmt) (FMT_BASE +(fmt<<8) +0x0008) #define A_FMT_PXL_BANDWIDTH(fmt) (FMT_BASE +(fmt<<8) +0x0009) /* +4*8 reserved addresses */ #define A_FMT_LINK_DATA_TEST_MUX(fmt) (FMT_BASE +(fmt<<8) +0x000e) #define A_FMT_MB_DIAG_REN(fmt) (FMT_BASE +(fmt<<8) +0x000f) #define A_FMT_LINK_OCC_CNT(fmt,lnk) (FMT_BASE +(fmt<<8) +0x0010 +lnk) #define A_FMT_TIMEOUT_ERR(fmt) (FMT_BASE +(fmt<<8) +0x001c) #define A_FMT_DATA_OVERFLOW_ERR(fmt) (FMT_BASE +(fmt<<8) +0x001d) #define A_FMT_HEADER_TRAILER_ERR(fmt) (FMT_BASE +(fmt<<8) +0x001e) #define A_FMT_ROD_BUSY_ERR(fmt) (FMT_BASE +(fmt<<8) +0x001f) #define A_FMT_DATA_FMT_STATUS(fmt) (FMT_BASE +(fmt<<8) +0x0020) #define A_FMT_STATUS(fmt) (FMT_BASE +(fmt<<8) +0x0021) #define A_FMT_VERSION(fmt) (FMT_BASE +(fmt<<8) +0x0022) #define A_FMT_MODEBIT_STAT_05(fmt) (FMT_BASE +(fmt<<8) +0x0023) #define A_FMT_MODEBIT_STAT_6B(fmt) (FMT_BASE +(fmt<<8) +0x0024) /* formatter FPGA registers */ #ifdef COMMENTED /* old formatters */ #define A_LNK_FMT_ERR_FLAGS(fmt, lnk) (FMT_BASE + (fmt << 8) + (lnk << 4) + 0x0000) #define A_LNK_FMT_CONFIG(fmt, lnk) (FMT_BASE + (fmt << 8) + (lnk << 4) + 0x0001) #define A_READOUT_TIMEOUT(fmt) (FMT_BASE + (fmt << 8) + 0x00f0) #define A_DATA_OVERFLOW_LIMIT(fmt) (FMT_BASE + (fmt << 8) + 0x00f1) #define A_HEADER_TRAILER_LIMIT(fmt) (FMT_BASE + (fmt << 8) + 0x00f2) #define A_ROD_BUSY_LIMIT(fmt) (FMT_BASE + (fmt << 8) + 0x00f3) #endif /* event fragment builder FPGA registers */ #define A_EFB_ERROR_MASK(efb, lnk) (EFB_BASE + (efb << 6) + ((lnk/12)<<4) +(lnk%12)) #define A_FORMAT_VRSN_LSB (EFB_BASE + 0x0080) #define A_FORMAT_VRSN_MSB (EFB_BASE + 0x0081) #define A_SOURCE_ID_LSB (EFB_BASE + 0x0082) #define A_SOURCE_ID_MSB (EFB_BASE + 0x0083) #define A_EFB_CMND_0 (EFB_BASE + 0x0084) #define A_EFB_FORMATTER_STAT (EFB_BASE + 0X0085) #define A_EFB_RUNTIME_STAT_REG (EFB_BASE + 0x0086) #define A_EVENT_HEADER_DATA (EFB_BASE + 0x0088) #define A_EV_FIFO_DATA1 (EFB_BASE + 0x0089) #define A_EV_FIFO_DATA2 (EFB_BASE + 0x008A) #define A_EFB_EVT_CNT (EFB_BASE + 0x008C) #define A_EFB_BANDWIDTH_CNT (EFB_BASE + 0x008D) #define A_EVT_MEM_MODE (EFB_BASE + 0x0090) #define A_EVT_MEM_CMND_STAT (EFB_BASE + 0x0091) #define A_EVT_MEM_RESET (EFB_BASE + 0x0092) #define A_EVT_MEM_FLAGS (EFB_BASE + 0x0093) #define A_EVT_MEM_A_WRD_CNT (EFB_BASE + 0x0098) #define A_EVT_MEM_B_WRD_CNT (EFB_BASE + 0x0099) #define A_EVT_MEM_PLAY_EVENT (EFB_BASE + 0x009A) #define A_EVT_MEM_STATUS (EFB_BASE + 0x009B) #define A_EFB_CODE_VERSION (EFB_BASE + 0x0087) /* router FPGA registers */ #define A_RTR_TRAP_CMND_0(slv) (RTR_BASE + (slv << 4) + 0x0000) #define A_RTR_TRAP_CMND_1(slv) (RTR_BASE + (slv << 4) + 0x0001) #define A_RTR_TRAP_RESET(slv) (RTR_BASE + (slv << 4) + 0x0002) #define A_RTR_TRAP_STATUS(slv) (RTR_BASE + (slv << 4) + 0x0003) #define A_RTR_TRAP_MATCH_0(slv) (RTR_BASE + (slv << 4) + 0x0004) #define A_RTR_TRAP_MOD_0(slv) (RTR_BASE + (slv << 4) + 0x0005) #define A_RTR_TRAP_MATCH_1(slv) (RTR_BASE + (slv << 4) + 0x0006) #define A_RTR_TRAP_MOD_1(slv) (RTR_BASE + (slv << 4) + 0x0007) #define A_RTR_TRAP_XFR_FRM_SIZE(slv) (RTR_BASE + (slv << 4) + 0x0008) #define A_RTR_TRAP_FIFO_WRD_CNT(slv) (RTR_BASE + (slv << 4) + 0x0009) #define A_RTR_TRAP_EVT_CNT(slv) (RTR_BASE + (slv << 4) + 0x000B) #define A_RTR_TRAP_INT_DELAY_CNT(slv) (RTR_BASE + (slv << 4) + 0x000C) #define A_RTR_CMND_STAT (RTR_BASE + 0x40 + 0x0) #define A_RTR_SLNK_ATLAS_DUMP_MATCH (RTR_BASE + 0x40 + 0x1) #define A_RTR_SLNK_ROD_DUMP_MATCH (RTR_BASE + 0x40 + 0x2) #define A_RTR_CODE_VERSION (RTR_BASE + 0x40 + 0x3) #define A_RTR_OUTPUT_SIGNAL_MUX (RTR_BASE + 0x40 + 0x4) /* ROD resources interface FPGA registers. */ #define A_RRIF_CODE_VERSION (RCF_BASE + 0x0103) #define A_RRIF_CMND_1 (RCF_BASE + 0x0104) /* MAIN CONTROL REG */ #define A_RRIF_CMND_0 (RCF_BASE + 0x0105) /* SPARE CONTROL REG */ #define A_ROD_MODE_REG (RCF_BASE + 0x0106) #define A_FE_MASK_LUT_SELECT (RCF_BASE + 0x0107) #define A_RRIF_STATUS_1 (RCF_BASE + 0x0108) /* MAIN STATUS REG */ #define A_RRIF_STATUS_0 (RCF_BASE + 0x0109) /* SPARE STATUS REG */ #define A_FE_CMND_MASK_0_LO (RCF_BASE + 0x010C) #define A_FE_CMND_MASK_0_HI (RCF_BASE + 0x010D) #define A_FE_CMND_MASK_1_LO (RCF_BASE + 0x010E) #define A_FE_CMND_MASK_1_HI (RCF_BASE + 0x010F) #define A_CALSTROBE_DELAY (RCF_BASE + 0x0110) #define A_CAL_CMND (RCF_BASE + 0x0111) #define A_FRMT_RMB_STATUS (RCF_BASE + 0x0114) #define A_EFB_DM_FIFO_FLAG_STA (RCF_BASE + 0x0116) #define A_EFB_DM_WC_STA_REG (RCF_BASE + 0x0117) /* ADDED MAP UPDATE*/ #define A_INP_MEM_CTRL (RCF_BASE + 0x0118) #define A_DBG_MEM_CTRL (RCF_BASE + 0x0119) #define A_CFG_READBACK_CNT (RCF_BASE + 0x011A) #define A_IDE_MEM_CTRL (RCF_BASE + 0x011C) #define A_IDE_MEM_STAT (RCF_BASE + 0x011D) #define A_INTRPT_TO_SLV (RCF_BASE + 0x0124) #define A_INTRPT_FROM_SLV (RCF_BASE + 0x0125) #define A_DFLT_ROD_EVT_TYPE (RCF_BASE + 0x01C0) #define A_CRTV_ROD_EVT_TYPE (RCF_BASE + 0x01D0) #define A_CAL_L1_TRIG_TYPE_0 (RCF_BASE + 0x0134) #define A_CAL_L1_TRIG_TYPE_1 (RCF_BASE + 0x0135) #define A_CAL_L1_ID_0 (RCF_BASE + 0x0138) #define A_CAL_L1_ID_1 (RCF_BASE + 0x0139) #define A_CAL_BCID (RCF_BASE + 0x013a) #define A_FE_OCC_CNTR_RESET(msk) (RCF_BASE + 0x0128 + (msk )) /* 1b/lnk;32b/reg*/ #define A_FE_OCC_CNTR_LOAD(msk) (RCF_BASE + 0x012C + (msk )) /* 1b/lnk;32b/reg*/ #define A_FE_OCC_LOAD_VALUE (RCF_BASE + 0x012F) #define A_DATA_LINK_MASK(msk) (RCF_BASE + 0x0130 + (msk )) /* 1b/lnk;32b/reg*/ #define A_FE_OCC_CNTR(occ) (RCF_BASE + 0x0140 + (occ)) #define A_DM_DFLT_LUT(mbLut) (RCF_BASE + 0x01C1 + mbLut) #define A_DM_CRTV_LUT(mbLut) (RCF_BASE + 0x01D1 + mbLut) #define A_CORRECTED_EVENTS_FIFO (RCF_BASE + 0x01E0) /**/ #define A_RMB_DFLT_LUT(lutset, fmt, mb) (RCF_BASE +0x0200 +(lutset<<5) +(fmt<<1) +mb) #define A_RMB_CRTV_LUT(lutset, fmt, mb) (RCF_BASE +0x0210 +(lutset<<5) +(fmt<<1) +mb) #define A_CMND_MASK_LUT(lutset, sp, lohi) (RCF_BASE +0x0180 +(lutset<<2) +(sp<<1) +lohi) /**/ /* old definitions #define A_RMB0_DFLT_LUT(fmt) (RCF_BASE + 0x0180 + (fmt << 1)) #define A_RMB1_DFLT_LUT(fmt) (RCF_BASE + 0x0181 + (fmt << 1)) #define A_RMB0_CRTV_LUT(fmt) (RCF_BASE + 0x0190 + (fmt << 1)) #define A_RMB1_CRTV_LUT(fmt) (RCF_BASE + 0x0191 + (fmt << 1)) */ /* BOC (optocard) registers */ #define A_STREAM_INHIBIT_MASK(clnk) (BOC_BASE + (clnk << 2) + 0x0) #define A_MARK_SPACE(clnk) (BOC_BASE + (clnk << 2) + 0x1) #define A_COARSE_DELAY(clnk) (BOC_BASE + (clnk << 2) + 0x2) #define A_FINE_DELAY(clnk) (BOC_BASE + (clnk << 2) + 0x3) #define A_LASER_CURR_DAC(clnk) (BOC_BASE + 0x180 + (clnk)) #define A_IN_LINK_DATA_DELAY(lnk) (BOC_BASE + 0x200 + (lnk)) #define A_BPM_CLOCK_PHASE (BOC_BASE + 0x260 + 0x0) #define A_BREG_CLOCK_PHASE (BOC_BASE + 0x260 + 0x3) #define A_VERNIER_CLOCK_STEP_PHASE0 (BOC_BASE + 0x260 + 0x4) #define A_VERNIER_CLOCK_STEP_PHASE1 (BOC_BASE + 0x260 + 0x5) #define A_STROBE_DELAY(sdlnk) (BOC_BASE + 0x280 + (sdlnk << 2)) #define A_IN_DATA_RX_THRESH_DAC(lnk) (BOC_BASE + 0x300 + (lnk)) #define A_BOC_RESET (BOC_BASE + 0x3C0 + 0x0) #define A_BPM_RESET (BOC_BASE + 0x3C0 + 0x1) #define A_TX_DAC_CLEAR (BOC_BASE + 0x3C0 + 0x2) #define A_RX_DAC_CLEAR (BOC_BASE + 0x3C0 + 0x3) #define A_BOC_STATUS (BOC_BASE + 0x3C0 + 0x4) #define A_RX_DATA_MODE (BOC_BASE + 0x3C0 + 0x5) /* + 2 reserved registers */ #define A_VERNIER_CLOCK_FINE_PHASE (BOC_BASE + 0x3C0 + 0x8) /* + 1 reserved register */ #define A_CLOCK_CONTROL_BITS (BOC_BASE + 0x3C0 + 0xA) #define A_BOC_FIRMWARE_VERSION (BOC_BASE + 0x3D0 + 0x0) #define A_BOC_HARDWARE_VERSION (BOC_BASE + 0x3D0 + 0x1) #define A_BOC_MODULE_TYPE (BOC_BASE + 0x3D0 + 0x2) #define A_BOC_MANUFACTURER (BOC_BASE + 0x3D0 + 0x3) #define A_BOC_SERIAL_NUMBER (BOC_BASE + 0x3D0 + 0x8) /* ADDRESS macro builds internal DSP addresses from above RRIF-centric addresses. * The 2 bit shift in the address definitions is because EMIF address bits (21:2) * map to rod_bus_adr(19:0). ## concatenates macros. */ #define ADDRESS(x) ((UINT32 *)(((A_##x)<<2) + (REG_BASE))) /************************************************************************************ * initRegisterArray * * synopsis: Initializes the rodRegister[] array of structures. ************************************************************************************/ INT32 initRegisterArray(void) { INT32 returnCode = SUCCESS; UINT32 x, y, z; for (x= 0; x < LAST_ROD_REG +1; ++x) rodRegister[x].address= 0; /* zero it */ /* formatter fpga registers */ for (x = 0; x < FORMATTERS_PER_ROD; ++x) { for (y = 0; y < LINKS_PER_FORMATTER; ++y) { rodRegister[FMT_LINK_OCC_CNT(x,y)].address= ADDRESS(FMT_LINK_OCC_CNT(x,y)); } rodRegister[FMT_LINK_EN(x)].address = ADDRESS(FMT_LINK_EN(x)); rodRegister[FMT_EXP_MODE_EN(x)].address = ADDRESS(FMT_EXP_MODE_EN(x)); rodRegister[FMT_CONFIG_MODE_EN(x)].address = ADDRESS(FMT_CONFIG_MODE_EN(x)); rodRegister[FMT_EDGE_MODE_EN(x)].address = ADDRESS(FMT_EDGE_MODE_EN(x)); rodRegister[FMT_READOUT_TIMEOUT(x)].address = ADDRESS(FMT_READOUT_TIMEOUT(x)); rodRegister[FMT_DATA_OVERFLOW_LIMIT(x)].address = ADDRESS(FMT_DATA_OVERFLOW_LIMIT(x)); rodRegister[FMT_HEADER_TRAILER_LIMIT(x)].address = ADDRESS(FMT_HEADER_TRAILER_LIMIT(x)); rodRegister[FMT_ROD_BUSY_LIMIT(x)].address = ADDRESS(FMT_ROD_BUSY_LIMIT(x)); rodRegister[FMT_PXL_LINK_L1A_CNT(x)].address = ADDRESS(FMT_PXL_LINK_L1A_CNT(x)); rodRegister[FMT_PXL_BANDWIDTH(x)].address = ADDRESS(FMT_PXL_BANDWIDTH(x)); rodRegister[FMT_LINK_DATA_TEST_MUX(x)].address = ADDRESS(FMT_LINK_DATA_TEST_MUX(x)); rodRegister[FMT_MB_DIAG_REN(x)].address = ADDRESS(FMT_MB_DIAG_REN(x)); rodRegister[FMT_TIMEOUT_ERR(x)].address = ADDRESS(FMT_TIMEOUT_ERR(x)); rodRegister[FMT_DATA_OVERFLOW_ERR(x)].address = ADDRESS(FMT_DATA_OVERFLOW_ERR(x)); rodRegister[FMT_HEADER_TRAILER_ERR(x)].address = ADDRESS(FMT_HEADER_TRAILER_ERR(x)); rodRegister[FMT_ROD_BUSY_ERR(x)].address = ADDRESS(FMT_ROD_BUSY_ERR(x)); rodRegister[FMT_DATA_FMT_STATUS(x)].address = ADDRESS(FMT_DATA_FMT_STATUS(x)); rodRegister[FMT_STATUS(x)].address = ADDRESS(FMT_STATUS(x)); rodRegister[FMT_VERSION(x)].address = ADDRESS(FMT_VERSION(x)); rodRegister[FMT_MODEBIT_STAT_05(x)].address = ADDRESS(FMT_MODEBIT_STAT_05(x)); rodRegister[FMT_MODEBIT_STAT_6B(x)].address = ADDRESS(FMT_MODEBIT_STAT_6B(x)); } #ifdef COMMENTED for (x = 0; x < FORMATTERS_PER_ROD; ++x) { for (y = 0; y < LINKS_PER_FORMATTER; ++y) { rodRegister[LNK_FMT_ERR_FLAGS(x,y)].address = ADDRESS(LNK_FMT_ERR_FLAGS(x,y)); rodRegister[LNK_FMT_CONFIG(x,y)].address = ADDRESS(LNK_FMT_CONFIG(x,y)); } rodRegister[READOUT_TIMEOUT(x)].address = ADDRESS(READOUT_TIMEOUT(x)); rodRegister[DATA_OVERFLOW_LIMIT(x)].address = ADDRESS(DATA_OVERFLOW_LIMIT(x)); rodRegister[HEADER_TRAILER_LIMIT(x)].address = ADDRESS(HEADER_TRAILER_LIMIT(x)); rodRegister[ROD_BUSY_LIMIT(x)].address = ADDRESS(ROD_BUSY_LIMIT(x)); } #endif /* EFB fpga registers */ for (x = 0; x < (EFBS_PER_ROD); ++x) { for (y = 0; y < (DATA_LINKS_PER_EFB); ++y) { rodRegister[EFB_ERROR_MASK(x,y)].address = ADDRESS(EFB_ERROR_MASK(x,y)); } } rodRegister[FORMAT_VRSN_LSB].address = ADDRESS(FORMAT_VRSN_LSB); rodRegister[FORMAT_VRSN_MSB].address = ADDRESS(FORMAT_VRSN_MSB); rodRegister[SOURCE_ID_LSB].address = ADDRESS(SOURCE_ID_LSB); rodRegister[SOURCE_ID_MSB].address = ADDRESS(SOURCE_ID_MSB); rodRegister[EFB_CMND_0].address = ADDRESS(EFB_CMND_0); rodRegister[EFB_FORMATTER_STAT].address = ADDRESS(EFB_FORMATTER_STAT); rodRegister[EFB_RUNTIME_STAT_REG].address = ADDRESS(EFB_RUNTIME_STAT_REG); rodRegister[EVENT_HEADER_DATA].address = ADDRESS(EVENT_HEADER_DATA); rodRegister[EV_FIFO_DATA1].address = ADDRESS(EV_FIFO_DATA1); rodRegister[EV_FIFO_DATA2].address = ADDRESS(EV_FIFO_DATA2); rodRegister[EFB_EVT_CNT].address = ADDRESS(EFB_EVT_CNT); rodRegister[EFB_BANDWIDTH_CNT].address = ADDRESS(EFB_BANDWIDTH_CNT); rodRegister[EVT_MEM_MODE].address = ADDRESS(EVT_MEM_MODE); rodRegister[EVT_MEM_CMND_STAT].address = ADDRESS(EVT_MEM_CMND_STAT); rodRegister[EVT_MEM_RESET].address = ADDRESS(EVT_MEM_RESET); rodRegister[EVT_MEM_FLAGS].address = ADDRESS(EVT_MEM_FLAGS); rodRegister[EVT_MEM_A_WRD_CNT].address = ADDRESS(EVT_MEM_A_WRD_CNT); rodRegister[EVT_MEM_B_WRD_CNT].address = ADDRESS(EVT_MEM_B_WRD_CNT); rodRegister[EVT_MEM_PLAY_EVENT].address = ADDRESS(EVT_MEM_PLAY_EVENT); rodRegister[EVT_MEM_STATUS].address = ADDRESS(EVT_MEM_STATUS); rodRegister[EFB_CODE_VERSION].address = ADDRESS(EFB_CODE_VERSION); /* router FPGA registers */ for (x = 0; x < N_SDSP; ++x) { rodRegister[RTR_TRAP_CMND_0(x)].address = ADDRESS(RTR_TRAP_CMND_0(x)); rodRegister[RTR_TRAP_CMND_1(x)].address = ADDRESS(RTR_TRAP_CMND_1(x)); rodRegister[RTR_TRAP_RESET(x)].address = ADDRESS(RTR_TRAP_RESET(x)); rodRegister[RTR_TRAP_STATUS(x)].address = ADDRESS(RTR_TRAP_STATUS(x)); rodRegister[RTR_TRAP_MATCH_0(x)].address = ADDRESS(RTR_TRAP_MATCH_0(x)); rodRegister[RTR_TRAP_MOD_0(x)].address = ADDRESS(RTR_TRAP_MOD_0(x)); rodRegister[RTR_TRAP_MATCH_1(x)].address = ADDRESS(RTR_TRAP_MATCH_1(x)); rodRegister[RTR_TRAP_MOD_1(x)].address = ADDRESS(RTR_TRAP_MOD_1(x)); rodRegister[RTR_TRAP_XFR_FRM_SIZE(x)].address = ADDRESS(RTR_TRAP_XFR_FRM_SIZE(x)); rodRegister[RTR_TRAP_FIFO_WRD_CNT(x)].address = ADDRESS(RTR_TRAP_FIFO_WRD_CNT(x)); rodRegister[RTR_TRAP_EVT_CNT(x)].address = ADDRESS(RTR_TRAP_EVT_CNT(x)); rodRegister[RTR_TRAP_INT_DELAY_CNT(x)].address = ADDRESS(RTR_TRAP_INT_DELAY_CNT(x)); } rodRegister[RTR_CMND_STAT].address = ADDRESS(RTR_CMND_STAT); rodRegister[RTR_SLNK_ATLAS_DUMP_MATCH].address = ADDRESS(RTR_SLNK_ATLAS_DUMP_MATCH); rodRegister[RTR_SLNK_ROD_DUMP_MATCH].address = ADDRESS(RTR_SLNK_ROD_DUMP_MATCH); rodRegister[RTR_CODE_VERSION].address = ADDRESS(RTR_CODE_VERSION); rodRegister[RTR_OUTPUT_SIGNAL_MUX].address = ADDRESS(RTR_OUTPUT_SIGNAL_MUX); /* ROD resources interface FPGA registers */ rodRegister[RRIF_CODE_VERSION].address = ADDRESS(RRIF_CODE_VERSION); rodRegister[RRIF_CMND_1].address = ADDRESS(RRIF_CMND_1); rodRegister[RRIF_CMND_0].address = ADDRESS(RRIF_CMND_0); rodRegister[ROD_MODE_REG].address = ADDRESS(ROD_MODE_REG); rodRegister[FE_MASK_LUT_SELECT].address = ADDRESS(FE_MASK_LUT_SELECT); rodRegister[RRIF_STATUS_1].address = ADDRESS(RRIF_STATUS_1); rodRegister[RRIF_STATUS_0].address = ADDRESS(RRIF_STATUS_0); rodRegister[FE_CMND_MASK_0_LO].address = ADDRESS(FE_CMND_MASK_0_LO); rodRegister[FE_CMND_MASK_0_HI].address = ADDRESS(FE_CMND_MASK_0_HI); rodRegister[FE_CMND_MASK_1_LO].address = ADDRESS(FE_CMND_MASK_1_LO); rodRegister[FE_CMND_MASK_1_HI].address = ADDRESS(FE_CMND_MASK_1_HI); rodRegister[CALSTROBE_DELAY].address = ADDRESS(CALSTROBE_DELAY); rodRegister[CAL_CMND].address = ADDRESS(CAL_CMND); rodRegister[FRMT_RMB_STATUS].address = ADDRESS(FRMT_RMB_STATUS); rodRegister[EFB_DM_FIFO_FLAG_STA].address = ADDRESS(EFB_DM_FIFO_FLAG_STA); rodRegister[EFB_DM_WC_STA_REG].address = ADDRESS(EFB_DM_WC_STA_REG); rodRegister[INP_MEM_CTRL].address = ADDRESS(INP_MEM_CTRL); rodRegister[DBG_MEM_CTRL].address = ADDRESS(DBG_MEM_CTRL); rodRegister[CFG_READBACK_CNT].address = ADDRESS(CFG_READBACK_CNT); rodRegister[IDE_MEM_CTRL].address = ADDRESS(IDE_MEM_CTRL); rodRegister[IDE_MEM_STAT].address = ADDRESS(IDE_MEM_STAT); rodRegister[INTRPT_TO_SLV].address = ADDRESS(INTRPT_TO_SLV); rodRegister[INTRPT_FROM_SLV].address = ADDRESS(INTRPT_FROM_SLV); rodRegister[DFLT_ROD_EVT_TYPE].address = ADDRESS(DFLT_ROD_EVT_TYPE); rodRegister[CRTV_ROD_EVT_TYPE].address = ADDRESS(CRTV_ROD_EVT_TYPE); rodRegister[CAL_L1_TRIG_TYPE_0].address = ADDRESS(CAL_L1_TRIG_TYPE_0); rodRegister[CAL_L1_TRIG_TYPE_1].address = ADDRESS(CAL_L1_TRIG_TYPE_1); rodRegister[CAL_L1_ID_0].address = ADDRESS(CAL_L1_ID_0); rodRegister[CAL_L1_ID_1].address = ADDRESS(CAL_L1_ID_1); rodRegister[CAL_BCID].address = ADDRESS(CAL_BCID); for (x = 0; x < NUM_FE_OCC_REGS; ++x) { rodRegister[FE_OCC_CNTR_RESET(x)].address = ADDRESS(FE_OCC_CNTR_RESET(x)); rodRegister[FE_OCC_CNTR_LOAD(x)].address = ADDRESS(FE_OCC_CNTR_LOAD(x)); } rodRegister[FE_OCC_LOAD_VALUE].address = ADDRESS(FE_OCC_LOAD_VALUE); for (x = 0; x < NUM_FE_OCC_REGS; ++x) { rodRegister[DATA_LINK_MASK(x)].address = ADDRESS(DATA_LINK_MASK(x)); } for (x = 0; x < NUM_FE_OCC_STAT_REGS; ++x) { rodRegister[FE_OCC_CNTR(x)].address = ADDRESS(FE_OCC_CNTR(x)); } for (x = 0; x < NUM_DM_LUTS; ++x) { rodRegister[DM_DFLT_LUT(x)].address = ADDRESS(DM_DFLT_LUT(x)); rodRegister[DM_CRTV_LUT(x)].address = ADDRESS(DM_CRTV_LUT(x)); } rodRegister[CORRECTED_EVENTS_FIFO].address = ADDRESS(CORRECTED_EVENTS_FIFO); /**/ for (x=0; x x; --y) { if (rodRegister[y].address == rodRegister[x].address) { if (rodRegister[x].address != 0) { newError(&returnCode, BAD_ADDRESS, FATAL_ERR, "initRegisterArray", "Register address already used.\n", __FILE__, __LINE__); } return returnCode; } }} #endif return returnCode; }