/* DSP Register Map Summary (1.1.x compatible):  (*) ==> see CommRegs structure below.
STATUS_REG_0       LIST_CNT_REG (*)   STATUS_REG_2       COMMAND_REG     
DIAGNOSTIC_REG     TRAPSTAT_REG_0     TRAPSTAT_REG_1     TRAPSTAT_REG_2  
HSTATUS_REG_0      HSTATUS_REG_1      HSSTAT_REG_0       HSSTAT_REG_1    
HSSTAT_REG_2       HSSTAT_REG_3       LIST_STATUS_REG    TRAP_REQ_REG    
                                                                         
TIME_REG           LOOP_REG           MEMORY_MAP_REG     TASK_STATE_REG  
HCMD_REG           TRAP_CMD_STAT      RESERVED_REG_0     RESERVED_REG_1  
RESERVED_REG_2     RESERVED_REG_3     RESERVED_REG_4     RESERVED_REG_5  
RESERVED_REG_6     RESERVED_REG_7 (*) INTR_DSP_HSHK      INTR_DSP_HSHK   
*/

/* CommRegs structure for compatibility between old (1.1.x) & new form of DSP code.
   Note that status[1] contains the list count; for code compatibility a (dummy)
   listCnt register is defined as well, which contains the same address as status[1]
   (& should be used in all code). Since this register nonetheless occupies space in
   the CommRegs structure (which might be obtained through a block read), a reserved
   register is removed from the structure to maintain the same structure size. The
   registers are positioned here so that the mapping is identical to the original for
   all registers of interest to the host.

   HCMD_STAT_REG_0/1 => HSTATUS_REG_0/1; HCMD is only command register.
*/

typedef struct {
	UINT32 status[2];
	#if defined(I_AM_HOST)
	 	UINT32 unused;
	#else
	 	UINT32 status2; /* SDSP communications status: private for MDSP */
	#endif
	UINT32 command;

	UINT32 diagnostic;
	UINT32 trapStat[3];

	UINT32 hStat[2];
	UINT32 hSdspStat[4];
	
	UINT32 listStatus;
	UINT32 trapReq;

	UINT32 time;
	UINT32 loop;
	UINT32 memoryMap;
	UINT32 taskState;
	
	UINT32 hCmd;
	UINT32 trapCmd;
	
	UINT32 reservedReg[7];  //(*): see above
	UINT32 listCnt;         //(*): see above

/* Inter-dsp communication registers: used for the handshake between master and
 * slave DSPs when one sends a list for the other to process.  These registers
 * reside in the IDRAM of each DSP.  The addresses are known to both the master
 * and the slaves.  Note that the write register for the slave is the read
 * register for the master and vice versa. */
	#if (defined(I_AM_HOST))
		UINT32 privateDsp[2];
	#elif (defined(I_AM_MASTER_DSP))
		UINT32 interDspHshkWr, interDspHshkRd;
	#elif (defined(I_AM_SLAVE_DSP))
		UINT32 interDspHshkRd, interDspHshkWr;
	#endif

} CommRegs;

/* communication register addresses: */
/* 0x00 */
#define STATUS_REG_0     (IDREGS_BASE)
#define STATUS_REG_1     ((STATUS_REG_0)    + 4)
#define STATUS_REG_2     ((STATUS_REG_1)    + 4)
#define COMMAND_REG_0    ((STATUS_REG_2)    + 4)

#define LIST_CNT_REG     (STATUS_REG_1)

/* 0x10 */
#define DIAGNOSTIC_REG   ((COMMAND_REG_0)   + 4)
#define TRAPSTAT_REG1_0   ((DIAGNOSTIC_REG)  + 4)
#define TRAPSTAT_REG1_1   ((TRAPSTAT_REG1_0)  + 4)
#define TRAPSTAT_REG1_2   ((TRAPSTAT_REG1_1)  + 4)

/* 0x20 */
#define HSTATUS_REG_0    ((TRAPSTAT_REG1_2)  + 4)
#define HSTATUS_REG_1    ((HSTATUS_REG_0)   + 4)
#define HSSTAT_REG_0     ((HSTATUS_REG_1)   + 4)
#define HSSTAT_REG_1     ((HSSTAT_REG_0)    + 4)

/* 0x30 */
#define HSSTAT_REG_2     ((HSSTAT_REG_1)    + 4)
#define HSSTAT_REG_3     ((HSSTAT_REG_2)    + 4)
#define LIST_STATUS_REG  ((HSSTAT_REG_3)    + 4)
#define TRAP_REQ_REG     ((LIST_STATUS_REG) + 4)

//The SDSPs use these registers as general status registers.
#if ((defined(I_AM_MASTER_DSP)) || (defined(I_AM_HOST)))
	#define SDSP_HSTATUS_REG_0   (HSSTAT_REG_0)
	#define SDSP_HSTATUS_REG_1   (HSSTAT_REG_1)
	#define SDSP_HSTATUS_REG_2   (HSSTAT_REG_2)
	#define SDSP_HSTATUS_REG_3   (HSSTAT_REG_3)
#endif

/* 0x40 */
#define TIME_REG         ((TRAP_REQ_REG)    + 4)
#define LOOP_REG         ((TIME_REG)        + 4)
#define MEMORY_MAP_REG   ((LOOP_REG)        + 4)
#define TASK_STATE_REG   ((MEMORY_MAP_REG)  + 4)

/* 0x50 */
#define HCMD_REG         ((TASK_STATE_REG)  + 4)
#define TRAP_CMD_REG1     ((HCMD_REG)        + 4)
#define RESERVED_REG_0   ((TRAP_CMD_REG1)    + 4)
#define RESERVED_REG_1   ((RESERVED_REG_0)  + 4)

//compatibility defs. dpsf:
#define TRAPSTAT_REG_0   TRAPSTAT_REG1_0
#define TRAPSTAT_REG_1   TRAPSTAT_REG1_1
#define TRAPSTAT_REG_2   TRAPSTAT_REG1_2

#define TRAP_CMD_STAT1    (TRAP_CMD_REG1)
#define TRAP_CMD_STAT    (TRAP_CMD_REG1)

#define HCMD_STAT_REG_0   (HSTATUS_REG_0)
#define HCMD_STAT_REG_1   (HSTATUS_REG_1)
#if (defined(I_AM_MASTER_DSP) || defined(I_AM_HOST))
#define HSTAT_REG_0			SDSP_HSTATUS_REG_0
#define HSTAT_REG_1			SDSP_HSTATUS_REG_1

#elif (defined(I_AM_SLAVE_DSP))
	#define HSTAT_REG_0       (HSSTAT_REG_0)
	#define HSTAT_REG_1       (HSSTAT_REG_1)
	#define HSTAT_REG_2       (HSSTAT_REG_2)
	#define HSTAT_REG_3       (HSSTAT_REG_3)
#endif

/* 0x60 */
#define RESERVED_REG_2   ((RESERVED_REG_1)  + 4)
#define RESERVED_REG_3   ((RESERVED_REG_2)  + 4)
#define RESERVED_REG_4   ((RESERVED_REG_3)  + 4)
#define RESERVED_REG_5   ((RESERVED_REG_4)  + 4)

/* 0x70 */
#define RESERVED_REG_6   ((RESERVED_REG_5)  + 4)
#define RESERVED_REG_7   ((RESERVED_REG_6)  + 4)

/* IDSP handshake registers: */
#if defined(I_AM_HOST)
	#define PRIVATE_DSP_0     ((RESERVED_REG_7)   + 4)
	#define PRIVATE_DSP_1     ((PRIVATE_DSP_0)    + 4)
#elif defined(I_AM_MASTER_DSP)
	#define INTR_DSP_HSHK_WR  ((RESERVED_REG_7)   + 4)
	#define INTR_DSP_HSHK_RD  ((INTR_DSP_HSHK_WR) + 4)
#elif defined(I_AM_SLAVE_DSP)
	#define INTR_DSP_HSHK_RD  ((RESERVED_REG_7)   + 4)
	#define INTR_DSP_HSHK_WR  ((INTR_DSP_HSHK_RD) + 4)
#endif