/* RRIF_CMND_1 */ -------------------------------------- FE_CMND_OUTPUT_ENABLE_O 0 FE_SP0_FR_DSP_TIM_O 1 FE_SP0_FR_DSP 1 FE_SP0_FR_TIM 0 NEW_MASK_READY_O 2 /* self clearing */ FE_OCC_CNTR_O 3 /* FE occupancy counter */ CMD_PULSE_CTR_RESET_O 4 CMD_PULSE_CTR_ENABLE_O 5 CMD_PULSE_CTR_LOAD_O 6 TRG_DECODER_RESET_O 7 TRG_DECODER_ENABLE_O 8 FORM_RMB_FLUSH_O 9 FORM_RMB_ENABLE_XFR_O 10 EFB_DYN_MSK_FLUSH_O 11 EFB_DYN_MSK_ENABLE_XFR_O 12 EFB_DYN_MSK_EVT_HDR_CNT_LD_O 13 EFB_DYN_MSK_EVT_MSK_CNT_LD_O 14 TEST_BENCH_RESET_O 15 TEST_BENCH_ENABLE_O 16 TEST_BENCH_RUN_O 17 SP_TRIGGER_SIGNAL_DECODER_EN_O 18 /* 0=> Off, 1=> Enabled */ CONFIGURATION_READBACK_O 19 /* 0=> Off, 1=> Enabled */ FE_MASK_LOAD_ENABLE_O 20 /* 0=> Off, 1=> Enabled */ STATIC_BCID_ENABLE_O 21 /* 0=> Off, 1=> Enabled */ STATIC_L1ID_ENABLE_O 22 /* 0=> Off, 1=> Enabled */ CMB_DYN_MASK_RDY_O 23 /* self clearing */ FIFO_CTRL_MUX_O 24 /* U FIFO (in, debug, event) MUX control */ FIFO_CTRL_MUX_W 2 /* U */ FIFO_TEST_MODE 0 /* control signals from test bench block */ FIFO_RESET 1 /* U FIFO rst:debug FIFO block control */ FIFO_ROD_BUS_MODE 2 /* U control signals come from ROD bus block*/ ROD_BUS_FIFO_ACCESS 0 /* U allows FIFO access over the ROD bus */ INPUT_FIFO_PLAY_INHIBIT_O 24 DEBUG_FIFO_ENABLE_O 25 DATA_PATH_SELECT_O 26 /* U data path mode selector */ DATA_PATH_SELECT_W 2 /* U */ TEST_BENCH_DATA_PATH 1 /* enable test bench data path */ STANDARD_DATA_PATH 2 /* enable run time data path */ ROD_TYPE_O 31 ROD_TYPE_SCT 0 ROD_TYPE_PIXEL 1