/* RRIF_CMND_1 */ -------------------------------------- FE_CMND_OUTPUT_ENABLE_O 0 FE_CMND_LNK_0_FR_DSP_TIM_O 1 FE_CMND_LNK_0_FR_DSP 1 FE_CMND_LNK_0_FR_TIM 0 NEW_MASK_READY_O 2 FE_OCC_CNTR_O 3 /* U FE occupancy counter */ TRG_ACCUM_CTRL_O 4 /* U FE command pulse accumulator control */ TRG_ACCUM_CTRL_W 3 /* U */ TRG_ACCUM_FLUSH 1 /* U */ TRG_ACCUM_ENABLE 2 TRG_ACCUM_LOAD 4 TRG_DECODER_O 7 /* U trigger signal decoder access control */ TRG_DECODER_W 2 /* U */ TRG_DECODER_RESET 1 /* U */ TRG_DECODER_ENABLE 2 FORM_RMB_FLUSH_O 9 FORM_RMB_ENABLE_XFR_O 10 EFB_DYN_MSK_FLUSH_O 11 EFB_DYN_MSK_ENABLE_XFR_O 12 EFB_DYN_MSK_EVT_HDR_CNT_LD_O 13 EFB_DYN_MSK_EVT_MSK_CNT_LD_O 14 TEST_BENCH_CLEAR_O 15 TEST_BENCH_ENABLE_O 16 TEST_BENCH_RUN_O 17 MODULE_CALIBRATION_O 18 /* 0=> Off, 1=> Enabled */ CONFIGURATION_READBACK_O 19 /* 0=> Off, 1=> Enabled */ FIFO_CTRL_MUX_O 24 /* U FIFO (in, debug, event) MUX control */ FIFO_CTRL_MUX_W 2 /* U */ FIFO_TEST_MODE 0 /* control signals from test bench block */ FIFO_RESET 1 /* U FIFO rst:debug FIFO block control */ FIFO_ROD_BUS_MODE 2 /* U control signals come from ROD bus block*/ DATA_PATH_SELECT_O 26 /* U data path mode selector */ DATA_PATH_SELECT_W 2 /* U */ ROD_BUS_FIFO_ACCESS 0 /* U allows FIFO access over the ROD bus */ STANDARD_DATA_PATH 2 /* enable run time data path */ TEST_MODE_DATA_PATH 1 /* enable test bench data path */ ROD_MODE_O 28 /* MODES Tbd */ ROD_MODE_W 3 ROD_TYPE_O 31 ROD_TYPE_SCT 0 ROD_TYPE_PIXEL 1