-- XLXL}"##&* <% VXL d n x             4 5 6 7 8 9 : ; < = > ? @ A B }C yD uE qF mG iH eI aJ ]K YL UM QN MO IP EQ AR =S 9T 5U 1V -W )X %Y !Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~     } y u q m i e a ] Y U Q M I E A = 9 5 1 -e )o % !                                         } y u q m i e a ] Y U Q M I E A = 9 5 1 - ) % !         !"#$%&'()*+,-./XLxXLXL@XLXLXLlXLXL4XLXLXL`XLXL(XLXLXLTXLXLXLXLXLHXLXLXLtXLXL<XLXLXLhXLXL0XLXLXL\XLXL$XLXLXLPXLXLXL|XLXLDXLXL XLpXLXL8XLXLXLdXL XL ,XL XL XL XXL XL  XL XL XL LXL XL XL { XL XL EXL XL XL tXL XL > XL RXL fXL XL 7XL XL d; XL XL  XL XL@XLwXLXL$XLf$XLC#XLwXL/.h/.1@//HCO1 ?-`.l3S3QdHID1 E;=Ltrigger times r.N-.h1@.N.MHCO1H ?-`-3S/nHID1p>Bv?number of min bias pileup evts -)-1@--HCO1 ?-`)3S.NxHID1Dy?Number of 32 bit words in event fragment)%)1@))HCO1 -`%3S-HID1Dy?Latency: triggered BCO to MCC output in us %!%1@%%HCO1 ?-`!3S)HID1Dy?Latency: triggered BCO to ROD output in us !!1@!!HCO1 `BD@@@@@@@@??@???@??-`3S%HID1C?pileup hits per link per event 1@HCO1 -`3S!HID1C?b jets hits per link per event N1@HCO1 A-`R3SHID1C?hits/link/event, SCT barrel 1 4N1@43HCO1 A-`3SHID1C?hits/link/event, SCT barrel 2 p1@poHCO1 A-`3S4HID1C?hits/link/event, SCT barrel 3 1@HCO1 A-`3SpHID1C?hits/link/event, SCT barrel 4 61@HCO1 .EE6DuCBBd-`3SHID1 4?@?cluster width 91@HCO1j t@AA@@A@@@@@@@A@@@@@@@AA`AA@@A0@@@@AA A@@@@A@AP@@@@A@AA@AB@A@A-`=3SHID1`B?total pileup hits by link !91@! HCO1j `-`3SHID1`B?total b jet hits by link1@HCO1j HC@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@C@-`3S!HID1`B?total hits by link, unscaled-1@HCO1 ?-`13SHID1F<output memory 0 occupancy F-1@HCO1 ?-`J3SHID1F<output memory 1 occupancy .F1@.-HCO1n ?-`3S4HID1dC>input buffer 0 occupancy1@HCO1n ?-`3S.5HID1dC>input buffer 1 occupancy1@HCO1n ?-`3S6HID1dC>input buffer 2 occupancyl1@lkHCO1n ?-`3S7HID1dC>input buffer 3 occupancyX1@HCO1n ?-`\3Sl8HID1dC>input buffer 4 occupancy@X1@@?HCO1n ?-`3S9HID1dC>input buffer 5 occupancy,1@HCO1n ?-`03S@:HID1dC>input buffer 6 occupancy,1@HCO1n ?-`3S;HID1dC>input buffer 7 occupancy~1@~}HCO1n ?-`3Sinput buffer 8 occupancy  j1@  HCO1n ?-` n3S~=HID1dC>input buffer 9 occupancy Q  j1@ Q PHCO1n ?-` 3S >HID1dC>input buffer 10 occupancy   < 1@  HCO1n ?-` @3S Q?HID1dC>input buffer 11 occupancy  #  <1@ # "HCO1n ?-` 3S @HID1dC>input buffer 12 occupancy    1@  HCO1n ?-` 3S #AHID1dC>input buffer 13 occupancy   w 1@  HCO1n ?-` {3S BHID1dC>input buffer 14 occupancy  ^  w1@ ^ ]HCO1n ?-` 3S CHID1dC>input buffer 15 occupancy   I 1@  HCO1n ?-` M3S ^DHID1dC>input buffer 16 occupancy  0 I1@ 0 /HCO1n ?-`3S EHID1dC>input buffer 17 occupancy 1@HCO1n ?-`3S 0FHID1dC>input buffer 18 occupancy 1@HCO1n ?-`3SGHID1dC>input buffer 19 occupancy k1@kjHCO1n ?-`3SHHID1dC>input buffer 20 occupancy V1@HCO1n ?-`Z3SkIHID1dC>input buffer 21 occupancy =V1@=<HCO1n ?-`3SJHID1dC>input buffer 22 occupancy (1@HCO1n ?-`,3S=KHID1dC>input buffer 23 occupancy (1@HCO1n ?-`3SLHID1dC>input buffer 24 occupancy x1@xwHCO1n ?-`3SMHID1dC>input buffer 25 occupancy c1@HCO1n ?-`g3SxNHID1dC>input buffer 26 occupancy Jc1@JIHCO1n ?-`3SOHID1dC>input buffer 27 occupancy 51@HCO1n ?-`93SJPHID1dC>input buffer 28 occupancy 51@HCO1n ?-`3SQHID1dC>input buffer 29 occupancy 1@HCO1n ?-` 3SRHID1dC>input buffer 30 occupancy p1@HCO1n ?-`t3SSHID1dC>input buffer 31 occupancy Wp1@WVHCO1n ?-`3STHID1dC>input buffer 32 occupancy B1@HCO1n ?-`F3SWUHID1dC>input buffer 33 occupancy )B1@)(HCO1n ?-`3SVHID1dC>input buffer 34 occupancy 1@HCO1n ?-`3S)WHID1dC>input buffer 35 occupancy }1@HCO1n ?-`3SXHID1dC>input buffer 36 occupancy d}1@dcHCO1n ?-`3SYHID1dC>input buffer 37 occupancy O1@HCO1n ?-`S3SdZHID1dC>input buffer 38 occupancy 6O1@65HCO1n ?-`3S[HID1dC>input buffer 39 occupancy !1@HCO1n ?-`%3S6\HID1dC>input buffer 40 occupancy !1@HCO1n ?-`3S]HID1dC>input buffer 41 occupancy q1@qpHCO1n ?-`3S^HID1dC>input buffer 42 occupancy \1@HCO1n ?-``3Sq_HID1dC>input buffer 43 occupancy C\1@CBHCO1n ?-`3S`HID1dC>input buffer 44 occupancy .1@HCO1n ?-`23SCaHID1dC>input buffer 45 occupancy .1@HCO1n ?-`3SbHID1dC>input buffer 46 occupancy ~1@~}HCO1n ?-`3ScHID1dC>input buffer 47 occupancy i1@HCO1n ?-`m3S~dHID1dC>input buffer 48 occupancy Pi1@POHCO1n ?-`3SeHID1dC>input buffer 49 occupancy ;1@HCO1n ?-`?3SPfHID1dC>input buffer 50 occupancy ";1@"!HCO1n ?-`3SgHID1dC>input buffer 51 occupancy  1@HCO1n ?-`3S"hHID1dC>input buffer 52 occupancy v 1@HCO1n ?-`z3SiHID1dC>input buffer 53 occupancy ]v1@]\HCO1n ?-`3SjHID1dC>input buffer 54 occupancy H1@HCO1n ?-`L3S]kHID1dC>input buffer 55 occupancy /H1@/.HCO1n ?-`3SlHID1dC>input buffer 56 occupancy 1@HCO1n ?-`3S/mHID1dC>input buffer 57 occupancy 1@HCO1n ?-`3SnHID1dC>input buffer 58 occupancy j1@jiHCO1n ?-`3SoHID1dC>input buffer 59 occupancy U1@HCO1n ?-`Y3SjpHID1dC>input buffer 60 occupancy <U1@<;HCO1n ?-`3SqHID1dC>input buffer 61 occupancy '1@HCO1n ?-`+3S<rHID1dC>input buffer 62 occupancy '1@ HCO1n ?-`3SsHID1dC>input buffer 63 occupancy w1@wvHCO1n ?-`3StHID1dC>input buffer 64 occupancy b1@HCO1n ?-`f3SwuHID1dC>input buffer 65 occupancy Ib1@IHHCO1n ?-`3SvHID1dC>input buffer 66 occupancy 41@HCO1n ?-`83SIwHID1dC>input buffer 67 occupancy 41@HCO1n ?-`3SxHID1dC>input buffer 68 occupancy 1@HCO1n ?-` 3SyHID1dC>input buffer 69 occupancy o1@HCO1n ?-`s3SzHID1dC>input buffer 70 occupancy Vo1@VUHCO1n ?-`3S{HID1dC>input buffer 71 occupancy A1@HCO1n ?-`E3SV|HID1dC>input buffer 72 occupancy (A1@('HCO1n ?-`3S}HID1dC>input buffer 73 occupancy 1@HCO1n ?-`3S(~HID1dC>input buffer 74 occupancy |1@HCO1n ?-`3SHID1dC>input buffer 75 occupancy c|1@cbHCO1n ?-`3SHID1dC>input buffer 76 occupancy N1@HCO1n ?-`R3ScHID1dC>input buffer 77 occupancy 5N1@54HCO1n ?-`3SHID1dC>input buffer 78 occupancy  1@HCO1n ?-`$3S5HID1dC>input buffer 79 occupancy  1@HCO1n ?-`3SHID1dC>input buffer 80 occupancy p1@poHCO1n ?-`3SHID1dC>input buffer 81 occupancy [1@HCO1n ?-`_3SpHID1dC>input buffer 82 occupancy B[1@BAHCO1n ?-`3SHID1dC>input buffer 83 occupancy -1@HCO1n ?-`13SBHID1dC>input buffer 84 occupancy -1@HCO1n ?-`3SHID1dC>input buffer 85 occupancy }1@}|HCO1n ?-`3SHID1dC>input buffer 86 occupancy h1@HCO1n ?-`l3S}HID1dC>input buffer 87 occupancy Oh1@ONHCO1n ?-`3SHID1dC>input buffer 88 occupancy ޸:1@޸޷HCO1n ?-`>3SOHID1dC>input buffer 89 occupancy !ݣ:1@! HCO1n ?-`ݧ3S޸HID1dC>input buffer 90 occupancy ݊ ݣ1@݊݉HCO1n ?-`3S!HID1dC>input buffer 91 occupancy u 1@HCO1n ?-`y3S݊HID1dC>input buffer 92 occupancy \u1@\[HCO1n ?-`3SHID1dC>input buffer 93 occupancy G1@HCO1n ?-`K3S\HID1dC>input buffer 94 occupancy .ڰG1@.-HCO1n ?-`ڴ3SHID1dC>input buffer 95 occupancy ڕڰ1@ڕڔHCO1j 1?BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB?BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB-`3S.HID1`B?peak input buffer occupancy by link ن1@HCO1j `-`ي3SڕHID1`B?events in header-only mode by link kن1@kjHCO1j `-`3SHID1`B?mean input buffer occupancy by link lׅ [YHAUT1@׆HCO1n d-`[3SkeHID1dtriggers per 40000 clock cycles vs time 9gLׅ1@gfHCO1  A-`P3SoHID17??min bias pileup events every 40000 clock cycles K0L1@0/HCO1 8ES`ES`ES`ES`ES`ES`ES`ES`ES`ES`ES`ES`ES`ES`ES`ES`ES`ES`ES`ES`-`3SgHID1IA?output memory 0 each 40000 clock cycles Kֶ1@HCO1  ETETETETETETETETETETETETETETETETETETETET-`ֺ3S0HID1IA?output memory 1 each 40000 clock cycles M֘iֶ1@֘֗HCO1 ????????????????????-`m3SHID1KA?input buffer 0 occupancy each 40000 clock cyclesMKi1@KJHCO1 xBBBBBBBBBBBBBBBBBBBB-` 3S֘HID1KA?input buffer 1 occupancy each 40000 clock cyclesM1@HCO1 BBBBBBBBBBBBBBBBBBBB-`3SKHID1KA?input buffer 2 occupancy each 40000 clock cyclesMձՂ1@ձհHCO1 xBBBBBBBBBBBBBBBBBBBB-`Ն3SHID1KA?input buffer 3 occupancy each 40000 clock cyclesMd5Ղ1@dcHCO1 BBBBBBBBBBBBBBBBBBBB-`93SձHID1KA?input buffer 4 occupancy each 40000 clock cyclesM51@HCO1 BBBBBBBBBBBBBBBBBBBB-`3SdHID1KA?input buffer 5 occupancy each 40000 clock cyclesMԛ1@HCO1 BBBBBBBBBBBBBBBBBBBB-`ԟ3SHID1KA?input buffer 6 occupancy each 40000 clock cyclesM}Nԛ1@}|HCO1 dBBBBBBBBBBBBBBBBBBBB-`R3SHID1KA?input buffer 7 occupancy each 40000 clock cyclesM0N1@0/HCO1 BBBBBBBBBBBBBBBBBBBB-`3S}HID1KA?input buffer 8 occupancy each 40000 clock cyclesMӴ1@HCO1 BBBBBBBBBBBBBBBBBBBB-`Ӹ3S0HID1KA?input buffer 9 occupancy each 40000 clock cyclesNӕfӴ1@ӕӔHCO1 xBBBBBBBBBBBBBBBBBBBB-`j3SHID1LA?input buffer 10 occupancy each 40000 clock cycles NGf1@GFHCO1 BBBBBBBBBBBBBBBBBBBB-`3SӕHID1LA?input buffer 11 occupancy each 40000 clock cycles N1@HCO1 dBBBBBBBBBBBBBBBBBBBB-`3SGHID1LA?input buffer 12 occupancy each 40000 clock cycles Nҫ|1@ҫҪHCO1 BBBBBBBBBBBBBBBBBBBB-`Ҁ3SHID1LA?input buffer 13 occupancy each 40000 clock cycles N].|1@]\HCO1 BBBBBBBBBBBBBBBBBBBB-`23SҫHID1LA?input buffer 14 occupancy each 40000 clock cycles N.1@HCO1 xBBBBBBBBBBBBBBBBBBBB-`3S]HID1LA?input buffer 15 occupancy each 40000 clock cycles Nђ1@HCO1 PBBBBBBBBBBBBBBBBBBBB-`і3SHID1LA?input buffer 16 occupancy each 40000 clock cycles NsDђ1@srHCO1 BBBBBBBBBBBBBBBBBBBB-`H3SHID1LA?input buffer 17 occupancy each 40000 clock cycles N%D1@%$HCO1 BBBBBBBBBBBBBBBBBBBB-`3SsHID1LA?input buffer 18 occupancy each 40000 clock cycles NШ1@HCO1 BBBBBBBBBBBBBBBBBBBB-`Ь3S%HID1LA?input buffer 19 occupancy each 40000 clock cycles NЉZШ1@ЉЈHCO1 BBBBBBBBBBBBBBBBBBBB-`^3SHID1LA?input buffer 20 occupancy each 40000 clock cycles Næw1@æåHCO1 BBBBBBBBBBBBBBBBBBBB-`{&HID1LA?input buffer 21 occupancy each 40000 clock cycles NX)w1@XWHCO1 BBBBBBBBBBBBBBBBBBBB-`-&æHID1LA?input buffer 22 occupancy each 40000 clock cycles N )1@  HCO1 xBBBBBBBBBBBBBBBBBBBB-`&XHID1LA?input buffer 23 occupancy each 40000 clock cycles N¼1@¼»HCO1 BBBBBBBBBBBBBBBBBBBB-`‘& HID1LA?input buffer 24 occupancy each 40000 clock cycles Nn?1@nmHCO1 BBBBBBBBBBBBBBBBBBBB-`C&¼HID1LA?input buffer 25 occupancy each 40000 clock cycles N ?1@ HCO1 BBBBBBBBBBBBBBBBBBBB-`&nHID1LA?input buffer 26 occupancy each 40000 clock cycles N1@HCO1 BBBBBBBBBBBBBBBBBBBB-`& HID1LA?input buffer 27 occupancy each 40000 clock cycles NU1@HCO1 PBBBBBBBBBBXL#SXL#ASXL#SXL#SXL#HS#XL"SXL"SXL"OSXL"SXL"SXL"VSXL"SXL"SXL"]SXL" SXL"SXL"dSXL"S"XL!SXL!kSXL!SXL!SXL!rSXL!SXL!SXL!ySXL!&SXL!SXL!SXL!-S!XL SXL SXL 4SXL SXL SXL ;SXL SXL SXL BSXL SXL SXL IS XLSXLSXLPSXLSXLSXLWSXLSXLSXL^SXL SXLSXLeSXLSXLSXLlSXLSXLSXLsSXL SXLSXLzSXL'SXLSXLSXL.SXLSXLSXL5SXLSXLSXL<SXLSXLSXLCSXLSXLSXLJSXLSXLSXLQSXLSXLSXLXSXLSXLRXLaRXLRXLRXLkRXLRXLRXLuRXL#RXLRXLPXL1PXL>XLqXLXLNXLXLXL|XLXLDXLXL XLpXLXL8XLXLXLdXLXL,XLXLXLXXLXL XLXLXLLXLXLXLxXLXL@XLXLXLlXLXL4XLXLXL`XLXL(XLXLXLTXLXLXLXLXLHXLXLXLtXLXL<XLXLXLhXLXL0XLXLXL\XLXL$XLXLXLPXLXLXL|XLXLDXLXL XLpXLXL8XLXLXLdXL XL ,XL XL XL XXL XL  XL XL XL LXL XL XL { XL XL EXL XL XL tXL XL > XL RXL fXL XL 7XL XL d; XL XL  XL XL@XLwXLXL$XLf$XLC#XLwXLBBBBBBBBBB-`Y&HID1LA?input buffer 28 occupancy each 40000 clock cycles N6U1@65HCO1 <BBBBBBBBBBBBBBBBBBBB-` &HID1LA?input buffer 29 occupancy each 40000 clock cycles N1@HCO1 BBBBBBBBBBBBBBBBBBBB-`&6HID1LA?input buffer 30 occupancy each 40000 clock cycles Nk1@HCO1 BBBBBBBBBBBBBBBBBBBB-`o&HID1LA?input buffer 31 occupancy each 40000 clock cycles NLk1@LKHCO1 BBBBBBBBBBBBBBBBBBBB-`!&HID1LA?input buffer 32 occupancy each 40000 clock cycles N1@HCO1 PBBBBBBBBBBBBBBBBBBBB-`&LHID1LA?input buffer 33 occupancy each 40000 clock cycles N1@HCO1 BBBBBBBBBBBBBBBBBBBB-`&HID1LA?input buffer 34 occupancy each 40000 clock cycles Nb31@baHCO1 BBBBBBBBBBBBBBBBBBBB-`7&HID1LA?input buffer 35 occupancy each 40000 clock cycles N31@HCO1 xBBBBBBBBBBBBBBBBBBBB-`&bHID1LA?input buffer 36 occupancy each 40000 clock cycles N1@HCO1 xBBBBBBBBBBBBBBBBBBBB-`&HID1LA?input buffer 37 occupancy each 40000 clock cycles NxI1@xwHCO1 BBBBBBBBBBBBBBBBBBBB-`M&HID1LA?input buffer 38 occupancy each 40000 clock cycles N*I1@*)HCO1 dBBBBBBBBBBBBBBBBBBBB-`&xHID1LA?input buffer 39 occupancy each 40000 clock cycles N1@HCO1 BBBBBBBBBBBBBBBBBBBB-`&*HID1LA?input buffer 40 occupancy each 40000 clock cycles N_1@HCO1 BBBBBBBBBBBBBBBBBBBB-`c&HID1LA?input buffer 41 occupancy each 40000 clock cycles N@_1@@?HCO1 BBBBBBBBBBBBBBBBBBBB-`&HID1LA?input buffer 42 occupancy each 40000 clock cycles N1@HCO1 xBBBBBBBBBBBBBBBBBBBB-`&@HID1LA?input buffer 43 occupancy each 40000 clock cycles Nu1@HCO1 BBBBBBBBBBBBBBBBBBBB-`y&HID1LA?input buffer 44 occupancy each 40000 clock cycles NV'u1@VUHCO1 BBBBBBBBBBBBBBBBBBBB-`+&HID1LA?input buffer 45 occupancy each 40000 clock cycles N'1@HCO1 xBBBBBBBBBBBBBBBBBBBB-`&VHID1LA?input buffer 46 occupancy each 40000 clock cycles N1@HCO1 xBBBBBBBBBBBBBBBBBBBB-`&HID1LA?input buffer 47 occupancy each 40000 clock cycles Nl=1@lkHCO1 ????????????????????-`A&HID1LA?input buffer 48 occupancy each 40000 clock cycles N=1@HCO1 (BBBBBBBBBBBBBBBBBBBB-`&lHID1LA?input buffer 49 occupancy each 40000 clock cycles N1@HCO1 BBBBBBBBBBBBBBBBBBBB-`&HID1LA?input buffer 50 occupancy each 40000 clock cycles NS1@HCO1 PBBBBBBBBBBBBBBBBBBBB-`W&HID1LA?input buffer 51 occupancy each 40000 clock cycles N4S1@43HCO1 BBBBBBBBBBBBBBBBBBBB-` &HID1LA?input buffer 52 occupancy each 40000 clock cycles N1@HCO1 BBBBBBBBBBBBBBBBBBBB-`&4HID1LA?input buffer 53 occupancy each 40000 clock cycles Ni1@HCO1 BBBBBBBBBBBBBBBBBBBB-`m&HID1LA?input buffer 54 occupancy each 40000 clock cycles NJi1@JIHCO1 BBBBBBBBBBBBBBBBBBBB-`&HID1LA?input buffer 55 occupancy each 40000 clock cycles N1@HCO1 BBBBBBBBBBBBBBBBBBBB-`&JHID1LA?input buffer 56 occupancy each 40000 clock cycles N1@HCO1 dBBBBBBBBBBBBBBBBBBBB-`& HID1LA?input buffer 57 occupancy each 40000 clock cycles N`11@`_HCO1 BBBBBBBBBBBBBBBBBBBB-`5& HID1LA?input buffer 58 occupancy each 40000 clock cycles N11@HCO1 BBBBBBBBBBBBBBBBBBBB-`&` HID1LA?input buffer 59 occupancy each 40000 clock cycles N1@HCO1 BBBBBBBBBBBBBBBBBBBB-`& HID1LA?input buffer 60 occupancy each 40000 clock cycles NvG1@vuHCO1 BBBBBBBBBBBBBBBBBBBB-`K& HID1LA?input buffer 61 occupancy each 40000 clock cycles N(G1@('HCO1 BBBBBBBBBBBBBBBBBBBB-`&vHID1LA?input buffer 62 occupancy each 40000 clock cycles N1@HCO1 BBBBBBBBBBBBBBBBBBBB-`&(HID1LA?input buffer 63 occupancy each 40000 clock cycles N]1@HCO1 PBBBBBBBBBBBBBBBBBBBB-`a&HID1LA?input buffer 64 occupancy each 40000 clock cycles N>]1@>=HCO1 BBBBBBBBBBBBBBBBBBBB-`&HID1LA?input buffer 65 occupancy each 40000 clock cycles N1@HCO1 BBBBBBBBBBBBBBBBBBBB-`&>HID1LA?input buffer 66 occupancy each 40000 clock cycles Ns1@HCO1 BBBBBBBBBBBBBBBBBBBB-`w&HID1LA?input buffer 67 occupancy each 40000 clock cycles NT%s1@TSHCO1 BBBBBBBBBBBBBBBBBBBB-`)&HID1LA?input buffer 68 occupancy each 40000 clock cycles N%1@HCO1 BBBBBBBBBBBBBBBBBBBB-`&THID1LA?input buffer 69 occupancy each 40000 clock cycles N1@HCO1 xBBBBBBBBBBBBBBBBBBBB-`&HID1LA?input buffer 70 occupancy each 40000 clock cycles Nj;1@jiHCO1 dBBBBBBBBBBBBBBBBBBBB-`?&HID1LA?input buffer 71 occupancy each 40000 clock cycles N;1@HCO1 dBBBBBBBBBBBBBBBBBBBB-`&jHID1LA?input buffer 72 occupancy each 40000 clock cycles N1@HCO1 BBBBBBBBBBBBBBBBBBBB-`&HID1LA?input buffer 73 occupancy each 40000 clock cycles NQ1@HCO1 BBBBBBBBBBBBBBBBBBBB-`U&HID1LA?input buffer 74 occupancy each 40000 clock cycles N2Q1@21HCO1 BBBBBBBBBBBBBBBBBBBB-`&HID1LA?input buffer 75 occupancy each 40000 clock cycles N1@HCO1 BBBBBBBBBBBBBBBBBBBB-`&2HID1LA?input buffer 76 occupancy each 40000 clock cycles Ng1@HCO1 BBBBBBBBBBBBBBBBBBBB-`k&HID1LA?input buffer 77 occupancy each 40000 clock cycles NHg1@HGHCO1 dBBBBBBBBBBBBBBBBBBBB-`&HID1LA?input buffer 78 occupancy each 40000 clock cycles N1@HCO1 BBBBBBBBBBBBBBBBBBBB-`&HHID1LA?input buffer 79 occupancy each 40000 clock cycles N}1@HCO1 BBBBBBBBBBBBBBBBBBBB-`& HID1LA?input buffer 80 occupancy each 40000 clock cycles N^/}1@^]HCO1 xBBBBBBBBBBBBBBBBBBBB-`3&!HID1LA?input buffer 81 occupancy each 40000 clock cycles N/1@HCO1 BBBBBBBBBBBBBBBBBBBB-`&^"HID1LA?input buffer 82 occupancy each 40000 clock cycles N1@HCO1 dBBBBBBBBBBBBBBBBBBBB-`&#HID1LA?input buffer 83 occupancy each 40000 clock cycles NtE1@tsHCO1 BBBBBBBBBBBBBBBBBBBB-`I&$HID1LA?input buffer 84 occupancy each 40000 clock cycles N&E1@&%HCO1 dBBBBBBBBBBBBBBBBBBBB-`&t%HID1LA?input buffer 85 occupancy each 40000 clock cycles N1@HCO1 BBBBBBBBBBBBBBBBBBBB-`&&&HID1LA?input buffer 86 occupancy each 40000 clock cycles N[1@HCO1 BBBBBBBBBBBBBBBBBBBB-`_&'HID1LA?input buffer 87 occupancy each 40000 clock cycles N< [1@<;HCO1 BBBBBBBBBBBBBBBBBBBB-`&(HID1LA?input buffer 88 occupancy each 40000 clock cycles N 1@HCO1 BBBBBBBBBBBBBBBBBBBB-`&<)HID1LA?input buffer 89 occupancy each 40000 clock cycles Nq1@HCO1 BBBBBBBBBBBBBBBBBBBB-`u&*HID1LA?input buffer 90 occupancy each 40000 clock cycles NR#q1@RQHCO1 BBBBBBBBBBBBBBBBBBBB-`'&+HID1LA?input buffer 91 occupancy each 40000 clock cycles N#1@HCO1 xBBBBBBBBBBBBBBBBBBBB-`&R,HID1LA?input buffer 92 occupancy each 40000 clock cycles N1@HCO1 BBBBBBBBBBBBBBBBBBBB-`&-HID1LA?input buffer 93 occupancy each 40000 clock cycles Nh91@hgHCO1 BBBBBBBBBBBBBBBBBBBB-`=&.HID1LA?input buffer 94 occupancy each 40000 clock cycles N91@HCO1 BBBBBBBBBBBBBBBBBBBB-`&h/HID1LA?input buffer 95 occupancy each 40000 clock cycles #HID1LA?input buffer 83 occupancy each 40000 clock cycles NtE1@tsHCO1 BBBBBBBBBBBBBBBBBBBB-`I&$HID1LA?input buffer 84 occupancy each 40000 clock cycles N&E1@&%HCO1 dBBBBBBBBBBBBBBBBBBBB-`&t%HID1LA?input buffer 85 occupancy each 40000 clock cycles N1@HCO1 BBBBBBBBBBBBBBBBBBBB-`&&&HID1LA?input buffer 86 occupancy each 40000 clock cycles N[1@HCO1 BBBBBBBBBBBBBBBBBBBB-`_&'HID1LA?input buffer 87 occupancy each 40000 clock cycles N< [1@<;HCO1 BBBBBBBBBBBBBBBBBBBB-`&(HID1LA?input buffer 88 occupancy each 40000 clock cycles N 1@HCO1 BBBBBBBBBBBBBBBBBBBB-`&<)HID1LA?input buffer 89 occupancy each 40000 clock cycles Nq1@