-- ۀۀ}?&) S<% Vۀdnx456789:;<=>?@ABCDEFG}HyIuJqKmLiMeNaO]PYQURQSMIEAe=o951-)%!  ۀcSۀSۀSۀjSۀSۀSۀqSۀSۀSۀxSۀ%SۀSۀSۀ,SۀSۀSۀ3SۀSۀSۀ:SۀSۀSۀBRۀRۀRۀLRۀRۀRۀVRۀRۀRۀ`RۀPۀPۀAۀqۀZۀZZۀZۀdۀۀ,ۀ ۀ ۀ Xۀ ۀ  ۀ  ۀ ۀ Lۀ ۀ ۀ xۀ ۀ @ ۀ ۀ ۀ lۀ ۀ 4ۀ  ۀ ۀ bۀ ۀ ,ۀ ۀ ۀ [ ۀ ۀ %ۀ ۀ ۀ  ۀy9ۀ Yۀ}ۀ)zۀ{ۀ$ۀf$ۀC#ۀwۀ/.h/.1@//HCO1 ????-`.l3S3QdHID1 E;=Ltrigger times r.N-.h1@.N.MHCO1H ?@@-`-3S/nHID1p>Bv?number of min bias pileup evts -)-1@--HCO1 ????-`)3S.NxHID1Dy?Number of 32 bit words in event fragment)%)1@))HCO1 -`%3S-HID1Dy?Latency: triggered BCO to MCC output in us %!%1@%%HCO1 ????-`!3S)HID1Dy?Latency: triggered BCO to ROD output in us v!~ $!1@!~!}HCO1J :FeCBBA0@@???-` (3S%HID1t@C?pileup hits per column pair per event u  $1@  HCO1J C ?@@-`3S!~HID1s@C?b jet hits per column pair per eventx71@HCO1J :FeCBBA0@@???-`;3S HID1v@C?hits/column-pair/event, pixel barrel 2, unscaledT71@HCO1# :FeCBBA0@@???-`3SHID1RA?hits/column-pair/event with EOC buffer limit, pixel barrel 241@HCO1  hA AA A@A`@A@@A@@@@?@@@??-`3SHID12C?hits/link/event, pixel barrel 2 1@HCO1 ?-`3SHID1F<output memory 0 occupancy 1@HCO1 ?-`3SHID1F<output memory 1 occupancy K1@HCO1n ?-`O3S4HID1dC>input buffer 0 occupancy3K1@32HCO1n ?-`3S5HID1dC>input buffer 1 occupancy1@HCO1n ?-`#3S36HID1dC>input buffer 2 occupancy1@HCO1n ?-`3S7HID1dC>input buffer 3 occupancyq1@qpHCO1n ?-`3S8HID1dC>input buffer 4 occupancy]1@HCO1n ?-`a3Sq9HID1dC>input buffer 5 occupancyE]1@EDHCO1n ?-`3S:HID1dC>input buffer 6 occupancy11@HCO1n ?-`53SE;HID1dC>input buffer 7 occupancy11@HCO1n ?-`3Sinput buffer 8 occupancy1@HCO1n ?-` 3S=HID1dC>input buffer 9 occupancyn1@HCO1n ?-`r3S>HID1dC>input buffer 10 occupancy Un1@UTHCO1n ?-`3S?HID1dC>input buffer 11 occupancy @1@HCO1n ?-`D3SU@HID1dC>input buffer 12 occupancy '@1@'&HCO1n ?-`3SAHID1dC>input buffer 13 occupancy 1@HCO1n ?-`3S'BHID1dC>input buffer 14 occupancy {1@HCO1n ?-`3SCHID1dC>input buffer 15 occupancy b{1@baHCO1n ?-`3SDHID1dC>input buffer 16 occupancy M1@HCO1n ?-`Q3SbEHID1dC>input buffer 17 occupancy 4 M1@43HCO1n ?-` 3SFHID1dC>input buffer 18 occupancy    1@  HCO1n ?-` #3S4GHID1dC>input buffer 19 occupancy    1@  HCO1n ?-` 3S HHID1dC>input buffer 20 occupancy  o  1@ o nHCO1n ?-` 3S IHID1dC>input buffer 21 occupancy   Z 1@  HCO1n ?-` ^3S oJHID1dC>input buffer 22 occupancy  A  Z1@ A @HCO1n ?-` 3S KHID1dC>input buffer 23 occupancy   , 1@  HCO1n ?-` 03S ALHID1dC>input buffer 24 occupancy    ,1@  HCO1n ?-` 3S MHID1dC>input buffer 25 occupancy  | 1@ | {HCO1n ?-` 3S NHID1dC>input buffer 26 occupancy g1@HCO1n ?-`k3S |OHID1dC>input buffer 27 occupancy Ng1@NMHCO1n ?-`3SPHID1dC>input buffer 28 occupancy 91@HCO1n ?-`=3SNQHID1dC>input buffer 29 occupancy  91@ HCO1n ?-`3SRHID1dC>input buffer 30 occupancy  1@HCO1n ?-`3S SHID1dC>input buffer 31 occupancy U 1@HCO1* AAAPA@AA0A@AAAAApAA@AAAAPA@AA`AAAA-`3SHID1S A?peak input buffer occupancy by link Ua1@HCO1* -`e3SHID1S A?events in header-only mode by link UF a1@FEHCO1* -`3SHID1S A?mean input buffer occupancy by link l  vtHAUT1@HCO1n d-`v3SFeHID1dtriggers per 40000 clock cycles vs time <d1@HCO1 OAAAA-`h3SoHID1:@?min bias pileup events every 40000 clock cycles KHd1@HGHCO1 CCCCCCCCCCCCCCCCCCCC-`3SHID1IA?output memory 0 each 40000 clock cycles K1@HCO1 CCCCCCCCCCCCCCCCCCCC-`3SHHID1IA?output memory 1 each 40000 clock cycles M1@HCO1 @AAAAAAAAAAAAAAAAAAAA-`3SHID1KA?input buffer 0 occupancy each 40000 clock cyclesMc41@cbHCO1 AAAAAAAAAAAAAAAAAAAA-`83SHID1KA?input buffer 1 occupancy each 40000 clock cyclesM41@HCO1 APAPAPAPAPAPAPAPAPAPAPAPAPAPAPAPAPAPAPAP-`3ScHID1KA?input buffer 2 occupancy each 40000 clock cyclesM1@HCO1 A@A@A@A@A@A@A@A@A@A@A@A@A@A@A@A@A@A@A@A@-`3SHID1KA?input buffer 3 occupancy each 40000 clock cyclesM|M1@|{HCO1 AAAAAAAAAAAAAAAAAAAA-`Q3SHID1KA?input buffer 4 occupancy each 40000 clock cyclesM/M1@/.HCO1 A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0-`3S|HID1KA?input buffer 5 occupancy each 40000 clock cyclesM1@HCO1 @AAAAAAAAAAAAAAAAAAAA-`3S/HID1KA?input buffer 6 occupancy each 40000 clock cyclesMf1@HCO1 -`j3SHID1KA?input buffer 7 occupancy each 40000 clock cyclesMHf1@HGHCO1 @@@@@@@@@@@@@@@@@@@@-`3SHID1KA?input buffer 8 occupancy each 40000 clock cyclesM1@HCO1 hAAAAAAAAAAAAAAAAAAAA-`3SHHID1KA?input buffer 9 occupancy each 40000 clock cyclesN~1@HCO1 AAAAAAAAAAAAAAAAAAAA-`3SHID1LA?input buffer 10 occupancy each 40000 clock cycles N_0~1@_^HCO1 AAAAAAAAAAAAAAAAAAAA-`43SHID1LA?input buffer 11 occupancy each 40000 clock cycles N01@HCO1 TAAAAAAAAAAAAAAAAAAAA-`3S_HID1LA?input buffer 12 occupancy each 40000 clock cycles N1@HCO1 ,ApApApApApApApApApApApApApApApApApApApAp-`3SHID1LA?input buffer 13 occupancy each 40000 clock cycles NuF1@utHCO1 hAAAAAAAAAAAAAAAAAAAA-`J3SHID1LA?input buffer 14 occupancy each 40000 clock cycles N'F1@'&HCO1 -`3SuHID1LA?input buffer 15 occupancy each 40000 clock cycles N1@HCO1 A@A@A@A@A@A@A@A@A@A@A@A@A@A@A@A@A@A@A@A@-`3S'HID1LA?input buffer 16 occupancy each 40000 clock cycles N\1@HCO1 hAAAAAAAAAAAAAAAAAAAA-``3SHID1LA?input buffer 17 occupancy each 40000 clock cycles N=\1@=<HCO1 hAAAAAAAAAAAAAAAAAAAA-`3SHID1LA?input buffer 18 occupancy each 40000 clock cycles N1@HCO1 AAAAAAAAAAAAAAAAAAAA-`3S=HID1LA?input buffer 19 occupancy each 40000 clock cycles Nr1@HCO1 APAPAPAPAPAPAPAPAPAPAPAPAPAPAPAPAPAPAPAP-`v3SHID1LA?input buffer 20 occupancy each 40000 clock cycles NS$r1@SRHCO1 A@A@A@A@A@A@A@A@A@A@A@A@A@A@A@A@A@A@A@A@-`(3SHID1LA?input buffer 21 occupancy each 40000 clock cycles N$1@HCO1 AAAAAAAAAAAAAAAAAAAA-`3SSHID1LA?input buffer 22 occupancy each 40000 clock cycles N1@HCO1 -`3SHID1LA?input buffer 23 occupancy each 40000 clock cycles Ni:1@ihHCO1 A`A`A`A`A`A`A`A`A`A`A`A`A`A`A`A`A`A`A`A`-`>3SHID1LA?input buffer 24 occupancy each 40000 clock cycles N:1@HCO1 AAAAAAAAAAAAAAAAAAAA-`3SiHID1LA?input buffer 25 occupancy each 40000 clock cycles N1@HCO1 TAAAAAAAAAAAAAAAAAAAA-`3SHID1LA?input buffer 26 occupancy each 40000 clock cycles NP1@~HCO1 hAAAAAAAAAAAAAAAAAAAA-`T3SHID1LA?input buffer 27 occupancy each 40000 clock cycles N1P1@10HCO1 AAAAAAAAAAAAAAAAAAAA-`3SHID1LA?input buffer 28 occupancy each 40000 clock cycles N1@HCO1 -`3S1HID1LA?input buffer 29 occupancy each 40000 clock cycles Nf1@HCO1 -`j3SHID1LA?input buffer 30 occupancy each 40000 clock cycles NGf1@GFHCO1 -`3SHID1LA?input buffer 31 occupancy each 40000 clock cycles HID1LA?input buffer 19 occupancy each 40000 clock cycles Nr1@HCO1 APAPAPAPAPAPAPAPAPAPAPAPAPAPAPAPAPAPAP