

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
length: 0x26, numMsgs= 0x2, primListRevision= 111
allPrimCount: 2, replyLength: 0x10, replyCount: 0x2
===========================================================
Master DSP SDRAM Test: Address 0x02100000 to 0x03000000
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
index: 0,  id: 0x6, primRevision: 102, length: 0x10, replyLength: 0x5
MEMORY_TEST
*start= 0x2100000, size= 0x7BFC00
repetitions[]={ 0x1, 0x1, 0x1, 0x1, 0x1, 0x0 }
errorsBeforeFail= 0x1000, continueOnError= 1, nReads= 0x1, dmaFlag= 1
===========================================================
Master DSP SDRAM Test: Address 0x02100000 to 0x03000000
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
index: 1,  id: 0x6, primRevision: 102, length: 0x10, replyLength: 0x5
MEMORY_TEST
*start= 0x2100000, size= 0x7BFC00
repetitions[]={ 0x1, 0x0, 0x0, 0x0, 0x0, 0x0 }
errorsBeforeFail= 0x1000, continueOnError= 1, nReads= 0x100, dmaFlag= 1
