------------------------------------------------------------------------------- -- Lawrence Berkeley National Laboratory ------------------------------------------------------------------------------- -- Filename: top.vhd -- Title: FPGA Program Reset Manager -- Description: This FPGA controls configuration of all FPGA parts, and -- controls the reset signals to all FPGAs and DSPs on the -- Read Out Driver Board used in Atlas. -- -- Constraints required to that define the location of the FPGA PRM global -- clocks and DLLs, and are used to properly synthesize the proto-type ver: -- -- INST main_clk_dll LOC = DLL0; -> Location of the main clk dll -- INST clk40_bufg LOC = GCLKBUF0; -> Location of the main clk global bus -- INST cclk_bufg LOC = GCLKBUF1; -> Location of the cclk global bus -- INST reset_bufg LOC = GCLKBUF2; -> Location of the reset global bus -- INST vme_clk_bufg LOC = GCLKBUF3; -> Location of the vme clk global bus -- -- NET clk40_in PERIOD = 25ns; -> Define period of system clock input -- NET clk40_i PERIOD = 25ns; -> Define period of internal system clock -- NET vme_clk_in PERIOD = 16ns; -> Define period of vme clock input -- NET vme_clk_in PERIOD = 16ns; -> Define period of internal vme clock -- ------------------------------------------------------------------------------- -- Author: John Joseph ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Revision History ------------------------------------------------------------------------------- -- -- June 8, 2000 JMJ defined top ports to match schematic requirements -- Aug 21, 2000 JMJ began to revise code for first prototype -- ------------------------------------------------------------------------------- -- Library Declaration ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; --needed for logical operations use IEEE.std_logic_arith.all; --needed for +/- operations -- comment out the 2 UNISIM lines for synthesis using Foundation 3.1i --library UNISIM; --use unisim.all; ------------------------------------------------------------------------------- -- PORT DECLARATION ------------------------------------------------------------------------------- entity fpga_prm_top is port ( -- clock and reset ports clk40_in : in std_logic; vme_clk_in : in std_logic; rst_n_in : in std_logic; -- FLASH memory I/O and control ports memory_address_out : out std_logic_vector(18 downto 0); memory_data : inout std_logic_vector( 7 downto 0); CE0_n_out : out std_logic; OE0_n_out : out std_logic; WE0_n_out : out std_logic; CE1_n_out : out std_logic; OE1_n_out : out std_logic; WE1_n_out : out std_logic; CE2_n_out : out std_logic; OE2_n_out : out std_logic; WE2_n_out : out std_logic; -- dsp I/O and Reset command ports mdsp_hd : inout std_logic_vector(15 downto 0); mdsp_hrdy_n_in : in std_logic; -- HRDY from the Master DSP mdsp_hhwil_out : out std_logic; -- HHWIL to the Master DSP mdsp_hcntl0_out : out std_logic; -- HCNTL0 to the Master DSP mdsp_hcntl1_out : out std_logic; -- HCNTL1 to the Master DSP mdsp_hds1_n_out : out std_logic; -- HDS1_N to the Master DSP mdsp_hcs_n_out : out std_logic; -- HCS_N to the Master DSP mdsp_hrnw_out : out std_logic; -- HRNW to the Master DSP -- RCF Reset command ports reset_cmds_in : in std_logic_vector(1 downto 0); -- Reset Cmd from the RRIF reset_cmds_out : out std_logic_vector(1 downto 0); -- Ack and clear of Reset Cmd to RRIF -- vme interface ports vme_addr_in : in std_logic_vector(31 downto 0); vme_data_inout : inout std_logic_vector(31 downto 0); vme_rnw_in : in std_logic; vme_ce_n_in : in std_logic_vector(5 downto 0); vme_be_n_in : in std_logic_vector(3 downto 0); vme_translator_en_n_out : out std_logic; vme_dtack_n_out : out std_logic; -- VME LACK_N vme_lden_n_in : in std_logic; svic_region_out : out std_logic_vector(2 downto 0); board_addr_n_in : in std_logic_vector(4 downto 0); -- ROD Status rod_busy_in : in std_logic; rod_busy_n_out : out std_logic; -- fpga programming and reset control/handshaking ports formA_prgbits_out : out std_logic; formA_cclk_out : out std_logic; formA_prgm_n_out : out std_logic; formA_done_in : in std_logic; formA_init_n_in : in std_logic; formA_rst_n_out : out std_logic; formB_prgbits_out : out std_logic; formB_cclk_out : out std_logic; formB_prgm_n_out : out std_logic; formB_done_in : in std_logic; formB_init_n_in : in std_logic; formB_rst_n_out : out std_logic; efb_prgbits_out : out std_logic; efb_cclk_out : out std_logic; efb_prgm_n_out : out std_logic; efb_done_in : in std_logic; efb_init_n_in : in std_logic; efb_rst_n_out : out std_logic; router_prgbits_out : out std_logic; router_cclk_out : out std_logic; router_prgm_n_out : out std_logic; router_done_in : in std_logic; router_init_n_in : in std_logic; router_rst_n_out : out std_logic; rodresio_prgbits_out : out std_logic; rodresio_cclk_out : out std_logic; rodresio_prgm_n_out : out std_logic; rodresio_done_in : in std_logic; rodresio_init_n_in : in std_logic; rodresio_rst_n_out : out std_logic; fpga_pgrm_done_out : out std_logic; -- dsp reset ports dsp_rst_n_out : out std_logic_vector(4 downto 0); -- ROD serial number inputs serial_number_n_in : in std_logic_vector(9 downto 0); rod_clock_select_in : in std_logic; -- test signal & spare output ports test_out : out std_logic_vector(7 downto 0); spare_pin : out std_logic_vector(7 downto 0) ); end fpga_prm_top; architecture rtl of fpga_prm_top is ------------------------------------------------------------------------------- --SIGNAL DECLARATION ------------------------------------------------------------------------------- -- internal version of power and ground signals signal pwr : std_logic; signal gnd : std_logic; -- internal clock signals signal clk40_g : std_logic; signal clk05_g : std_logic; signal vme_clk_g : std_logic; signal cclk_g : std_logic; -- ROD clock select Status signal rod_clk_sel_p : std_logic; -- clock signals attached to the main_clk_dll module signal dll_clk40_in : std_logic; signal dll_clk40_out : std_logic; signal dll_clk05_out : std_logic; signal clk40_locked_i : std_logic; signal vme_clk_ibufg_o : std_logic; signal dll_vme_clk_out : std_logic; signal dll_cclk_out : std_logic; signal vme_clk_locked_i : std_logic; attribute CLKDV_DIVIDE : string; -- divide attribute for main_clk_dll / divide by 8 (5 MHz | 200ns) attribute CLKDV_DIVIDE of main_clk_dll : label is "8"; -- divide attribute for vme_clk_dll / divide by 16 (3.75 MHz | 267ns) attribute CLKDV_DIVIDE of vme_clk_dll : label is "16"; -- internal async reset signal signal rst_n_i : std_logic; signal rst_i : std_logic; signal rst_n_ibuf_o : std_logic; -- internal flash memory signals signal flash_mem_addr_out_i : std_logic_vector(18 downto 0); signal flash_mem_data_out_i : std_logic_vector(7 downto 0); signal flash_mem_data_in_i : std_logic_vector(7 downto 0); signal memory_data_dir_en_i : std_logic; signal WE_n_out_i : std_logic; signal OE_n_out_i : std_logic; signal CE0_n_out_i : std_logic; signal CE1_n_out_i : std_logic; signal CE2_n_out_i : std_logic; signal flash_addr_i : std_logic_vector(23 downto 0); signal flash_data_out_i : std_logic_vector(7 downto 0); signal flash_data_in_i : std_logic_vector(7 downto 0); signal flash_cmd_reg_i : std_logic_vector(2 downto 0); signal flash_status_reg_i : std_logic_vector(2 downto 0); -- internal reset cmd interface signals signal mdsp_hpi_data_in_i : std_logic_vector(15 downto 0); signal mdsp_hpi_data_out_i : std_logic_vector(15 downto 0); signal mdsp_hpi_data_dir_i : std_logic; signal mdsp_cen_n_i : std_logic; signal mdsp_cen_i : std_logic; signal mdsp_rnw_i : std_logic; signal mdsp_hrdy_n_i : std_logic; signal mdsp_hhwil_i : std_logic; signal mdsp_hcntl0_i : std_logic; signal mdsp_hcntl1_i : std_logic; signal mdsp_hds1_n_i : std_logic; signal reset_cmds_in_i : std_logic_vector(1 downto 0); signal reset_cmds_out_i : std_logic_vector(1 downto 0); signal data_strb_i : std_logic; -- internal vmebus signals signal vme_data_out_p : std_logic_vector(31 downto 0); signal vme_data_in_p : std_logic_vector(31 downto 0); signal vme_prm_out_i : std_logic_vector(31 downto 0); signal vme_hpi_do_i : std_logic_vector(31 downto 0); signal vme_addr_i : std_logic_vector(31 downto 0); signal vme_be_n_p : std_logic_vector( 3 downto 0); signal vme_be_n_i : std_logic_vector( 3 downto 0); signal vme_ce_n_i : std_logic_vector( 5 downto 0); signal vme_ce_i : std_logic_vector( 5 downto 0); signal vme_trans_en_n_i : std_logic; signal vme_rnw_p : std_logic; signal vme_rnw_i : std_logic; signal vme_lden_n_p : std_logic; signal vme_dtack_n_i : std_logic; signal vme_data_dir_i : std_logic; signal svic_region_i : std_logic_vector(2 downto 0); signal board_addr_n_i : std_logic_vector(4 downto 0); -- program reset manager bus signals signal prm_cen_i : std_logic; signal prm_rnw_i : std_logic; -- internal fpga configuration signals signal efb_prgbits_out_i : std_logic; signal efb_cclk_out_i : std_logic; signal efb_prgm_n_out_i : std_logic; signal efb_done_in_i : std_logic; signal efb_init_n_in_i : std_logic; signal efb_rst_n_out_i : std_logic; signal efb_rst_n_out_p : std_logic; signal efb_halt_i : std_logic; signal formA_prgbits_out_i : std_logic; signal formA_cclk_out_i : std_logic; signal formA_prgm_n_out_i : std_logic; signal formA_done_in_i : std_logic; signal formA_init_n_in_i : std_logic; signal formA_rst_n_out_i : std_logic; signal formA_rst_n_out_p : std_logic; signal formA_halt_i : std_logic; signal formB_prgbits_out_i : std_logic; signal formB_cclk_out_i : std_logic; signal formB_prgm_n_out_i : std_logic; signal formB_done_in_i : std_logic; signal formB_init_n_in_i : std_logic; signal formB_rst_n_out_i : std_logic; signal formB_rst_n_out_p : std_logic; signal formB_halt_i : std_logic; signal router_prgbits_out_i : std_logic; signal router_cclk_out_i : std_logic; signal router_prgm_n_out_i : std_logic; signal router_done_in_i : std_logic; signal router_init_n_in_i : std_logic; signal router_rst_n_out_i : std_logic; signal router_rst_n_out_p : std_logic; signal router_halt_i : std_logic; signal rodresio_prgbits_out_i : std_logic; signal rodresio_cclk_out_i : std_logic; signal rodresio_prgm_n_out_i : std_logic; signal rodresio_done_in_i : std_logic; signal rodresio_init_n_in_i : std_logic; signal rodresio_rst_n_out_i : std_logic; signal rodresio_rst_n_out_p : std_logic; signal rodresio_halt_i : std_logic; -- internal dsp signal dsp_rst_n_out_i : std_logic_vector(4 downto 0); -- internal configuration and status signals signal fpga_pgrm_done_out_i : std_logic; -- indicates that config is complete signal fpga_pgrm_done_out_p : std_logic; -- indicates that config is complete signal fpga_sel_i : std_logic_vector(2 downto 0); signal fpga_rst_status_reg_i : std_logic_vector(4 downto 0); signal dsp_rst_status_reg_i : std_logic_vector(4 downto 0); -- internal shift register control, status, and data bits signal shift_reg0_load_i : std_logic; signal shift_reg1_load_i : std_logic; signal sr_cnfg_data_i : std_logic; signal sr_cnfg_data0_i : std_logic; signal sr_cnfg_data1_i : std_logic; signal shift_reg_en_i : std_logic_vector(1 downto 0); signal shift_reg_en_d1 : std_logic_vector(1 downto 0); signal shift_reg_load_en_i : std_logic_vector(1 downto 0); -- internal control signals (the names should define) signal cnfg_enable_i : std_logic; -- flag to indicate that prm is in cnfg mode signal cnfg_addr_i : std_logic_vector(23 downto 0); -- cnfg data addr location signal cnfg_data_i : std_logic_vector( 7 downto 0); -- internal cnfg data path signal clr_cnfg_reg_i : std_logic; signal fpga_cnfg_reg_i : std_logic_vector( 6 downto 0); signal fpga_rst_reg_i : std_logic_vector( 6 downto 0); signal dsp_rst_reg_i : std_logic_vector( 5 downto 0); signal reset_dsp_i : std_logic_vector( 5 downto 0); signal dsp_reset_cmd_i : std_logic_vector( 3 downto 0); signal clr_rst_reg_i : std_logic; signal fetch_cnfg_loc_i : std_logic; -- flag to indicate fetch of location data signal cnfg_start_addr_i : std_logic_vector(23 downto 0); signal cnfg_stop_addr_i : std_logic_vector(23 downto 0); signal rod_busy_p : std_logic; signal rod_busy_i : std_logic; signal rod_busy_n_i : std_logic; signal serial_number_n_p : std_logic_vector( 9 downto 0); signal serial_number_n_i : std_logic_vector( 9 downto 0); signal serial_number_i : std_logic_vector( 9 downto 0); ------------------------------------------------------------------------------- --COMPONENT DECLARATION ------------------------------------------------------------------------------- -- The shift register converts the flash data from an 8-bit word to a serial -- stream with the LSB out first. Two shift registers are used in the design -- to ensure a continuous stream of configuration bits to the FPGAs. component shift_register port ( clk_in : in std_logic; -- cclk input rst_n_in : in std_logic; -- reset input en_load_in : in std_logic; -- enable load en_shift_in : in std_logic; -- enable shift data_in : in std_logic_vector(7 downto 0); -- 8-bit word in data_out : out std_logic -- single bit out ); end component; -- The register block preforms all register function required by the FPGA PRM component progman_register_block port ( clk_in : in std_logic; -- clk40 input rst_n_in : in std_logic; -- async global reset prb_bus_strb_in : in std_logic; prb_bus_ce_in : in std_logic; prb_bus_rnw_in : in std_logic; prb_bus_addr_in : in std_logic_vector(31 downto 0); prb_bus_data_in : in std_logic_vector(31 downto 0); prb_bus_data_out : out std_logic_vector(31 downto 0); prb_rrif_done_in : in std_logic; prb_rrif_init_n_in : in std_logic; prb_rrif_halt_in : in std_logic; prb_formA_done_in : in std_logic; prb_formA_init_n_in : in std_logic; prb_formA_halt_in : in std_logic; prb_formB_done_in : in std_logic; prb_formB_init_n_in : in std_logic; prb_formB_halt_in : in std_logic; prb_efb_done_in : in std_logic; prb_efb_init_n_in : in std_logic; prb_efb_halt_in : in std_logic; prb_router_done_in : in std_logic; prb_router_init_n_in : in std_logic; prb_router_halt_in : in std_logic; prb_fpga_rst_status_reg_in : in std_logic_vector( 4 downto 0); prb_dsp_rst_status_reg_in : in std_logic_vector( 4 downto 0); fpga_cnfg_reg_out : out std_logic_vector( 6 downto 0); fpga_rst_reg_out : out std_logic_vector( 6 downto 0); dsp_rst_reg_out : out std_logic_vector( 5 downto 0); flash_cmd_reg_out : out std_logic_vector( 2 downto 0); flash_status_reg_in : in std_logic_vector( 2 downto 0); flash_addr_reg_out : out std_logic_vector(23 downto 0); flash_data_reg_in : in std_logic_vector( 7 downto 0); flash_data_reg_out : out std_logic_vector( 7 downto 0); clr_cnfg_reg_in : in std_logic; clr_rst_reg_in : in std_logic; prb_cnfg_en_in : in std_logic; cnfg_start_reg_in : in std_logic_vector(23 downto 0); cnfg_stop_reg_in : in std_logic_vector(23 downto 0); serial_number_in : in std_logic_vector( 9 downto 0); rod_busy_in : in std_logic; rod_clk_status_in : in std_logic; vme_clk_status_in : in std_logic; rod_clk_select_in : in std_logic ); end component; -- The flash decoder block interfaces the FPGA PRM with the Flash Memory ICs component flash_decoder_block port ( clk_in : in std_logic; cclk_in : in std_logic; rst_n_in : in std_logic; fdb_addr_in : in std_logic_vector(23 downto 0); fdb_data_in : in std_logic_vector(7 downto 0); fdb_data_out : out std_logic_vector(7 downto 0); fdb_cr_in : in std_logic_vector(2 downto 0); fdb_sr_out : out std_logic_vector(2 downto 0); cnfg_enable_in : in std_logic; cnfg_addr_in : in std_logic_vector(23 downto 0); cnfg_data_out : out std_logic_vector(7 downto 0); memory_addr_out : out std_logic_vector(18 downto 0); memory_data_in : in std_logic_vector(7 downto 0); memory_data_out : out std_logic_vector(7 downto 0); write_en_n_out : out std_logic; output_en_n_out : out std_logic; CE0_n_out : out std_logic; CE1_n_out : out std_logic; CE2_n_out : out std_logic; shift_reg_load_in : in std_logic_vector(1 downto 0); fetch_cnfg_loc_in : in std_logic ); end component; component fpga_cnfg_reset_controller_block port ( clk_in : in std_logic; cclk_in : in std_logic; rst_n_in : in std_logic; cb_formA_done_in : in std_logic; cb_formA_init_n_in : in std_logic; cb_formA_halt_out : out std_logic; cb_formB_done_in : in std_logic; cb_formB_init_n_in : in std_logic; cb_formB_halt_out : out std_logic; cb_efb_done_in : in std_logic; cb_efb_init_n_in : in std_logic; cb_efb_halt_out : out std_logic; cb_router_done_in : in std_logic; cb_router_init_n_in : in std_logic; cb_router_halt_out : out std_logic; cb_rrif_done_in : in std_logic; cb_rrif_init_n_in : in std_logic; cb_rrif_halt_out : out std_logic; cb_fpga_cnfg_reg_in : in std_logic_vector( 5 downto 0); cb_clr_cnfg_reg_out : out std_logic; cb_fpga_rst_reg_in : in std_logic_vector( 5 downto 0); cb_dsp_rst_reg_in : in std_logic_vector( 5 downto 0); cb_clr_rst_reg_out : out std_logic; cb_fpga_rst_status_reg_out : out std_logic_vector( 4 downto 0); cb_dsp_rst_status_reg_out : out std_logic_vector( 4 downto 0); cnfg_enable_out : out std_logic; cnfg_done_out : out std_logic; cnfg_addr_out : out std_logic_vector(23 downto 0); cnfg_data_in : in std_logic_vector(7 downto 0); cb_rrif_prgm_n_out : out std_logic; cb_formA_prgm_n_out : out std_logic; cb_formB_prgm_n_out : out std_logic; cb_efb_prgm_n_out : out std_logic; cb_router_prgm_n_out : out std_logic; cb_rrif_rst_n_out : out std_logic; cb_formA_rst_n_out : out std_logic; cb_formB_rst_n_out : out std_logic; cb_efb_rst_n_out : out std_logic; cb_router_rst_n_out : out std_logic; fpga_sel_out : out std_logic_vector(2 downto 0); shift_reg_en_out : out std_logic_vector(1 downto 0); shift_reg_load_out : out std_logic_vector(1 downto 0); fetch_cnfg_loc_out : out std_logic; cb_mdsp_rst_n_out : out std_logic; cb_sdsp0_rst_n_out : out std_logic; cb_sdsp1_rst_n_out : out std_logic; cb_sdsp2_rst_n_out : out std_logic; cb_sdsp3_rst_n_out : out std_logic; cnfg_start_addr_out : out std_logic_vector(23 downto 0); cnfg_stop_addr_out : out std_logic_vector(23 downto 0); cnfg_override_in : in std_logic ); end component; component hpi_data_controller port ( clk_in : in std_logic; -- vme_clk66 input rst_n_in : in std_logic; -- asynchronous global reset svic_region_in : in std_logic_vector( 2 downto 0); mdsp_cen_in : in std_logic; -- MDSP CE_N signal in mdsp_ds_in : in std_logic; -- MDSP Data Strobe (VME BE) mdsp_hrdy_n_in : in std_logic; -- Master DSP HRDY_N signal mdsp_hpi_data_in : in std_logic_vector(15 downto 0); -- mdsp_hpi_data_out : out std_logic_vector(15 downto 0); -- mdsp_cen_n_out : out std_logic; -- MDSP CE_N signal out mdsp_rnw_out : out std_logic; -- MDSP RNW signal out mdsp_hhwil_out : out std_logic; -- MDSP HHWIL signal mdsp_hds1_n_out : out std_logic; -- MDSP HHDS1 signal vme_bus_rnw_in : in std_logic; -- VMEBus read/not_write signal mdsp_vme_data_in : in std_logic_vector(31 downto 0); -- mdsp_vme_data_out : out std_logic_vector(31 downto 0); -- vme_dtack_n_out : out std_logic; -- VMEBus LACK_N lvme_cen_in : in std_logic_vector(5 downto 0) ); end component; component vme_address_decoder is port ( clk_in : in std_logic; -- VMEBus clk (60MHz) rst_n_in : in std_logic; -- asynchronous reset (active low) rod_addr_n_in : in std_logic_vector( 4 downto 0); -- GA bits must be inv lvme_addr_in : in std_logic_vector(11 downto 0); -- VMEBus Addr (31:20) lvme_be_n_in : in std_logic_vector( 3 downto 0); -- LVME Byte Enables lvme_cs_n_in : in std_logic_vector( 5 downto 0); -- LVME Chip Selects prm_cen_out : out std_logic; -- PRM Register Block CS mdsp_cen_out : out std_logic; -- MDSP HPI State Machine Enable data_strb_out : out std_logic; -- VME BE signal svic_region_out : out std_logic_vector( 2 downto 0) -- region map output ); end component; component reset_command_controller is port ( clk40_in : in std_logic; clk05_in : in std_logic; rst_n_in : in std_logic; clr_reset_cmd_in : in std_logic; rod_busy_in : in std_logic; reset_commands_in : in std_logic_vector(1 downto 0); reset_commands_out : out std_logic_vector(1 downto 0); reset_sdsp_out : out std_logic_vector(3 downto 0) ); end component; ------------------------------------------------------------------------------- -- PAD DECLARATIONS ------------------------------------------------------------------------------- component IBUFG port (I : in STD_LOGIC; O : out STD_LOGIC); end component; component BUFG port (I : in STD_LOGIC; O : out STD_LOGIC); end component; component IBUF port (I : in STD_LOGIC; O : out STD_LOGIC); end component; component OBUF port (I : in STD_LOGIC; O : out STD_LOGIC); end component; component IOBUF port ( I : in STD_LOGIC; O : out STD_LOGIC; IO : inout STD_LOGIC; T : in STD_LOGIC ); end component; component OBUFT port ( I : in STD_LOGIC; O : out STD_LOGIC; T : in STD_LOGIC ); end component; component PULLUP port (O : out STD_LOGIC); end component; ------------------------------------------------------------------------------- -- XILINX PARTS SPECIFIC COMPONENTS/SIGNALS ------------------------------------------------------------------------------- component STARTUP_VIRTEX port ( GSR : in std_logic; GTS : in std_logic; CLK : in std_logic ); end component; component CLKDLL port ( CLK0 : out STD_LOGIC; CLK90 : out STD_LOGIC; CLK180 : out STD_LOGIC; CLK270 : out STD_LOGIC; CLK2X : out STD_LOGIC; CLKDV : out STD_LOGIC; LOCKED : out STD_LOGIC; CLKIN : in STD_LOGIC; CLKFB : in STD_LOGIC; RST : in STD_LOGIC ); end component; ------------------------------------------------------------------------------- -- SIGNAL ASSIGNMENTS ------------------------------------------------------------------------------- begin pwr <= '1'; gnd <= '0'; rst_i <= not rst_n_i; memory_data_dir_en_i <= WE_n_out_i; shift_reg0_load_i <= shift_reg_load_en_i(0); shift_reg1_load_i <= shift_reg_load_en_i(1); reset_dsp_i <= dsp_rst_reg_i OR '0' & dsp_reset_cmd_i & '0'; rodresio_rst_n_out_p <= rodresio_rst_n_out_i AND NOT fpga_rst_reg_i(6); formA_rst_n_out_p <= formA_rst_n_out_i AND NOT fpga_rst_reg_i(6); formB_rst_n_out_p <= formB_rst_n_out_i AND NOT fpga_rst_reg_i(6); efb_rst_n_out_p <= efb_rst_n_out_i AND NOT fpga_rst_reg_i(6); router_rst_n_out_p <= router_rst_n_out_i AND NOT fpga_rst_reg_i(6); ------------------------------------------------------------------------------- -- XILINX PARTS SPECIFIC COMPONENTS/SIGNALS ------------------------------------------------------------------------------- U1 : STARTUP_VIRTEX port map ( GSR => rst_i, GTS => rst_i, CLK => cclk_g ); -------------------------------------------------------------------------------- --COMPONENT INSTANTIATION -------------------------------------------------------------------------------- U2 : fpga_cnfg_reset_controller_block port map ( clk_in => vme_clk_g, cclk_in => cclk_g, rst_n_in => rst_n_i, cb_formA_done_in => formA_done_in_i, cb_formA_init_n_in => formA_init_n_in_i, cb_formA_halt_out => formA_halt_i, cb_formB_done_in => formB_done_in_i, cb_formB_init_n_in => formB_init_n_in_i, cb_formB_halt_out => formB_halt_i, cb_efb_done_in => efb_done_in_i, cb_efb_init_n_in => efb_init_n_in_i, cb_efb_halt_out => efb_halt_i, cb_router_done_in => router_done_in_i, cb_router_init_n_in => router_init_n_in_i, cb_router_halt_out => router_halt_i, cb_rrif_done_in => rodresio_done_in_i, cb_rrif_init_n_in => rodresio_init_n_in_i, cb_rrif_halt_out => rodresio_halt_i, cb_fpga_cnfg_reg_in => fpga_cnfg_reg_i(5 downto 0), cb_clr_cnfg_reg_out => clr_cnfg_reg_i, cb_fpga_rst_reg_in => fpga_rst_reg_i(5 downto 0), cb_dsp_rst_reg_in => reset_dsp_i, --dsp_rst_reg_i, cb_clr_rst_reg_out => clr_rst_reg_i, cb_fpga_rst_status_reg_out => fpga_rst_status_reg_i, cb_dsp_rst_status_reg_out => dsp_rst_status_reg_i, cnfg_enable_out => cnfg_enable_i, cnfg_done_out => fpga_pgrm_done_out_i, cnfg_addr_out => cnfg_addr_i, cnfg_data_in => cnfg_data_i, cb_rrif_prgm_n_out => rodresio_prgm_n_out_i, cb_formA_prgm_n_out => formA_prgm_n_out_i, cb_formB_prgm_n_out => formB_prgm_n_out_i, cb_efb_prgm_n_out => efb_prgm_n_out_i, cb_router_prgm_n_out => router_prgm_n_out_i, cb_rrif_rst_n_out => rodresio_rst_n_out_i, cb_formA_rst_n_out => formA_rst_n_out_i, cb_formB_rst_n_out => formB_rst_n_out_i, cb_efb_rst_n_out => efb_rst_n_out_i, cb_router_rst_n_out => router_rst_n_out_i, fpga_sel_out => fpga_sel_i, shift_reg_en_out => shift_reg_en_i, shift_reg_load_out => shift_reg_load_en_i, fetch_cnfg_loc_out => fetch_cnfg_loc_i, cb_mdsp_rst_n_out => dsp_rst_n_out_i(4), cb_sdsp0_rst_n_out => dsp_rst_n_out_i(0), cb_sdsp1_rst_n_out => dsp_rst_n_out_i(1), cb_sdsp2_rst_n_out => dsp_rst_n_out_i(2), cb_sdsp3_rst_n_out => dsp_rst_n_out_i(3), cnfg_start_addr_out => cnfg_start_addr_i, cnfg_stop_addr_out => cnfg_stop_addr_i, cnfg_override_in => fpga_cnfg_reg_i(6) ); U3 : progman_register_block port map ( clk_in => vme_clk_g, rst_n_in => rst_n_i, prb_bus_strb_in => data_strb_i, prb_bus_ce_in => prm_cen_i, prb_bus_rnw_in => vme_rnw_p, prb_bus_addr_in => vme_addr_i, prb_bus_data_in => vme_data_in_p, prb_bus_data_out => vme_prm_out_i, prb_rrif_done_in => rodresio_done_in_i, prb_rrif_init_n_in => rodresio_init_n_in_i, prb_rrif_halt_in => rodresio_halt_i, prb_formA_done_in => formA_done_in_i, prb_formA_init_n_in => formA_init_n_in_i, prb_formA_halt_in => formA_halt_i, prb_formB_done_in => formB_done_in_i, prb_formB_init_n_in => formB_init_n_in_i, prb_formB_halt_in => formB_halt_i, prb_efb_done_in => efb_done_in_i, prb_efb_init_n_in => efb_init_n_in_i, prb_efb_halt_in => efb_halt_i, prb_router_done_in => router_done_in_i, prb_router_init_n_in => router_init_n_in_i, prb_router_halt_in => router_halt_i, prb_fpga_rst_status_reg_in => fpga_rst_status_reg_i, prb_dsp_rst_status_reg_in => dsp_rst_status_reg_i, fpga_cnfg_reg_out => fpga_cnfg_reg_i, fpga_rst_reg_out => fpga_rst_reg_i, dsp_rst_reg_out => dsp_rst_reg_i, flash_cmd_reg_out => flash_cmd_reg_i, flash_status_reg_in => flash_status_reg_i, flash_addr_reg_out => flash_addr_i, flash_data_reg_in => flash_data_in_i, flash_data_reg_out => flash_data_out_i, clr_cnfg_reg_in => clr_cnfg_reg_i, clr_rst_reg_in => clr_rst_reg_i, prb_cnfg_en_in => cnfg_enable_i, cnfg_start_reg_in => cnfg_start_addr_i, cnfg_stop_reg_in => cnfg_stop_addr_i, serial_number_in => serial_number_i, rod_busy_in => rod_busy_i, rod_clk_status_in => clk40_locked_i, vme_clk_status_in => vme_clk_locked_i, rod_clk_select_in => rod_clk_sel_p ); U4 : flash_decoder_block port map ( clk_in => vme_clk_g, cclk_in => cclk_g, rst_n_in => rst_n_i, fdb_addr_in => flash_addr_i, fdb_data_in => flash_data_out_i, fdb_data_out => flash_data_in_i, fdb_cr_in => flash_cmd_reg_i, fdb_sr_out => flash_status_reg_i, cnfg_enable_in => cnfg_enable_i, cnfg_addr_in => cnfg_addr_i, cnfg_data_out => cnfg_data_i, memory_addr_out => flash_mem_addr_out_i, memory_data_in => flash_mem_data_in_i, memory_data_out => flash_mem_data_out_i, write_en_n_out => WE_n_out_i, output_en_n_out => OE_n_out_i, CE0_n_out => CE0_n_out_i, CE1_n_out => CE1_n_out_i, CE2_n_out => CE2_n_out_i, shift_reg_load_in => shift_reg_load_en_i, fetch_cnfg_loc_in => fetch_cnfg_loc_i ); U5 : shift_register port map ( clk_in => cclk_g, rst_n_in => rst_n_i, en_load_in => shift_reg0_load_i, en_shift_in => shift_reg_en_i(0), data_in => cnfg_data_i, data_out => sr_cnfg_data0_i ); U6 : shift_register port map ( clk_in => cclk_g, rst_n_in => rst_n_i, en_load_in => shift_reg1_load_i, en_shift_in => shift_reg_en_i(1), data_in => cnfg_data_i, data_out => sr_cnfg_data1_i ); U7 : hpi_data_controller port map ( clk_in => vme_clk_g, rst_n_in => rst_n_i, svic_region_in => svic_region_i, mdsp_cen_in => mdsp_cen_i, mdsp_ds_in => data_strb_i, mdsp_hrdy_n_in => mdsp_hrdy_n_i, mdsp_hpi_data_in => mdsp_hpi_data_in_i, mdsp_hpi_data_out => mdsp_hpi_data_out_i, mdsp_cen_n_out => mdsp_cen_n_i, mdsp_rnw_out => mdsp_rnw_i, mdsp_hhwil_out => mdsp_hhwil_i, mdsp_hds1_n_out => mdsp_hds1_n_i, vme_bus_rnw_in => vme_rnw_i, mdsp_vme_data_in => vme_data_in_p, mdsp_vme_data_out => vme_hpi_do_i, vme_dtack_n_out => vme_dtack_n_i, lvme_cen_in => vme_ce_i ); U8 : vme_address_decoder port map ( clk_in => vme_clk_g, rst_n_in => rst_n_i, rod_addr_n_in => board_addr_n_i, lvme_addr_in => vme_addr_i(31 downto 20), lvme_be_n_in => vme_be_n_p, lvme_cs_n_in => vme_ce_n_i, prm_cen_out => prm_cen_i, mdsp_cen_out => mdsp_cen_i, data_strb_out => data_strb_i, svic_region_out => svic_region_i ); U9 : reset_command_controller port map ( clk40_in => clk40_g, clk05_in => clk05_g, rst_n_in => rst_n_i, clr_reset_cmd_in => clr_rst_reg_i, rod_busy_in => rod_busy_i, reset_commands_in => reset_cmds_in_i, reset_commands_out => reset_cmds_out_i, reset_sdsp_out => dsp_reset_cmd_i ); ------------------------------------------------------------------------------- -- I/O Buffer / Clock DLL Instantiation ------------------------------------------------------------------------------- -- 40MHz Clock Circuit clk40_ibufg : IBUFG port map (I => clk40_in, O => dll_clk40_in); main_clk_dll : CLKDLL port map ( CLK0 => dll_clk40_out, CLK90 => open, CLK180 => open, CLK270 => open, CLK2X => open, CLKDV => dll_clk05_out, LOCKED => clk40_locked_i, CLKIN => dll_clk40_in, CLKFB => clk40_g, RST => gnd ); clk40_bufg : BUFG port map (I => dll_clk40_out, O => clk40_g); clk05_bufg : BUFG port map (I => dll_clk05_out, O => clk05_g); -- 60MHz Clock Circuit vme_clk_ibufg : IBUFG port map (I => vme_clk_in, O => vme_clk_ibufg_o); vme_clk_dll : CLKDLL port map ( CLK0 => dll_vme_clk_out, CLK90 => open, CLK180 => open, CLK270 => open, CLK2X => open, CLKDV => dll_cclk_out, LOCKED => vme_clk_locked_i, CLKIN => vme_clk_ibufg_o, CLKFB => vme_clk_g, RST => gnd ); vme_clk_bufg : BUFG port map (I => dll_vme_clk_out, O => vme_clk_g); cclk_bufg : BUFG port map (I => dll_cclk_out, O => cclk_g); reset_ibuf : IBUF port map (I => rst_n_in, O => rst_n_i); ------------------------------------------------------------------------------- -- FLASH Memory I/O memory_address_out_block : for i in 0 to 18 generate memory_address_out_obufs : OBUF port map ( I => flash_mem_addr_out_i(i), O => memory_address_out(i) ); end generate; memory_data_inout_block : for i in 0 to 7 generate memory_data_inout_iobufs : IOBUF port map ( I => flash_mem_data_out_i(i), O => flash_mem_data_in_i(i), IO => memory_data(i), T => memory_data_dir_en_i ); end generate; WE0_n_out_obuf : OBUF port map (I => WE_n_out_i, O => WE0_n_out); WE1_n_out_obuf : OBUF port map (I => WE_n_out_i, O => WE1_n_out); WE2_n_out_obuf : OBUF port map (I => WE_n_out_i, O => WE2_n_out); OE0_n_out_obuf : OBUF port map (I => OE_n_out_i, O => OE0_n_out); OE1_n_out_obuf : OBUF port map (I => OE_n_out_i, O => OE1_n_out); OE2_n_out_obuf : OBUF port map (I => OE_n_out_i, O => OE2_n_out); CE0_n_out_obuf : OBUF port map (I => CE0_n_out_i, O => CE0_n_out); CE1_n_out_obuf : OBUF port map (I => CE1_n_out_i, O => CE1_n_out); CE2_n_out_obuf : OBUF port map (I => CE2_n_out_i, O => CE2_n_out); ------------------------------------------------------------------------------- -- DSP I/O And Reset commands mdsp_hpi_data_inout_block : for i in 0 to 15 generate mdsp_hpi_data_iobufs : IOBUF port map ( I => mdsp_hpi_data_out_i(i), O => mdsp_hpi_data_in_i(i), IO => mdsp_hd(i), T => mdsp_hpi_data_dir_i ); end generate; mdsp_hrdy_n_ibuf : IBUF port map (I => mdsp_hrdy_n_in, O => mdsp_hrdy_n_i); mdsp_cen_n_obuf : OBUF port map (I => mdsp_cen_n_i, O => mdsp_hcs_n_out); mdsp_rnw_obuf : OBUF port map (I => mdsp_rnw_i, O => mdsp_hrnw_out); mdsp_hds1_n_obuf : OBUF port map (I => mdsp_hds1_n_i, O => mdsp_hds1_n_out); mdsp_hhwil_obuf : OBUF port map (I => mdsp_hhwil_i, O => mdsp_hhwil_out); mdsp_hcntl0_obuf : OBUF port map (I => mdsp_hcntl0_i, O => mdsp_hcntl0_out); mdsp_hcntl1_obuf : OBUF port map (I => mdsp_hcntl1_i, O => mdsp_hcntl1_out); reset_cmds_out_block : for i in 0 to 1 generate reset_cmds_out_obufs : OBUF port map (I => reset_cmds_out_i(i), O => reset_cmds_out(i)); end generate; reset_cmds_in_block : for i in 0 to 1 generate reset_cmds_in_obufs : IBUF port map (I => reset_cmds_in(i), O => reset_cmds_in_i(i)); end generate; ------------------------------------------------------------------------------- -- FPGA configuration and reset bits rodresio_prgbits_out_obuf : OBUF port map (I => rodresio_prgbits_out_i, O => rodresio_prgbits_out); rodresio_cclk_out_obuf : OBUF port map (I => rodresio_cclk_out_i, O => rodresio_cclk_out); rodresio_prgm_n_out_obuf : OBUFT port map (I => gnd, O => rodresio_prgm_n_out, T => rodresio_prgm_n_out_i); rodresio_prgm_n_out_pullup : PULLUP port map (O => rodresio_prgm_n_out); rodresio_done_in_ibuf : IBUF port map (I => rodresio_done_in, O => rodresio_done_in_i); rodresio_init_n_in_ibuf : IBUF port map (I => rodresio_init_n_in, O => rodresio_init_n_in_i); rodresio_rst_n_out_obuf : OBUF port map (I => rodresio_rst_n_out_p, O => rodresio_rst_n_out); router_prgbits_out_obuf : OBUF port map (I => router_prgbits_out_i, O => router_prgbits_out); router_cclk_out_obuf : OBUF port map (I => router_cclk_out_i, O => router_cclk_out); router_prgm_n_out_obuf : OBUFT port map (I => gnd, O => router_prgm_n_out, T => router_prgm_n_out_i); router_prgm_n_out_pullup : PULLUP port map (O => router_prgm_n_out); router_done_in_ibuf : IBUF port map (I => router_done_in, O => router_done_in_i); router_init_n_in_ibuf : IBUF port map (I => router_init_n_in, O => router_init_n_in_i); router_rst_n_out_obuf : OBUF port map (I => router_rst_n_out_p, O => router_rst_n_out); efb_prgbits_out_obuf : OBUF port map (I => efb_prgbits_out_i, O => efb_prgbits_out); efb_cclk_out_obuf : OBUF port map (I => efb_cclk_out_i, O => efb_cclk_out); efb_prgm_n_out_obuf : OBUFT port map (I => gnd, O => efb_prgm_n_out, T => efb_prgm_n_out_i); efb_prgm_n_out_pullup : PULLUP port map (O => efb_prgm_n_out); efb_done_in_ibuf : IBUF port map (I => efb_done_in, O => efb_done_in_i); efb_init_n_in_ibuf : IBUF port map (I => efb_init_n_in, O => efb_init_n_in_i); efb_rst_n_out_obuf : OBUF port map (I => efb_rst_n_out_p, O => efb_rst_n_out); formA_prgbits_out_obuf : OBUF port map (I => formA_prgbits_out_i, O => formA_prgbits_out); formA_cclk_out_obuf : OBUF port map (I => formA_cclk_out_i, O => formA_cclk_out); formA_prgm_n_out_obuf : OBUFT port map (I => gnd, O => formA_prgm_n_out, T => formA_prgm_n_out_i); formA_prgm_n_out_pullup : PULLUP port map (O => formA_prgm_n_out); formA_done_in_ibuf : IBUF port map (I => formA_done_in, O => formA_done_in_i); formA_init_n_in_ibuf : IBUF port map (I => formA_init_n_in, O => formA_init_n_in_i); formA_rst_n_out_obuf : OBUF port map (I => formA_rst_n_out_p, O => formA_rst_n_out); formB_prgbits_out_obuf : OBUF port map (I => formB_prgbits_out_i, O => formB_prgbits_out); formB_cclk_out_obuf : OBUF port map (I => formB_cclk_out_i, O => formB_cclk_out); formB_prgm_n_out_obuf : OBUFT port map (I => gnd, O => formB_prgm_n_out, T => formB_prgm_n_out_i); formB_prgm_n_out_pullup : PULLUP port map (O => formB_prgm_n_out); formB_done_in_ibuf : IBUF port map (I => formB_done_in, O => formB_done_in_i); formB_init_n_in_ibuf : IBUF port map (I => formB_init_n_in, O => formB_init_n_in_i); formB_rst_n_out_obuf : OBUF port map (I => formB_rst_n_out_p, O => formB_rst_n_out); dsp_rst_n_out_block : for i in 0 to 4 generate dsp_rst_n_out_obufts : OBUFT port map ( I => gnd, O => dsp_rst_n_out(i), T => dsp_rst_n_out_i(i) ); dsp_rst_n_out_pullups : PULLUP port map (O => dsp_rst_n_out(i)); end generate; fpga_pgrm_done_out_obuf : OBUF port map (I => rod_busy_n_i, O => fpga_pgrm_done_out); ------------------------------------------------------------------------------- -- ROD Status rod_busy_ibuf : IBUF port map (I => rod_busy_in, O => rod_busy_p); rod_busy_n_obuf : OBUF port map (I => rod_busy_n_i, O => rod_busy_n_out); ------------------------------------------------------------------------------- -- Serial Number Inputs serial_number_in_block : for i in 0 to 9 generate serial_number_n_p(i) <= serial_number_n_in(i); serial_number_pullups : PULLUP port map (O => serial_number_n_p(i)); serial_number_ibufs : IBUF port map (I => serial_number_n_p(i), O => serial_number_n_i(i)); serial_number_i(i) <= NOT serial_number_n_i(i); end generate; ------------------------------------------------------------------------------- -- Test Output I/O test0_obuf : OBUF -- port map (I => vme_addr_i(1), O => test_out(0)); test1_obuf : OBUF -- port map (I => mdsp_hhwil_i, O => test_out(1)); test2_obuf : OBUF -- port map (I => mdsp_hrdy_n_i, O => test_out(2)); test3_obuf : OBUF -- port map (I => mdsp_cen_i, O => test_out(3)); test4_obuf : OBUF -- port map (I => prm_cen_i, O => test_out(4)); test5_obuf : OBUF -- port map (I => vme_rnw_i, O => test_out(5)); test6_obuf : OBUF -- port map (I => vme_trans_en_n_i, O => test_out(6)); test7_obuf : OBUF -- port map (I => vme_dtack_n_i, O => test_out(7)); spare_pin_block : for i in 0 to 5 generate spare_pin_obufts : OBUF port map (I => vme_ce_n_i(i), O => spare_pin(i)); end generate; spare_pin6_obuf : OBUF port map (I => clk40_g, O => spare_pin(6)); spare_pin7_obuf : OBUF port map (I => vme_lden_n_p, O => spare_pin(7)); vme_lden_n_ibuf : IBUF port map (I => vme_lden_n_in, O => vme_lden_n_p); rod_clock_select_ibuf : IBUF port map (I => rod_clock_select_in, O => rod_clk_sel_p); ------------------------------------------------------------------------------- -- VMEBus I/O vme_data_inout_block : for i in 0 to 31 generate vme_data_inout_iobufs : IOBUF port map ( I => vme_data_out_p(i), O => vme_data_in_p(i), IO => vme_data_inout(i), T => vme_data_dir_i ); end generate; vme_addr_in_block : for i in 0 to 31 generate vme_addr_in_ibufs : IBUF port map (I => vme_addr_in(i), O => vme_addr_i(i)); end generate; vme_rnw_ibuf : IBUF port map (I => vme_rnw_in, O => vme_rnw_p); vme_ce_in_block : for i in 0 to 5 generate vme_ce_in_ibufs : IBUF port map (I => vme_ce_n_in(i), O => vme_ce_n_i(i)); end generate; vme_be_in_block : for i in 0 to 3 generate vme_be_in_ibufs : IBUF port map (I => vme_be_n_in(i), O => vme_be_n_p(i)); end generate; vme_translator_en_n_obuf : OBUF port map (I => vme_trans_en_n_i, O => vme_translator_en_n_out); vme_dtack_n_obuf : OBUF port map (I => vme_dtack_n_i, O => vme_dtack_n_out); svic_region_out_block : for i in 0 to 2 generate svic_region_obufs : OBUF port map (I => svic_region_i(i), O => svic_region_out(i)); end generate; board_addr_n_in_block : for i in 0 to 4 generate board_addr_n_in_ibufs : IBUF port map (I => board_addr_n_in(i), O => board_addr_n_i(i)); end generate; ------------------------------------------------------------------------------- -- PROCESS DECLARATION ------------------------------------------------------------------------------- sr_cnfg_data_mux : process ( cclk_g, rst_n_i, shift_reg_en_i, shift_reg_en_d1, sr_cnfg_data0_i, sr_cnfg_data1_i ) begin if (rst_n_i = '0') then sr_cnfg_data_i <= '0'; elsif (cclk_g'event and cclk_g = '1') then shift_reg_en_d1 <= shift_reg_en_i; if (shift_reg_en_d1 = "01") then sr_cnfg_data_i <= sr_cnfg_data0_i; elsif (shift_reg_en_d1 = "10") then sr_cnfg_data_i <= sr_cnfg_data1_i; else sr_cnfg_data_i <= '0'; end if; end if; end process sr_cnfg_data_mux; ------------------------------------------------------------------------------- fpga_pgrm_mux : process ( vme_clk_g, cclk_g, rst_n_i, fpga_sel_i, sr_cnfg_data_i ) begin if (rst_n_i = '0') then efb_prgbits_out_i <= '0'; efb_cclk_out_i <= '0'; formA_prgbits_out_i <= '0'; formA_cclk_out_i <= '0'; formB_prgbits_out_i <= '0'; formB_cclk_out_i <= '0'; rodresio_prgbits_out_i <= '0'; rodresio_cclk_out_i <= '0'; router_prgbits_out_i <= '0'; router_cclk_out_i <= '0'; elsif (vme_clk_g'event and vme_clk_g = '1') then case fpga_sel_i is when "000" => -- select rrif efb_prgbits_out_i <= '0'; efb_cclk_out_i <= '0'; formA_prgbits_out_i <= '0'; formA_cclk_out_i <= '0'; formB_prgbits_out_i <= '0'; formB_cclk_out_i <= '0'; rodresio_prgbits_out_i <= sr_cnfg_data_i; rodresio_cclk_out_i <= NOT cclk_g; router_prgbits_out_i <= '0'; router_cclk_out_i <= '0'; when "001" => -- select both formatter banks efb_prgbits_out_i <= '0'; efb_cclk_out_i <= '0'; formA_prgbits_out_i <= sr_cnfg_data_i; formA_cclk_out_i <= NOT cclk_g; formB_prgbits_out_i <= sr_cnfg_data_i; formB_cclk_out_i <= NOT cclk_g; rodresio_prgbits_out_i <= '0'; rodresio_cclk_out_i <= '0'; router_prgbits_out_i <= '0'; router_cclk_out_i <= '0'; when "010" => -- select formatter A bank efb_prgbits_out_i <= '0'; efb_cclk_out_i <= '0'; formA_prgbits_out_i <= sr_cnfg_data_i; formA_cclk_out_i <= NOT cclk_g; formB_prgbits_out_i <= '0'; formB_cclk_out_i <= '0'; rodresio_prgbits_out_i <= '0'; rodresio_cclk_out_i <= '0'; router_prgbits_out_i <= '0'; router_cclk_out_i <= '0'; when "011" => -- select formatter B bank efb_prgbits_out_i <= '0'; efb_cclk_out_i <= '0'; formA_prgbits_out_i <= '0'; formA_cclk_out_i <= '0'; formB_prgbits_out_i <= sr_cnfg_data_i; formB_cclk_out_i <= NOT cclk_g; rodresio_prgbits_out_i <= '0'; rodresio_cclk_out_i <= '0'; router_prgbits_out_i <= '0'; router_cclk_out_i <= '0'; when "100" => -- select efb efb_prgbits_out_i <= sr_cnfg_data_i; efb_cclk_out_i <= NOT cclk_g; formA_prgbits_out_i <= '0'; formA_cclk_out_i <= '0'; formB_prgbits_out_i <= '0'; formB_cclk_out_i <= '0'; rodresio_prgbits_out_i <= '0'; rodresio_cclk_out_i <= '0'; router_prgbits_out_i <= '0'; router_cclk_out_i <= '0'; when "101" => -- select router efb_prgbits_out_i <= '0'; efb_cclk_out_i <= '0'; formA_prgbits_out_i <= '0'; formA_cclk_out_i <= '0'; formB_prgbits_out_i <= '0'; formB_cclk_out_i <= '0'; rodresio_prgbits_out_i <= '0'; rodresio_cclk_out_i <= '0'; router_prgbits_out_i <= sr_cnfg_data_i; router_cclk_out_i <= NOT cclk_g; when others => efb_prgbits_out_i <= '0'; efb_cclk_out_i <= '0'; formA_prgbits_out_i <= '0'; formA_cclk_out_i <= '0'; formB_prgbits_out_i <= '0'; formB_cclk_out_i <= '0'; rodresio_prgbits_out_i <= '0'; rodresio_cclk_out_i <= '0'; router_prgbits_out_i <= '0'; router_cclk_out_i <= '0'; end case; end if; end process fpga_pgrm_mux; ------------------------------------------------------------------------------- rod_busy : process ( clk40_g, rst_n_i ) begin if (rst_n_i = '0') then rod_busy_i <= '1'; rod_busy_n_i <= '0'; elsif (clk40_g'event AND clk40_g = '1') then rod_busy_i <= NOT fpga_pgrm_done_out_i OR NOT rod_busy_p; rod_busy_n_i <= NOT rod_busy_i; end if; end process rod_busy; ------------------------------------------------------------------------------- vme_data_out_mux : process ( vme_clk_g, rst_n_i ) begin if (rst_n_i = '0') then vme_data_out_p <= (others => '0'); elsif (vme_clk_g'event AND vme_clk_g = '1') then if (prm_cen_i = '1') then vme_data_out_p <= vme_prm_out_i; elsif (mdsp_cen_i = '1') then vme_data_out_p <= vme_hpi_do_i; else vme_data_out_p <= (others => '0'); end if; end if; end process vme_data_out_mux; vme_data_output_en : process ( vme_clk_g, rst_n_i ) begin if (rst_n_i = '0') then vme_trans_en_n_i <= '1'; vme_data_dir_i <= '1'; vme_be_n_i <= (others => '1'); elsif (vme_clk_g'event AND vme_clk_g = '1') then vme_be_n_i <= vme_be_n_p; -- vme_trans_en_n_i <= vme_be_n_i(3) AND vme_be_n_i(2) AND vme_be_n_i(1) AND vme_be_n_i(0); if (vme_be_n_p = "1111" AND vme_be_n_i = "1111") then vme_trans_en_n_i <= '1'; else vme_trans_en_n_i <= '0'; end if; if ((prm_cen_i = '1' OR mdsp_cen_i = '1') AND vme_rnw_i = '1') then vme_data_dir_i <= '0'; -- output to VME else vme_data_dir_i <= '1'; -- input from VME end if; end if; end process vme_data_output_en; hpi_data_output_en : process ( vme_clk_g, rst_n_i ) begin if (rst_n_i = '0') then mdsp_hpi_data_dir_i <= '1'; elsif (vme_clk_g'event AND vme_clk_g = '1') then if (mdsp_cen_i = '1' AND vme_rnw_i = '0') then mdsp_hpi_data_dir_i <= '0'; -- output to MDSP else mdsp_hpi_data_dir_i <= '1'; -- input from MDSP end if; end if; end process hpi_data_output_en; vme_to_mdsp_register : process ( vme_clk_g, rst_n_i ) begin if (rst_n_i = '0') then mdsp_hcntl1_i <= '0'; mdsp_hcntl0_i <= '0'; elsif (vme_clk_g'event AND vme_clk_g = '1') then mdsp_hcntl1_i <= NOT vme_addr_i(23) AND vme_addr_i(22); mdsp_hcntl0_i <= NOT vme_addr_i(23) AND vme_addr_i(21); end if; end process vme_to_mdsp_register; vme_signal_register : process ( vme_clk_g, rst_n_i ) begin if (rst_n_i = '0') then vme_rnw_i <= '0'; vme_ce_i <= (others => '0'); elsif (vme_clk_g'event AND vme_clk_g = '1') then vme_rnw_i <= vme_rnw_p; vme_ce_i <= NOT vme_ce_n_i; end if; end process vme_signal_register; ------------------------------------------------------------------------------- end rtl;