C51 COMPILER V8.09 FX2SLAVEFIFOMODE 12/28/2007 10:51:03 PAGE 1 C51 COMPILER V8.09, COMPILATION OF MODULE FX2SLAVEFIFOMODE OBJECT MODULE PLACED IN .\Debug\FX2SlaveFIFOMode.obj COMPILER INVOKED BY: C:\Program Files\Keil\C51\BIN\C51.EXE FX2SlaveFIFOMode.c ROM(COMPACT) OPTIMIZE(6,SPEED) DEBUG OBJEC -TEXTEND OBJECT(.\Debug\FX2SlaveFIFOMode.obj) line level source 1 //----------------------------------------------------------------------------- 2 // Copyright 2007, Piero Giubilato, Lawrence Berkely National Laboratory 3 //----------------------------------------------------------------------------- 4 5 //______________________________________________________________________________ 6 // {Trace} 7 // [File name] "FX2SlaveFIFOMode.c" 8 // [Language] "C Standard" 9 // [Last revision] "06 Dec 2007" 10 // [Author] "Piero Giubilato" 11 // [Member of] "FX2 Firmware" 12 // [Description] "This file is the program that has to be loaded into the 8051" 13 // "microprocessor embedded into the Cypress FX2LP chip, in order to get it" 14 // "interfacing correctly with the FPGA firmware and the PARROT framework." 15 // [Compiler] "Keil uVision 3.53" 16 // [Key documentation] "Cypress EZ-USB Technical Reference Manual" 17 // {Trace} 18 //______________________________________________________________________________ 19 20 //______________________________________________________________________________ 21 // {Description} 22 // 23 // 24 // 25 // 26 // 27 // 28 // {Description} 29 //______________________________________________________________________________ 30 31 32 33 // Using this setting for the TD_Init function will result into putting the 34 // Cypress device into a FIFO Slave mode, actually putting out of the game the 35 // integrated A851 microcrontroller. The FPGA is instead used as a master, while 36 // the Cypress chips acts like a with FIFO USB 37 38 39 // FX2LP inclusions (necessary just to avoid excessive 0x style programming) 40 #include "fx2.h" // macros, datatypes, globals & function prototypes 41 #include "fx2regs.h" // FX2 registers & reference masks definition 42 #include "syncdly.h" // Cypress macro used to addres some FX2 issues 43 44 45 //______________________________________________________________________________ 46 void SlaveFIFOMode (void) 47 { 48 1 // Pay attention: the register initialization procedure MUST follow the 49 1 // present order. Do NOT rearrange it! 50 1 51 1 // ** Step 1: set the device IFCONFIG register to define the behaviour of 52 1 // the interface between the slave FIFOs and the external master, and 53 1 // set the SLAVE mode also. 54 1 C51 COMPILER V8.09 FX2SLAVEFIFOMODE 12/28/2007 10:51:03 PAGE 2 55 1 // Interface configuration register description: 56 1 // Bit 7: IFCLKSRC (0 = external on IFGCLK pin, 1 = internal) 57 1 // Bit 6: 3048MHZ (0 = 30 MHz, 1 = 48 MHz) 58 1 // Bit 5: IFCLKOE (0 = disabled (tri-state), 1 = put IFCLK on IFCLK pin) 59 1 // Bit 4: IFCLKPOL (0 = normal, 1 = inverted) 60 1 // Bit 3: ASYNC (0 = synchronous mode, 1 = asynchronous mode) 61 1 // Bit 2: GSTATE (0 = disabled, 1 = drive GPIF state on PORTE[0:2]) 62 1 // Bit 1: IFCFG1 (00 = PORTS, 01 = reserved, 10 = GPIF, 11 = SLAVE) 63 1 // Bit 0: IFCFG0 64 1 65 1 IFCONFIG = 0x43; // Ext Clk, 48MHz, No OE, No Inv, SYNCH, No GPIF, SLAVE 66 1 //IFCONFIG = 0xE3; // Int Clk, 48MHz, OE, No Inv, SYNCH, No GPIF, SLAVE 67 1 //IFCONFIG = 0xA3; // Int Clk, 32MHz, OE, No Inv, SYNCH, No GPIF, SLAVE 68 1 SYNCDELAY; 69 1 70 1 // ** Step 2: set the SLCS pin to allow enabling/disbling the chip 71 1 // by an external command 72 1 PORTACFG = 0x40; // Set pin # 74 as a SLCS input (active low) 73 1 SYNCDELAY; 74 1 75 1 // ** Step 3: set up the correct connection for the FIFO's flags, fixed mode. 76 1 // Bits [7:4] FlagB / Flag D 77 1 // Bits [3:0] FlagA / Flag C 78 1 // 79 1 // FLAGx[3:0] () 80 1 // 1000 EP2 Empty {0x8} 81 1 // 1110 EP6 Full {0xE} 82 1 // 1100 EP2 Full {0xC} 83 1 // 1010 EP6 Empty {0xA} 84 1 PINFLAGSAB = 0x8E; // EP6 Full -> FlagA, EP2 Empty -> FlagB 85 1 SYNCDELAY; 86 1 87 1 //PINFLAGSAB = 0xE8; SYNCDELAY; // EP6 Full -> FlagB, EP2 Empty -> FlagA 88 1 PINFLAGSCD = 0xDC; SYNCDELAY; // EP2 Full -> FlagC, EP6 Empty -> FlagD 89 1 90 1 // ** Step 4: Set FIFO's flags pins asserted level (0 = active low, 1 = active high) 91 1 // Bit 7: 0 92 1 // Bit 6: 0 93 1 // Bit 5: PKTEND 94 1 // Bit 4: SLOE 95 1 // Bit 3: SLRD 96 1 // Bit 2: SLWR 97 1 // Bit 1: EF 98 1 // Bit 0: FF 99 1 FIFOPINPOLAR = 0x00; // Set Empty and Full flag with active high pin! 100 1 SYNCDELAY; 101 1 102 1 // ** Step 5: set the auto-arming of endpoints when switching from Auto to 103 1 // Manual mode. 104 1 REVCTL = 0x03; 105 1 SYNCDELAY; 106 1 107 1 // ** Step 6: configure the Endpoints. 108 1 // Endpoint configuration register description: 109 1 // Bit 7: Active (0 = disable, 1 = active) 110 1 // Bit 6: Direction (0 = OUT, 1 = IN) 111 1 // Bit 5: Type1 (00 = illegal, 01 = ISO, 10 = BULK, 11 = INT) 112 1 // Bit 4: Type0 113 1 // Bit 3: Size (0 = 512 bytes, 1 = 1024 bytes) 114 1 // Bit 2: Not used 115 1 // Bit 1: Buf1 (00 = quad, 01 = illegal, 10 = double, 11 = triple) 116 1 // Bit 0: Buf0 C51 COMPILER V8.09 FX2SLAVEFIFOMODE 12/28/2007 10:51:03 PAGE 3 117 1 118 1 119 1 // Pay attention: endpoints MUST be set starting from the active once 120 1 // in order to avoid the chip messing up the buffer assignement! 121 1 //EP2CFG = 0xA0; SYNCDELAY; // ON, OUT, BULK, 512, Buffer 4X 122 1 EP2CFG = 0xA2; SYNCDELAY; // ON, OUT, BULK, 512, Buffer 2X 123 1 EP6CFG = 0xE0; SYNCDELAY; // ON, IN, BULK, 512, Buffer 4X 124 1 //EP6CFG = 0xE2; SYNCDELAY; // ON, IN, BULK, 512, Buffer 2X 125 1 126 1 EP4CFG = 0x20; SYNCDELAY; // OFF, OUT, BULK, 512, Buffer 2X 127 1 EP8CFG = 0x20; SYNCDELAY; // OFF, OUT, BULK, 512, Buffer 2X 128 1 129 1 // ** Step 7: reset the FIFOs 130 1 FIFORESET = 0x80; SYNCDELAY; // Send a NAK to all Host transfers 131 1 FIFORESET = 0x02; SYNCDELAY; // Reset Endpoint 2 FIFO 132 1 FIFORESET = 0x08; SYNCDELAY; // Reset Endpoint 6 FIFO 133 1 FIFORESET = 0x00; SYNCDELAY; // Restore normal operation 134 1 135 1 // ** Step 8: arm both Endpoint 2 buffers to "prime the pump" 136 1 OUTPKTEND = 0x82; SYNCDELAY; 137 1 OUTPKTEND = 0x82; SYNCDELAY; 138 1 139 1 // ** Step 9: put both Endpoints in AUTO mode, so actually taking 140 1 // away the CPU from managing the packets transfer. Set also the 141 1 // packet width to 16 bits (one WORD wide). 142 1 143 1 // Endpoint fifo register description: 144 1 // Bit 7: Not used 145 1 // Bit 6: INFM1 (0 = NORMAL, 1 = FLAG active 1 byte early) 146 1 // Bit 5: OEP1 (0 = NORMAL, 1 = FLAG active 1 byte early) 147 1 // Bit 4: AUTOOUT (0 = FALSE, 1 = TRUE) 148 1 // Bit 3: AUTOIN (0 = FALSE, 1 = TRUE) 149 1 // Bit 2: ZEROLENIN (0 = disable, 1 = send 0 length pkt on PKTEND) 150 1 // Bit 1: Not used 151 1 // Bit 0: WORDWIDE (0 = byte wide, 1 = word wide) 152 1 EP2FIFOCFG = 0x11; SYNCDELAY; // AUTOOUT, ZEROLEN = 0, WORDWIDE = 1 153 1 EP6FIFOCFG = 0x0D; SYNCDELAY; // AUTOIN, ZEROLEN = 1, WORDWIDE = 1 154 1 155 1 // ** Step 10: set packet autocommissioning size for the IN endpoint 156 1 EP6AUTOINLENH = 0x02; SYNCDELAY; // Auto-commit 512-bytes packets 157 1 EP6AUTOINLENL = 0x00; SYNCDELAY; // Minimal packet is 0 bytes 158 1 } 159 160 MODULE INFORMATION: STATIC OVERLAYABLE CODE SIZE = 162 ---- CONSTANT SIZE = ---- ---- XDATA SIZE = ---- ---- PDATA SIZE = ---- ---- DATA SIZE = ---- ---- IDATA SIZE = ---- ---- BIT SIZE = ---- ---- END OF MODULE INFORMATION. C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)