--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   16:12:30 09/27/2007
-- Design Name:   daq
-- Module Name:   C:/ICES/Ecostrip/daq_tb0.vhd
-- Project Name:  Sim
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: daq
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY daq_tb0_vhd IS
END daq_tb0_vhd;

ARCHITECTURE behavior OF daq_tb0_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT daq
	PORT(
		clk_in : IN std_logic;
		i_address : IN std_logic_vector(10 downto 0);
		reset : IN std_logic;
		i_read : IN std_logic;
		i_enable : IN std_logic;
		i_ack1 : IN std_logic;
		i_rxdata : IN std_logic;    
		data : INOUT std_logic_vector(15 downto 0);      
		dbd : OUT std_logic_vector(15 downto 0);
		dba : OUT std_logic_vector(10 downto 0);
		md : OUT std_logic_vector(31 downto 0);
		req1 : OUT std_logic;
		stoptrig1 : OUT std_logic;
		LED : OUT std_logic_vector(4 downto 0);
		txclk : OUT std_logic;
		txdata : OUT std_logic
		);
	END COMPONENT;

	--Inputs
	SIGNAL clk_in :  std_logic := '0';
	SIGNAL reset :  std_logic := '1';
	SIGNAL i_read :  std_logic := '0';
	SIGNAL i_enable :  std_logic := '0';
	SIGNAL i_ack1 :  std_logic := '0';
	SIGNAL i_rxdata :  std_logic := '0';
	SIGNAL i_address :  std_logic_vector(10 downto 0) := (others=>'0');

	--BiDirs
	SIGNAL data :  std_logic_vector(15 downto 0);

	--Outputs
	SIGNAL dbd :  std_logic_vector(15 downto 0);
	SIGNAL dba :  std_logic_vector(10 downto 0);
	SIGNAL md :  std_logic_vector(31 downto 0);
	SIGNAL req1 :  std_logic;
	SIGNAL stoptrig1 :  std_logic;
	SIGNAL LED :  std_logic_vector(4 downto 0);
	SIGNAL txclk :  std_logic;
	SIGNAL txdata :  std_logic;

BEGIN

    reset <= '0'     AFTER 500 ns;
    clk_in <= NOT clk_in AFTER 25 ns;

	-- Instantiate the Unit Under Test (UUT)
	uut: daq PORT MAP(
		clk_in => clk_in,
		data => data,
		i_address => i_address,
		dbd => dbd,
		dba => dba,
		md => md,
		reset => reset,
		i_read => i_read,
		i_enable => i_enable,
		req1 => req1,
		i_ack1 => i_ack1,
		stoptrig1 => stoptrig1,
		LED => LED,
		txclk => txclk,
		txdata => txdata,
		i_rxdata => i_rxdata
	);

	tb : PROCESS
	BEGIN

		-- Wait 100 ns for global reset to finish
		wait for 1000 ns;

		-- Place stimulus here
		i_read <= '0';
		i_address <= "11000000000";
		data <= x"000F";
		i_enable <= '1';		
		wait for 100 ns;
		i_enable <= '0';		
		wait for 500 ns;
		i_ack1 <= '1';
		wait for 500 ns;
		i_ack1 <= '0';
		
		wait for 1000 ns;
		-- Place stimulus here
		i_read <= '0';
		i_address <= "11000000000";--768
		data <= x"000F";--l_data
		i_enable <= '1';		
		wait for 100 ns;
		i_enable <= '0';		
		wait for 500 ns;
		i_ack1 <= '1';
		wait for 500 ns;
		i_ack1 <= '0';
		
		wait for 1000 ns;
		-- Place stimulus here
		i_read <= '0';
		i_address <= "11000000001";--768
		data <= x"0000";--h_data
		i_enable <= '1';		
		wait for 100 ns;
		i_enable <= '0';		
		wait for 500 ns;
		i_ack1 <= '1';
		wait for 500 ns;
		i_ack1 <= '0';
		
		wait for 1000 ns;
		-- Place stimulus here
		i_read <= '0';
		i_address <= "11000000010";--769
		data <= x"0003";--l_data
		i_enable <= '1';		
		wait for 100 ns;
		i_enable <= '0';		
		wait for 500 ns;
		i_ack1 <= '1';
		wait for 500 ns;
		i_ack1 <= '0';
		
		wait for 1000 ns;
		-- Place stimulus here
		i_read <= '0';
		i_address <= "11000000011";--769
		data <= x"0000";--h_data
		i_enable <= '1';		
		wait for 100 ns;
		i_enable <= '0';		
		wait for 500 ns;
		i_ack1 <= '1';
		wait for 500 ns;
		i_ack1 <= '0';
		
		wait; -- will wait forever
	END PROCESS;

END;