//------------------------------------------------------------------------------
// DAQ application task       												            --
// (C) Devis Contarato 2009, Berkeley Lab									            --
//------------------------------------------------------------------------------

//______________________________________________________________________________
// {Trace}
// [File name] "task_DAQ_Detector.cpp"
// [Author] "Devis Contarato"
// [Version] "0.5"
// [Modified by] "Devis Contarato"
// [Last revision] "18 May 2009"
// [Language] "C++"
// [Compiler] "Visual C++ 8.x 9.x"
// [Member of] "Cool SEAL"
// [Project] "SEAL"
// [Description] "DAQ application task"
// [Key documentation]
// "Visual C++ Reference Help"
// {Trace}
//______________________________________________________________________________

// Standard components
#include <math.h>

// Application components
#include "global.h"
#include "cool.h"
#include "task_DAQ_Detector.h"

//______________________________________________________________________________
task_DAQ_Detector::task_DAQ_Detector()
{
   // Standard constructor
	dbg_Print("task_DAQ_Detector::task_DAQ_Detector: ()", DBG_LVL_ZERO);
	
	// Initialize detector description
	Init();
}

//______________________________________________________________________________
task_DAQ_Detector::~task_DAQ_Detector()
{
   // Standard destructor
	dbg_Print("task_DAQ_Detector::~task_DAQ_Detector: ()", DBG_LVL_ZERO);

	// Detectors
	for(UInt_t i=0; i < detector.size(); i++){
		delete detector[i];
	}
}


//******************************************************************************
//*																			   *
//*				  Data & Detector initialization		                       *
//*																			   *
//******************************************************************************

//______________________________________________________________________________
void task_DAQ_Detector::Init()
{
	// Set up the data
	dbg_Print("task_DAQ_Detector::Init()", DBG_LVL_FLOW);

	/////////////////////////////////
	// LDRD-2 DETECTOR DESCRIPTION //
	/////////////////////////////////
	detector.push_back( new geom_Frame() );
	detector[0]->Name("LDRD2");

	// Defines the hardware chips
		// LEFT LDRD2 sector
		detector[0]->chip(0)->Name("Left");		// LEFT side of LDRD2
		detector[0]->chip(0)->col_Count(48);	// 48 columns
		detector[0]->chip(0)->row_Count(96);	// 96 rows
		detector[0]->chip(0)->col_Pitch(20);	// Pixel column pitch
		detector[0]->chip(0)->row_Pitch(20);	// Pixel row pitch
		
		// RIGHT LDRD2 sector
		detector[0]->chip_Add(); 
		detector[0]->chip(1)->Name("Right");	// RIGHT side of LDRD2
		detector[0]->chip(1)->col_Count(48);	// 48 columns
		detector[0]->chip(1)->row_Count(96);	// 96 rows
		detector[0]->chip(1)->col_Pitch(20);	// Pixel column pitch
		detector[0]->chip(1)->row_Pitch(20);	// Pixel row pitch
	
	// Defines the logic layers

		// First logical layer (SIGNAL)
		detector[0]->layer(0)->Name("Signal");		// The signal (abstracted) layer
		detector[0]->layer(0)->dp_col_Count(96);	// Logical column count
		detector[0]->layer(0)->dp_row_Count(96);	// Logical row count
		
		// Second logical layer (REFERENCE)
		detector[0]->layer_Add();
		detector[0]->layer(1)->Name("Reference");	// The reference (abstracted) layer
		detector[0]->layer(1)->dp_col_Count(96);	// 96 columns
		detector[0]->layer(1)->dp_row_Count(96);	// 96 rows

		// Defines the chip/channel/layer connections
	
		// 1st output, left sector signal
		detector[0]->channel(0)->Name("Left signal");	// Chip/Layer connection
		detector[0]->channel(0)->chip_Idx(0);			// Data are shaped as decribed by chip #0
		detector[0]->channel(0)->layer_Idx(0);			// Data are directed to layer #0

		// 2nd output, left sector reference
		detector[0]->channel_Add(0, 1);					// Chip #0 to layer #1
		detector[0]->channel(1)->Name("Left reference");

		// 3rd output, right sector signal
		detector[0]->channel_Add(1, 0);					// Chip #1 to layer #0
		detector[0]->channel(2)->Name("Right signal");

		// 4th output, right sector reference
		detector[0]->channel_Add(1, 1);					// Chip #1 to layer #1
		detector[0]->channel(3)->Name("Right reference");

	// Sets the chip geometry
	// Here we set the chip mapping respect to layer mapping. Basically, the 
	// number of pixels contained into one chip is considered as a linear vector,
	// where for each pixel is stored the location where to place it into the 
	// logical target layer defined by the channel association.

		// Chip #0 is on the left side of the logical frame, chip #1 (Right)
		// on the right side but mirrored, i.e. the first data to exit is the
		// last in the row.
		geom_Chip* ldrd2_Left = detector[0]->chip(0);
		geom_Chip* ldrd2_Right = detector[0]->chip(1);
		UInt_t l_Col = 0, r_Col = 0, lr_Row = 0;
		for (UInt_t i = 0; i < ldrd2_Left->dp_Count(); i++) {
			
			// Left
			l_Col = i % 48;
			r_Col = 95 - i % 48;
			lr_Row = (UInt_t)(i / 48);
			
			// Put the address in linear style
			ldrd2_Left->dp_Value(i) = l_Col + lr_Row * 96;	
			ldrd2_Right->dp_Value(i) = r_Col + lr_Row * 96;

		}

	///////////////////////////////////////
	// SOI-2 ANALOG DETECTOR DESCRIPTION //
	///////////////////////////////////////
	detector.push_back( new geom_Frame() );
	detector[1]->Name("SOI2 Analog");

	// Defines the hardware chips
		// SOI2 analog sector
		detector[1]->chip(0)->Name("Analog");   // Analog pixel sector of SOI2
		detector[1]->chip(0)->col_Count(40);	// 40 columns
		detector[1]->chip(0)->row_Count(172);	// 172 rows
		detector[1]->chip(0)->col_Pitch(20);	// Pixel column pitch
		detector[1]->chip(0)->row_Pitch(20);	// Pixel row pitch
	
	// Defines the logic layers

		// Just one logical layer
		detector[1]->layer(0)->Name("Signal");		// The signal (abstracted) layer
		detector[1]->layer(0)->dp_col_Count(40);	// Logical column count
		detector[1]->layer(0)->dp_row_Count(172);	// Logical row count
		
	// Defines the chip/channel/layer connections
	
		// Analog output
		detector[1]->channel(0)->Name("Analog output");	// Chip/Layer connection
		detector[1]->channel(0)->chip_Idx(0);			// Data are shaped as decribed by chip #0
		detector[1]->channel(0)->layer_Idx(0);			// Data are directed to layer #0

	// Sets the chip geometry
		// Simple 1-to-1 mapping
		geom_Chip* soi2_Analog = detector[1]->chip(0);
		soi2_Analog->dp_all_Range(0, 1);

	///////////////////////////////////////
	// SOI-2 DIGITAL DETECTOR DESCRIPTION //
	///////////////////////////////////////
	detector.push_back( new geom_Frame() );
	detector[2]->Name("SOI2 Digital");

	// Defines the hardware chips
		// SOI2 Digital sector
		detector[2]->chip(0)->Name("Digital");   // Analog pixel sector of SOI2
		detector[2]->chip(0)->col_Count(128);	// 128 columns
		detector[2]->chip(0)->row_Count(172);	// 172 rows
		detector[2]->chip(0)->col_Pitch(20);	// Pixel column pitch
		detector[2]->chip(0)->row_Pitch(20);	// Pixel row pitch
	
	// Defines the logic layers

		// Just one logical layer
		detector[2]->layer(0)->Name("Signal");		// The signal (abstracted) layer
		detector[2]->layer(0)->dp_col_Count(128);	// Logical column count
		detector[2]->layer(0)->dp_row_Count(172);	// Logical row count

	// Defines the chip/channel/layer connections
	
		// Digital output
		detector[2]->channel(0)->Name("Digital output"); // Chip/Layer connection
		detector[2]->channel(0)->chip_Idx(0);			 // Data are shaped as decribed by chip #0
		detector[2]->channel(0)->layer_Idx(0);			 // Data are directed to layer #0

	// Sets the chip geometry
		// Simple 1-to-1 mapping
		geom_Chip* soi2_Digital = detector[2]->chip(0);
		soi2_Digital->dp_all_Range(0, 1);		

	///////////////////////
	// TEAM1K - 1 OUTPUT //
	///////////////////////
	detector.push_back( new geom_Frame() );
	detector[3]->Name("TEAM1K - 1 Out");

		// First analog output
		detector[3]->chip(0)->Name("Analog");   // Analog pixel sector of SOI2
		detector[3]->chip(0)->col_Count(64);	// 64 columns
		detector[3]->chip(0)->row_Count(1024);	// 1024 rows
		detector[3]->chip(0)->col_Pitch(10);	// Pixel column pitch
		detector[3]->chip(0)->row_Pitch(10);	// Pixel row pitch
		
	   // Define one logic layer
		detector[3]->layer(0)->Name("Signal");		// The signal (abstracted) layer
		detector[3]->layer(0)->dp_col_Count(64);	// Logical column count (64 columns * 4 outputs)
		detector[3]->layer(0)->dp_row_Count(1024);	// Logical row count
	
		// Chip/channel/layer connections
		detector[3]->channel(0)->Name("Analog output");	// Chip/Layer connection
		detector[3]->channel(0)->chip_Idx(0);			// Data are shaped as decribed by chip #0
		detector[3]->channel(0)->layer_Idx(0);			// Data are directed to layer #0
				
		// Sets the chip geometry	

		// One analog output
		geom_Chip* team_Analog  = detector[3]->chip(0);
		team_Analog->dp_all_Range(0, 1);

	////////////////////////
	// TEAM1K - 4 OUTPUTS //
	////////////////////////
	detector.push_back( new geom_Frame() );
	detector[4]->Name("TEAM1K - 4 Outs");

		// First analog output
		detector[4]->chip(0)->Name("Analog");   // Analog pixel sector of SOI2
		detector[4]->chip(0)->col_Count(64);	// 64 columns
		detector[4]->chip(0)->row_Count(1024);	// 1024 rows
		detector[4]->chip(0)->col_Pitch(10);	// Pixel column pitch
		detector[4]->chip(0)->row_Pitch(10);	// Pixel row pitch

		// Add three analog outputs
		for(UInt_t i = 1; i < 4; i++){
			detector[4]->chip_Add();
   		detector[4]->chip(i)->Name("Analog");   // Analog pixel sector of SOI2
			detector[4]->chip(i)->col_Count(64);	// 40 columns
			detector[4]->chip(i)->row_Count(1024);	// 172 rows
			detector[4]->chip(i)->col_Pitch(10);	// Pixel column pitch
			detector[4]->chip(i)->row_Pitch(10);	// Pixel row pitch
		}
	
	   // Define one logic layer
		detector[4]->layer(0)->Name("Signal");		// The signal (abstracted) layer
		detector[4]->layer(0)->dp_col_Count(256);	// Logical column count (64 columns * 4 outputs)
		detector[4]->layer(0)->dp_row_Count(1024);	// Logical row count

		for(UInt_t i = 1; i < 4; i++){
			detector[4]->channel_Add(i, 0);           // Add chip i to layer 0
			detector[4]->channel(i)->Name("Analog output");
		}
		
		// Chip/channel/layer connections
		detector[4]->channel(0)->Name("Analog output");	// Chip/Layer connection
		detector[4]->channel(0)->chip_Idx(0);			// Data are shaped as decribed by chip #0
		detector[4]->channel(0)->layer_Idx(0);			// Data are directed to layer #0
				
		// Sets the chip geometry	
		// 4 analog outputs
		geom_Chip* team_AnalogOuts[4];
		UInt_t column = 0;
		UInt_t row = 0;
		for(UInt_t i = 0; i < 4; i++){
			team_AnalogOuts[i] = detector[4]->chip(i);

			for(UInt_t j = 0; j < team_AnalogOuts[i]->dp_Count(); j++){
				column = j % 64;
				row = (UInt_t)(j / 64);
				team_AnalogOuts[i]->dp_Value(j) = 64 * i + column + 256 * row;
			}
		}

	/////////////////////////////////////////////
	// TEAM1K - FULL READOUT W/ GRETINA SYSTEM //
	/////////////////////////////////////////////

	detector.push_back(new geom_Frame());
	detector[5]->Name("TEAM1K - FULL");
	geom_Frame* team4 = detector.back();

		UInt_t col_Count = 1024;
		UInt_t row_Count = 1024;

		// Hardware ID
		team4->HrdID(128);		// FPGA-encoded hardware ID

		// 4 Chips: as we are reading 4 channels, the 16 real sectors are rearranged into 
		// 4 macro sectors, each one of 1/4 of the total number of pixels
		team4->chip(0)->col_Count(col_Count / 4);
		team4->chip(0)->row_Count(row_Count);
		for (UInt_t i = 1; i < 4; i++) {
			team4->chip_Add();
			team4->chip(i)->col_Count(col_Count / 4);
			team4->chip(i)->row_Count(row_Count);
		}

		// 1 Layer
		team4->layer(0)->Name("TEAM chip");
		team4->layer(0)->dp_col_Count(col_Count);
		team4->layer(0)->dp_row_Count(row_Count);

		// 4 Channels
		team4->channel(0)->chip_Idx(0);
		team4->channel(0)->layer_Idx(0);
		for (UInt_t i = 1; i < 4; i++) team4->channel_Add(i, 0);
			
		// The data sequence from the digitizer is:
		// Chn:	0 1 2 3 0 1 2 3 ... 0 1 2 3 0 1 2 3 ... 0 1 2 3 0 1 2 3 0 1 2 3 ... 0 1 2 3
		// Sec:  0 0 8 8 0 0 8 8 ... 0 0 8 8 0 0 8 8 ... 0 0 8 8 1 1 9 9 1 1 9 9 ... 1 1 9 9
		// Row:  0 0 0 0 0 0 0 0 ... 0 0 0 0 1 1 1 1 ... k k k k 0 0 0 0 0 0 0 0     k k k k
		// Col:  0 1 0 1 2 3 2 3 ... 626362630 1 0 1 ... 626362630 1 0 1 2 3 2 3 ... 62636263
					
		// Trhough all the expected data point per channel
		row_Count = team4->chip(0)->row_Count();
		col_Count = team4->chip(0)->col_Count();
		UInt_t width = col_Count * 4;
		UInt_t half_Width = col_Count * 2;
		for (UInt_t y = 0; y < row_Count; y++) {
			for (UInt_t x = 0; x < col_Count; x++) {
				
				// Column left-right swapped version
				
				// Digitizer 0
				team4->chip(0)->dp_Value(x, y) = y * width + ((x*2)/64+1)*64 - (x*2)%64 - 1;
				team4->chip(1)->dp_Value(x, y) = y * width + ((x*2+1)/64+1)*64 - (x*2+1)%64 -1;
				
				// Digitizer 1
				team4->chip(2)->dp_Value(x, y) = y * width + half_Width + ((x*2) /64+1)*64 - (x*2)%64 - 1;
				team4->chip(3)->dp_Value(x, y) = y * width + half_Width + ((x*2+1)/64+1)*64 - (x*2+1)%64 -1;
				
				
				// Correct version
				//team4->chip(0)->dp_Value(x, y)= y * width + x * 2;
				//team4->chip(1)->dp_Value(x, y)= y * width + x * 2 + 1;
				//team4->chip(2)->dp_Value(x, y)= y * width + x * 2 + half_Width;
				//team4->chip(3)->dp_Value(x, y)= y * width + x * 2 + half_Width + 1;
			
				// Debug version, Left and right swapped to account for a similar swap
				// into the data_Mux moddule on the firmware
				//team4->chip(0)->dp_Value(x, y)= y * width + x * 2 + 1;
				//team4->chip(1)->dp_Value(x, y)= y * width + x * 2;
				//team4->chip(2)->dp_Value(x, y)= y * width + x * 2 + half_Width + 1;
				//team4->chip(3)->dp_Value(x, y)= y * width + x * 2 + half_Width;
			
			}
		}
}