library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

-- ********************************************
-- ALL Signals are active LOW unless specified
-- ********************************************
-- 
-- REV 1.0 / February 25 2004 
-- 

-- REV 1.1 / FEBRUARY 21 2004
-- Modification of the behavior to account for
-- potential latching of the data on the same
-- edge as the timer content is changing...
-- Since the clocks are phase locked, the latch
-- is now operating on the falling edge of the
-- acqclk signal.
-- ********************************************

entity timer is
    Port ( reset 			: in std_logic;			
           reset_timer	: in std_logic;
			  timeclk		: in std_logic;
			  acqclk			: in std_logic;
           latch_en		: in std_logic;
			  msb				: out std_logic_vector (15 downto 0);
			  lsb				: out std_logic_vector (15 downto 0)
			  );
end timer;

architecture Behavioral of timer is

	--------------------------------------------------
	-- Components
	--------------------------------------------------
	COMPONENT counter32
	PORT(
		reset 	: IN std_logic;
		clk 		: IN std_logic;
		msb_out 	: OUT std_logic_vector(15 downto 0);
		lsb_out 	: OUT std_logic_vector(15 downto 0)
		);
	END COMPONENT;

	COMPONENT timelatch
	PORT(
		reset 	: IN std_logic;
		clk		: IN std_logic;
		latch_en : IN std_logic;
		msb_in 	: IN std_logic_vector(15 downto 0);
		lsb_in 	: IN std_logic_vector(15 downto 0);          
		msb_out 	: OUT std_logic_vector(15 downto 0);
		lsb_out 	: OUT std_logic_vector(15 downto 0)
		);
	END COMPONENT;

	--------------------------------------------------
	-- Signals
	--------------------------------------------------
	signal rst 					: std_logic;
	signal msb_count			: std_logic_vector(15 downto 0);
	signal lsb_count			: std_logic_vector(15 downto 0);


begin

----------------------------------------------
	rst 	<= reset_timer and reset;

----------------------------------------------
	Inst_counter32: counter32 PORT MAP(
		reset 	=> rst,
		clk 		=> timeclk,
		msb_out 	=> msb_count,
		lsb_out 	=> lsb_count
	);

----------------------------------------------
	Inst_timelatch: timelatch PORT MAP(
		reset 	=> reset,
		clk		=> acqclk,
		latch_en => latch_en,
		msb_in 	=> msb_count,
		lsb_in 	=> lsb_count,
		msb_out 	=> msb,
		lsb_out 	=> lsb
	);
----------------------------------------------

end Behavioral;