library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;


-- ********************************************
-- ALL Signals are active LOW unless specified
-- ********************************************
-- 
-- REV 1.0 / February 25 2004 
-- 
-- REV 1.1 / FEBRUARY 21 2004
-- Modification of the behavior to account for
-- potential latching of the data on the same
-- edge as the timer content is changing...
-- Since the clocks are phase locked, the latch
-- is now operating on the falling edge of the
-- acqclk signal.
-- ********************************************

entity timelatch is
    Port ( reset 		: in std_logic;
           clk 		: in std_logic;
			  latch_en	: in std_logic;
	        msb_in 	: in std_logic_vector(15 downto 0);
           lsb_in 	: in std_logic_vector(15 downto 0);
           msb_out 	: out std_logic_vector(15 downto 0);
           lsb_out 	: out std_logic_vector(15 downto 0));
end timelatch;

architecture Behavioral of timelatch is

signal msb_internal: std_logic_vector(15 downto 0);
signal lsb_internal: std_logic_vector(15 downto 0);

begin

	msb_out	<= msb_internal;
	lsb_out	<= lsb_internal;

	process (reset, clk, msb_in, lsb_in, msb_internal, lsb_internal)
	begin
		if reset = '0' then

			msb_internal <= "0000000000000000";
			lsb_internal <= "0000000000000000";

		elsif ( clk'event and clk = '0' ) then		 -- FALLING EDGE !!

			if latch_en = '0' then
		
				msb_internal <= msb_in;
				lsb_internal <= lsb_in;

			else

				msb_internal <= msb_internal;
				lsb_internal <= lsb_internal;
			
			end if;

		end if;

	end process;

end Behavioral;