--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   13:46:26 08/08/2006
-- Design Name:   addrtime_ctrl
-- Module Name:   E:/jfb/Xilinx_XP/SAO/Work/timer/testbench.vhd
-- Project Name:  timer
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: addrtime_ctrl
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY testbench_vhd IS
END testbench_vhd;

ARCHITECTURE behavior OF testbench_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT addrtime_ctrl
	PORT(
		reset 		: IN std_logic;
		reset_timer : IN std_logic;
		timeclk 		: IN std_logic;
		acqclk 		: IN std_logic;
		latch_en 	: IN std_logic;
		timersel 	: IN std_logic;
		header 		: IN std_logic;
		chnid 		: IN std_logic;
		timer_upper : IN std_logic;
		timer_lower : IN std_logic;
		dr 			: IN std_logic_vector(1 downto 0);
		pt 			: IN std_logic_vector(1 downto 0);
		dwc 			: IN std_logic;
		ndwc 			: IN std_logic;
		channel 		: IN std_logic_vector(1 downto 0);
		module 		: IN std_logic_vector(7 downto 0);          
		data_out 	: OUT std_logic_vector(15 downto 0)
		);
	END COMPONENT;

	--Inputs
	SIGNAL reset 			:  std_logic ;
	SIGNAL reset_timer 	:  std_logic := '1';
	SIGNAL timeclk 		:  std_logic := '0';
	SIGNAL acqclk 			:  std_logic := '0';
	SIGNAL latch_en 		:  std_logic ;
	SIGNAL timersel 		:  std_logic ;
	SIGNAL header 			:  std_logic ;
	SIGNAL chnid 			:  std_logic ;
	SIGNAL timer_upper 	:  std_logic ;
	SIGNAL timer_lower 	:  std_logic ;
	SIGNAL dwc 				:  std_logic ;
	SIGNAL ndwc 			:  std_logic ;
	SIGNAL dr 				:  std_logic_vector(1 downto 0) := "01";
	SIGNAL pt 				:  std_logic_vector(1 downto 0) := "00";
	SIGNAL channel 		:  std_logic_vector(1 downto 0) := "10";
	SIGNAL module 			:  std_logic_vector(7 downto 0) := "10101010";

	--Outputs
	SIGNAL data_out :  std_logic_vector(15 downto 0);

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: addrtime_ctrl PORT MAP(
		reset 		=> reset,
		reset_timer => reset_timer,
		timeclk 		=> timeclk,
		acqclk 		=> acqclk,
		latch_en 	=> latch_en,
		timersel 	=> timersel,
		header 		=> header,
		chnid 		=> chnid,
		timer_upper => timer_upper,
		timer_lower => timer_lower,
		dr 			=> dr,
		pt 			=> pt,
		dwc 			=> dwc,
		ndwc 			=> ndwc,
		channel 		=> channel,
		module 		=> module,
		data_out 	=> data_out
	);

	tb : PROCESS
	BEGIN

		-- Wait 100 ns for global reset to finish
		wait for 100 ns;

		-- Place stimulus here
		
		acqclk		<=	(not acqclk) after 0.5 us;
		timeclk		<=	(not timeclk) after 5 us;
		reset			<=	'0','1' after 10 us;
	
		latch_en		<=	'1','0' after 200 us;
		timersel		<=	'1','0' after 500 us;
		header		<=	'1','0' after 600 us,'1' after 650 us;
		chnid			<=	'1','0' after 700 us, '1' after 750 us;
		timer_upper	<=	'1','0' after 800 us, '1' after 850 us;
		timer_lower	<=	'1','0' after 900 us, '1' after 950 us;
		dwc			<=	'1','0' after 1000 us, '1' after 1050 us;
		ndwc			<=	'1','0' after 1100 us, '1' after 1150 us;
	
		wait; -- will wait forever
	END PROCESS;

END;