library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

-- ********************************************
-- ALL Signals are active LOW unless specified
-- ********************************************
-- 
-- REV 1.0 / February 25 2004 
-- 
-- ********************************************
entity mux3216 is
    Port ( channel_sel	: in  std_logic;							  -- channel select (OE)

	        header			: in 	std_logic;							  -- Header output en

	        chn_id			: in 	std_logic;							  -- Channel id output en
			  addr_data		: in 	std_logic_vector(9 downto 0);	  -- channel and module addr

           timer_upper	: in 	std_logic;							  -- trigger MSB output en
			  timer_msb		: in 	std_logic_vector(15 downto 0);  -- trigger MSB data
			  timer_lower	: in  std_logic;							  -- trigger LSB output en
           timer_lsb		: in 	std_logic_vector(15 downto 0);  -- trigger LSB data

           dr				: in 	std_logic_vector(1 downto 0);   -- decimation ratio
           pt				: in 	std_logic_vector(1 downto 0);   -- pre-trigger, N1 parameter (trigger location)
           dwc				: in 	std_logic;  						  -- decimation word count output en
           ndwc			: in 	std_logic;  						  -- non-decimation word count output en
     
			  muxout 		: out std_logic_vector(15 downto 0)
           );
end mux3216;

architecture Behavioral of mux3216 is

begin
	process (channel_sel, header, chn_id, timer_upper, timer_lower, dr, pt, addr_data, dwc, ndwc, timer_msb, timer_lsb)
	begin

		if channel_sel = '0' then
				
			if header = '0' then
				muxout <= CONV_STD_LOGIC_VECTOR (12, 16);
				

			elsif chn_id = '0' then
				muxout(15 downto 14) <= "00";
				muxout(13 downto 12) <= dr;
				muxout(11 downto 10) <= pt;
				muxout(9 downto 0) 	<= addr_data;
		
			elsif timer_upper = '0' then 
				muxout	<= timer_msb;
		
			elsif timer_lower = '0' then 
				muxout	<= timer_lsb; 
		
			elsif dwc = '0' then 
				case pt is
					when "00" =>
						muxout <= CONV_STD_LOGIC_VECTOR (512, 16);

					when "01" =>
						muxout <= CONV_STD_LOGIC_VECTOR (1024, 16);

					when "10" =>
						muxout <= CONV_STD_LOGIC_VECTOR (2048, 16);

					when others =>
						muxout <= CONV_STD_LOGIC_VECTOR (2560, 16);

				end case;

			elsif ndwc = '0' then 
				case pt is
					when "00" =>
						muxout <= CONV_STD_LOGIC_VECTOR (3572, 16);

					when "01" =>
						muxout <= CONV_STD_LOGIC_VECTOR (3060, 16);

					when "10" =>
						muxout <= CONV_STD_LOGIC_VECTOR (2036, 16);

					when others =>
						muxout <= CONV_STD_LOGIC_VECTOR (1524, 16);

				end case;

			else
				muxout	<= "0000000000000000";
										
			end if;

		else
				muxout 	<= "0000000000000000";
		
		end if;
 	end process;													  

end Behavioral;