library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

-- ********************************************
-- ALL Signals are active LOW unless specified
-- ********************************************
-- 
-- REV 1.0 / February 25 2004 
-- The channel address is hard-encoded on the board (resistors)
--	Same thing for the module address.
-- There are four channels per modules (2 bits, LSBs)
-- There are at least 4 modules, requiring 2 bits.
-- The module address field is 8 bits (256 modules)
-- ********************************************
entity chn_addr is
    Port ( channel_addr 	: in 	std_logic_vector(1 downto 0);
           module_addr 		: in 	std_logic_vector(7 downto 0);
           addr_data 		: out std_logic_vector(9 downto 0)
			 );
end chn_addr;

architecture Behavioral of chn_addr is

begin
	process (channel_addr, module_addr)
	begin

		addr_data(9) 				<= module_addr(7);
		addr_data(8) 				<= module_addr(6);
		addr_data(7) 				<= module_addr(5);
		addr_data(6) 				<= module_addr(4);
		addr_data(5) 				<= module_addr(3);
		addr_data(4) 				<= module_addr(2);
		addr_data(3) 				<= module_addr(1);
		addr_data(2) 				<= module_addr(0);
		addr_data(1) 				<= channel_addr(1);
		addr_data(0) 				<= channel_addr(0);

	end process;

end Behavioral;