library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

-- ********************************************
-- ALL Signals are active LOW unless specified
-- ********************************************
-- 
-- REV 1.0 / February 25 2004 
-- The channel address is hard-encoded on the board (resistors)
--	Same thing for the module address.
-- There are four channels per modules (2 bits, LSBs)
-- There are at least 4 modules, requiring 2 bits.
-- The module address field is 8 bits (256 modules)
-- ********************************************

-- NOTE / February 21 2005
-- ------------------------
-- The time counter advances with the timeclk signal.
-- The acqclk signal is used to ensure that the time is latched
-- at the proper moment
-- The proper operation requires that the signal acqclk and timeclk
-- are phase-locked (ie. generated from the same source)


entity addrtime_ctrl is
    Port ( reset 			: in 	std_logic;
           reset_timer	: in 	std_logic;
			  timeclk		: in 	std_logic;	-- clock for the timer
			  acqclk			: in 	std_logic;	-- clock from the acquisition (channel)
           latch_en 		: in 	std_logic;	-- from channel to provide instant for tag
			  timersel			: in  std_logic;	-- channel sel for output mux
			  header			: in 	std_logic;	-- mux sel	header
			  chnid			: in 	std_logic;	-- mux sel	channel addr
			  timer_upper	: in	std_logic;	-- mux sel	timer msb
	        timer_lower 	: in  std_logic;	-- mux sel	timer msb
			  dr 				: in  std_logic_vector(1 downto 0);	 -- decimation ratio
			  pt 				: in  std_logic_vector(1 downto 0);	 -- pre-trigger param
			  dwc 			: in  std_logic;							 -- decimation word count output en 
			  ndwc			: in  std_logic;          				 -- non-decimation word count output en 
			  channel		: in 	std_logic_vector(1 downto 0);	 -- address encoded on-board
           module		 	: in 	std_logic_vector(7 downto 0);	 -- address encoded on-board
           data_out 		: out std_logic_vector(15 downto 0)
			  );
end addrtime_ctrl;

architecture Behavioral of addrtime_ctrl is

	----------------------------------------
	-- Components
	----------------------------------------

	----------------------------------------------------
	COMPONENT timer
	PORT(
		reset 			: IN std_logic;
		reset_timer 	: IN std_logic;
		timeclk 			: IN std_logic;
		acqclk 			: IN std_logic;
		latch_en 		: IN std_logic;          
		msb 				: OUT std_logic_vector(15 downto 0);
		lsb 				: OUT std_logic_vector(15 downto 0)
		);
	END COMPONENT;
	----------------------------------------------------
	COMPONENT chn_addr
	PORT(
		channel_addr 	: IN  std_logic_vector(1 downto 0);
		module_addr 	: IN  std_logic_vector(7 downto 0);          
		addr_data 		: OUT std_logic_vector(9 downto 0)
		);
	END COMPONENT;
	----------------------------------------------------
	COMPONENT mux3216
	PORT(
		channel_sel 	: IN std_logic;
		header 			: IN std_logic;
		chn_id 			: IN std_logic;
		addr_data 		: IN std_logic_vector(9 downto 0);
		timer_upper 	: IN std_logic;
		timer_msb 		: IN std_logic_vector(15 downto 0);
		timer_lower 	: IN std_logic;
		timer_lsb 		: IN std_logic_vector(15 downto 0);
		dr 				: IN std_logic_vector(1 downto 0);
		pt 				: IN std_logic_vector(1 downto 0);
		dwc 				: IN std_logic;
		ndwc 				: IN std_logic;          
		muxout 			: OUT std_logic_vector(15 downto 0)
		);
	END COMPONENT;
	----------------------------------------------------

	----------------------------------------
	-- Signals
	----------------------------------------

	signal msb_sig 			: std_logic_vector(15 downto 0);
	signal lsb_sig 			: std_logic_vector(15 downto 0);
	signal addr_data_sig 	: std_logic_vector(9 downto 0);
	signal muxout_sig			: std_logic_vector(15 downto 0);

----------------------------------------
-- Architecture's Description
----------------------------------------
begin

	data_out(15 downto 0)	<= muxout_sig;

	----------------------------------------------------
	Inst_timer: timer PORT MAP(
		reset 			=> reset,
		reset_timer 	=> reset_timer,
		timeclk 			=> timeclk,
		acqclk 			=> acqclk,
		latch_en 		=> latch_en,
		msb 				=> msb_sig,
		lsb 				=> lsb_sig
	);
	----------------------------------------------------
	Inst_chn_addr: chn_addr PORT MAP(
		channel_addr 	=> channel,
		module_addr 	=> module,
		addr_data 		=> addr_data_sig
	);
	----------------------------------------------------
	Inst_mux3216: mux3216 PORT MAP(
		channel_sel 	=> timersel,
		header 			=> header,
		chn_id 			=> chnid,
		addr_data 		=> addr_data_sig,
		timer_upper		=> timer_upper,
		timer_msb 		=> msb_sig,
		timer_lower 	=> timer_lower,
		timer_lsb 		=> lsb_sig,
		dr 				=> dr,
		pt 				=> pt,
		dwc 				=> dwc,
		ndwc 				=> ndwc,
		muxout 			=> muxout_sig
	);
	----------------------------------------------------

end Behavioral;