Release 8.2.01i - xst I.32 Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to ./xst/projnav.tmp CPU : 0.00 / 0.20 s | Elapsed : 0.00 / 0.00 s --> Parameter xsthdpdir set to ./xst CPU : 0.00 / 0.20 s | Elapsed : 0.00 / 0.00 s --> Reading design: addrtime_ctrl.prj TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) Design Hierarchy Analysis 4) HDL Analysis 5) HDL Synthesis 5.1) HDL Synthesis Report 6) Advanced HDL Synthesis 6.1) Advanced HDL Synthesis Report 7) Low Level Synthesis 8) Partition Report 9) Final Report ========================================================================= * Synthesis Options Summary * ========================================================================= ---- Source Parameters Input File Name : "addrtime_ctrl.prj" Input Format : mixed Ignore Synthesis Constraint File : NO ---- Target Parameters Output File Name : "addrtime_ctrl" Output Format : NGC Target Device : XC9500XL CPLDs ---- Source Options Top Module Name : addrtime_ctrl Automatic FSM Extraction : YES FSM Encoding Algorithm : Auto Mux Extraction : YES Resource Sharing : YES ---- Target Options Add IO Buffers : YES MACRO Preserve : YES XOR Preserve : YES Equivalent register Removal : YES ---- General Options Optimization Goal : Area Optimization Effort : 1 Keep Hierarchy : YES RTL Output : Yes Hierarchy Separator : / Bus Delimiter : <> Case Specifier : maintain ---- Other Options lso : addrtime_ctrl.lso verilog2001 : YES safe_implementation : No Clock Enable : YES wysiwyg : NO ========================================================================= ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file "E:/jfb/Xilinx_XP/SAO/Work/timer/counter32.vhd" in Library work. Architecture behavioral of Entity counter32 is up to date. Compiling vhdl file "E:/jfb/Xilinx_XP/SAO/Work/timer/timelatch.vhd" in Library work. Architecture behavioral of Entity timelatch is up to date. Compiling vhdl file "E:/jfb/Xilinx_XP/SAO/Work/timer/timer.vhd" in Library work. Architecture behavioral of Entity timer is up to date. Compiling vhdl file "E:/jfb/Xilinx_XP/SAO/Work/timer/chn_addr.vhd" in Library work. Architecture behavioral of Entity chn_addr is up to date. Compiling vhdl file "E:/jfb/Xilinx_XP/SAO/Work/timer/mux3216.vhd" in Library work. Architecture behavioral of Entity mux3216 is up to date. Compiling vhdl file "E:/jfb/Xilinx_XP/SAO/Work/timer/addrtime_ctrl.vhd" in Library work. Architecture behavioral of Entity addrtime_ctrl is up to date. ========================================================================= * Design Hierarchy Analysis * ========================================================================= Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Building hierarchy successfully finished. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Performing bidirectional port resolution... Synthesizing Unit . Related source file is "E:/jfb/Xilinx_XP/SAO/Work/timer/chn_addr.vhd". Unit synthesized. Synthesizing Unit . Related source file is "E:/jfb/Xilinx_XP/SAO/Work/timer/mux3216.vhd". Unit synthesized. Synthesizing Unit . Related source file is "E:/jfb/Xilinx_XP/SAO/Work/timer/counter32.vhd". Found 16-bit comparator less for signal <$cmp_lt0000> created at line 52. Found 16-bit comparator less for signal <$cmp_lt0001> created at line 59. Found 16-bit up counter for signal . Found 16-bit up counter for signal . Summary: inferred 2 Counter(s). inferred 2 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is "E:/jfb/Xilinx_XP/SAO/Work/timer/timelatch.vhd". Found 16-bit register for signal . Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is "E:/jfb/Xilinx_XP/SAO/Work/timer/timer.vhd". Unit synthesized. Synthesizing Unit . Related source file is "E:/jfb/Xilinx_XP/SAO/Work/timer/addrtime_ctrl.vhd". Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # Counters : 2 16-bit up counter : 2 # Registers : 2 16-bit register : 2 # Comparators : 2 16-bit comparator less : 2 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= ========================================================================= Advanced HDL Synthesis Report Macro Statistics # Counters : 2 16-bit up counter : 2 # Registers : 48 Flip-Flops : 48 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= WARNING:Xst:1355 - Unit chn_addr is merged (low complexity) Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... implementation constraint: INIT=r : cnt1_15 implementation constraint: INIT=r : cnt2_15 implementation constraint: INIT=r : cnt1_14 implementation constraint: INIT=r : cnt2_0 implementation constraint: INIT=r : cnt2_1 implementation constraint: INIT=r : cnt2_2 implementation constraint: INIT=r : cnt2_3 implementation constraint: INIT=r : cnt2_4 implementation constraint: INIT=r : cnt2_5 implementation constraint: INIT=r : cnt2_6 implementation constraint: INIT=r : cnt2_7 implementation constraint: INIT=r : cnt2_8 implementation constraint: INIT=r : cnt2_9 implementation constraint: INIT=r : cnt2_10 implementation constraint: INIT=r : cnt2_11 implementation constraint: INIT=r : cnt2_12 implementation constraint: INIT=r : cnt2_13 implementation constraint: INIT=r : cnt2_14 implementation constraint: INIT=r : cnt1_13 implementation constraint: INIT=r : cnt1_12 implementation constraint: INIT=r : cnt1_0 implementation constraint: INIT=r : cnt1_1 implementation constraint: INIT=r : cnt1_2 implementation constraint: INIT=r : cnt1_3 implementation constraint: INIT=r : cnt1_4 implementation constraint: INIT=r : cnt1_5 implementation constraint: INIT=r : cnt1_6 implementation constraint: INIT=r : cnt1_7 implementation constraint: INIT=r : cnt1_8 implementation constraint: INIT=r : cnt1_9 implementation constraint: INIT=r : cnt1_10 implementation constraint: INIT=r : cnt1_11 Optimizing unit ... ========================================================================= * Partition Report * ========================================================================= Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- ========================================================================= * Final Report * ========================================================================= Final Results RTL Top Level Output File Name : addrtime_ctrl.ngr Top Level Output File Name : addrtime_ctrl Output Format : NGC Optimization Goal : Area Keep Hierarchy : YES Target Technology : XC9500XL CPLDs Macro Preserve : YES XOR Preserve : YES Clock Enable : YES wysiwyg : NO Design Statistics # IOs : 42 Cell Usage : # BELS : 463 # AND2 : 164 # AND3 : 24 # AND4 : 2 # INV : 169 # OR2 : 74 # XOR2 : 30 # FlipFlops/Latches : 64 # FDC : 16 # FDCE : 48 # IO Buffers : 42 # IBUF : 26 # OBUF : 16 ========================================================================= CPU : 6.31 / 6.53 s | Elapsed : 7.00 / 7.00 s --> Total memory usage is 112912 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 1 ( 0 filtered) Number of infos : 0 ( 0 filtered)