# Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl 
# do top_tb0.fdo 
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim XE III vcom 6.0a Compiler 2004.11 Nov 10 2004
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity receivecommand
# -- Compiling architecture behavioral of receivecommand
# Model Technology ModelSim XE III vcom 6.0a Compiler 2004.11 Nov 10 2004
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity chip
# -- Compiling architecture behavioral of chip
# Model Technology ModelSim XE III vcom 6.0a Compiler 2004.11 Nov 10 2004
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Compiling entity top
# -- Compiling architecture behavioral of top
# Model Technology ModelSim XE III vcom 6.0a Compiler 2004.11 Nov 10 2004
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package vcomponents
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity top_tb0
# -- Compiling architecture testbench_arch of top_tb0
# vsim -lib work -t 1ps top_tb0 
# Loading C:\Modeltech_xe_starter\win32xoem/../std.standard
# Loading C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_1164(body)
# Loading C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_arith(body)
# Loading C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_unsigned(body)
# Loading C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.vcomponents
# Loading C:\Modeltech_xe_starter\win32xoem/../std.textio(body)
# Loading C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_textio(body)
# Loading work.top_tb0(testbench_arch)
# Loading work.top(behavioral)
# Loading C:\Modeltech_xe_starter\win32xoem/../ieee.vital_timing(body)
# Loading C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.ibuf(ibuf_v)
# Loading C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.bufg(bufg_v)
# Loading C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.obuft(obuft_v)
# Loading C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.obuf(obuf_v)
# Loading work.chip(behavioral)
# Loading work.receivecommand(behavioral)
# .main_pane.mdi.interior.cs.vm.paneset.cli_0.wf.clip.cs
# .main_pane.workspace
# .main_pane.signals.interior.cs
# ** Failure: Simulation successful (not a failure).  No problems detected.
#    Time: 120020 ns  Iteration: 0  Process: /top_tb0/line__174 File: top_tb0.vhw
# Break at top_tb0.vhw line 940
# Simulation Breakpoint: Break at top_tb0.vhw line 940
# MACRO ./top_tb0.fdo PAUSED at line 15