version 3
U:/Projects/SAO/VHDL/SAOTxBoard/sao_tx/top.vhd
top
VHDL
VHDL
top_tb0.xwv
Clocked
-
-
120000000000
ns
GSR:true
PRLD:false
100000000
CLOCK_LIST_BEGIN
CLK_40MHZ
10000000
10000000
5000000
5000000
100000000
RISING
CLOCK_LIST_END
SIGNAL_LIST_BEGIN
ACLK
CLK_40MHZ
ACQENnB0
CLK_40MHZ
ACQENnB1
CLK_40MHZ
ACQENnB2
CLK_40MHZ
ACQENnB3
CLK_40MHZ
ADCRST
CLK_40MHZ
CLK_40MHZ_OK
CLK_40MHZ
CTRL
CLK_40MHZ
CTRL_OK
CLK_40MHZ
DAC_CSn_B
CLK_40MHZ
DAC_DIN
CLK_40MHZ
DAC_LOADn
CLK_40MHZ
DAC_SCLK
CLK_40MHZ
DATA
CLK_40MHZ
DR0
CLK_40MHZ
DR1
CLK_40MHZ
D_OEn_B
CLK_40MHZ
ENABLEn_B
CLK_40MHZ
FFn_B
CLK_40MHZ
HFn_B
CLK_40MHZ
LOCKED
CLK_40MHZ
POR
CLK_40MHZ
PT0
CLK_40MHZ
PT1
CLK_40MHZ
RCLK3
CLK_40MHZ
RCLK4_B
CLK_40MHZ
RESETn
CLK_40MHZ
RST4n_B
CLK_40MHZ
RST_TIMERn
CLK_40MHZ
SYNCn
CLK_40MHZ
SYSCLK
CLK_40MHZ
TCLK
CLK_40MHZ
TMODE
CLK_40MHZ
uD_OEn_B
CLK_40MHZ
uDr
CLK_40MHZ
uDw
CLK_40MHZ
SIGNAL_LIST_END
SIGNALS_NOT_ON_DISPLAY
ACLK_DIFF
ACQENnB0_DIFF
ACQENnB1_DIFF
ACQENnB2_DIFF
ACQENnB3_DIFF
ADCRST_DIFF
DAC_CSn_B_DIFF
DAC_DIN_DIFF
DAC_LOADn_DIFF
DAC_SCLK_DIFF
DATA_DIFF
DR0_DIFF
DR1_DIFF
D_OEn_B_DIFF
ENABLEn_B_DIFF
PT0_DIFF
PT1_DIFF
RCLK3_DIFF
RCLK4_B_DIFF
RESETn_DIFF
RST4n_B_DIFF
RST_TIMERn_DIFF
SYNCn_DIFF
SYSCLK_DIFF
TCLK_DIFF
TMODE_DIFF
uD_OEn_B_DIFF
uDw_DIFF
SIGNALS_NOT_ON_DISPLAY_END
MARKER_LIST_BEGIN
466153675
643985167
864979642
5662340482
MARKER_LIST_END
MEASURE_LIST_BEGIN
MEASURE_LIST_END
SIGNAL_ORDER_BEGIN
CLK_40MHZ
CLK_40MHZ_OK
CTRL
CTRL_OK
LOCKED
POR
FFn_B
HFn_B
uDr
ACLK
ADCRST
DAC_DIN
DAC_LOADn
DAC_SCLK
DR0
DR1
PT0
PT1
RCLK3
RESETn
RST_TIMERn
SYNCn
SYSCLK
TCLK
TMODE
ACQENnB0
ACQENnB1
ACQENnB2
ACQENnB3
DAC_CSn_B
DATA
D_OEn_B
ENABLEn_B
RCLK4_B
RST4n_B
uD_OEn_B
uDw
SIGNAL_ORDER_END
-X-X-X-