Logic

Signal Name	Total Pterms	Total Inputs	Function Block	Macrocell	Power Mode	Slew Rate	Pin Number	Pin Type	Pin Use	Reg Init State
chip_comp/TCLKCounter<10>	2	14	FB4	MC5	STD		3	I/O/GTS4	I	RESET
chip_comp/CommandReceived<6>	2	5	FB4	MC6	STD		4	I/O	I	RESET
chip_comp/CommandReceived<4>	2	5	FB4	MC8	STD		5	I/O/GTS1	I	RESET
chip_comp/CommandReceived<15>	2	5	FB4	MC12	STD		6	I/O/GTS2	(b)	RESET
chip_comp/CommandReceived<13>	2	5	FB4	MC14	STD		7	I/O	(b)	RESET
ACQENnB0<3>	1	2	FB2	MC5	STD	SLOW	11	I/O	O	SET
ACQENnB1<3>	1	2	FB2	MC6	STD	SLOW	12	I/O	O	SET
ACQENnB2<3>	1	2	FB2	MC8	STD	SLOW	13	I/O	O	SET
ACQENnB3<3>	1	2	FB2	MC10	STD	SLOW	14	I/O	O	SET
ACQENnB0<2>	1	2	FB2	MC12	STD	SLOW	15	I/O	O	SET
ACQENnB1<2>	1	2	FB2	MC14	STD	SLOW	16	I/O	O	SET
ACQENnB2<2>	1	2	FB2	MC15	STD	SLOW	17	I/O	O	SET
ACQENnB3<2>	1	2	FB2	MC17	STD	SLOW	19	I/O	O	SET
ACQENnB0<1>	1	2	FB1	MC5	STD	SLOW	20	I/O	O	SET
ACQENnB1<1>	1	2	FB1	MC6	STD	SLOW	21	I/O	O	SET
ACQENnB2<1>	1	2	FB1	MC8	STD	SLOW	22	I/O	O	SET
ACQENnB3<1>	1	2	FB1	MC10	STD	SLOW	23	I/O	O	SET
ACQENnB0<0>	1	2	FB1	MC12	STD	SLOW	24	I/O	O	SET
SYSCLK	1	1	FB1	MC14	STD	SLOW	25	I/O	O
TCLK	1	11	FB1	MC15	STD	SLOW	26	I/O	O	RESET
ACLK	1	9	FB1	MC17	STD	SLOW	27	I/O	O	RESET
RCLK3	1	1	FB3	MC2	STD	SLOW	28	I/O	O
chip_comp/StatusDataSel<1>	2	10	FB3	MC10	STD		30	I/O/GCK1	GCK/I	RESET
chip_comp/ACLKCounter<8>	2	11	FB3	MC12	STD		31	I/O	I	RESET
chip_comp/ACLKCounter<6>	4	11	FB3	MC14	STD		32	I/O/GCK2	(b)	RESET
ACQENnB1<0>	1	2	FB3	MC15	STD	SLOW	33	I/O	O	SET
ACQENnB2<0>	1	2	FB5	MC2	STD	SLOW	34	I/O	O	SET
ACQENnB3<0>	1	2	FB5	MC5	STD	SLOW	35	I/O	O	SET
DATA<15>	6	7	FB5	MC10	STD	SLOW	39	I/O	O
DATA<14>	6	7	FB5	MC12	STD	SLOW	40	I/O	O
DATA<13>	6	7	FB5	MC14	STD	SLOW	41	I/O	O
DATA<12>	6	7	FB5	MC15	STD	SLOW	43	I/O	O
DATA<11>	6	7	FB5	MC17	STD	SLOW	44	I/O	O
DATA<10>	6	7	FB7	MC3	STD	SLOW	45	I/O	O
DATA<9>	6	7	FB7	MC5	STD	SLOW	46	I/O	O
DATA<8>	6	7	FB7	MC12	STD	SLOW	48	I/O	O
DATA<7>	6	7	FB7	MC15	STD	SLOW	49	I/O	O
DATA<6>	6	7	FB9	MC2	STD	SLOW	50	I/O	O
DATA<5>	6	7	FB9	MC3	STD	SLOW	51	I/O	O
DATA<4>	6	7	FB9	MC5	STD	SLOW	52	I/O	O
DATA<3>	6	7	FB9	MC6	STD	SLOW	53	I/O	O
DATA<2>	6	7	FB9	MC8	STD	SLOW	54	I/O	O
DATA<1>	6	7	FB9	MC11	STD	SLOW	56	I/O	O
DATA<0>	6	7	FB9	MC12	STD	SLOW	57	I/O	O
RST4n_B<0>	1	5	FB9	MC14	STD	SLOW	58	I/O	O	RESET
D_OEn_B<0>	1	4	FB9	MC17	STD	SLOW	59	I/O	O	SET
RCLK4_B<0>	1	3	FB11	MC3	STD	SLOW	60	I/O	O
RST4n_B<1>	1	5	FB11	MC5	STD	SLOW	61	I/O	O	RESET
D_OEn_B<1>	1	4	FB11	MC10	STD	SLOW	64	I/O	O	SET
RCLK4_B<1>	1	3	FB11	MC11	STD	SLOW	66	I/O	O
RST4n_B<2>	1	5	FB11	MC12	STD	SLOW	68	I/O	O	RESET
D_OEn_B<2>	1	4	FB11	MC14	STD	SLOW	69	I/O	O	SET
RCLK4_B<2>	1	3	FB11	MC17	STD	SLOW	70	I/O	O
RST4n_B<3>	1	5	FB13	MC2	STD	SLOW	71	I/O	O	RESET
D_OEn_B<3>	1	4	FB13	MC8	STD	SLOW	74	I/O	O	SET
RCLK4_B<3>	1	3	FB13	MC11	STD	SLOW	75	I/O	O
DAC_LOADn	0	0	FB13	MC14	STD	SLOW	76	I/O	O
DAC_DIN	0	0	FB13	MC15	STD	SLOW	77	I/O	O
DAC_SCLK	0	0	FB13	MC17	STD	SLOW	78	I/O	O
DAC_CSn_B<0>	0	0	FB15	MC2	STD	SLOW	79	I/O	O
DAC_CSn_B<1>	0	0	FB15	MC3	STD	SLOW	80	I/O	O
DAC_CSn_B<2>	0	0	FB15	MC8	STD	SLOW	81	I/O	O
DAC_CSn_B<3>	0	0	FB15	MC10	STD	SLOW	82	I/O	O
chip_comp/GenDataCounter<13>	2	15	FB15	MC11	STD		83	I/O	(b)	RESET
ENABLEn_B<3>	1	2	FB15	MC12	STD	SLOW	85	I/O	O	SET
ENABLEn_B<2>	1	2	FB15	MC14	STD	SLOW	86	I/O	O	SET
ENABLEn_B<1>	1	2	FB15	MC15	STD	SLOW	87	I/O	O	SET
ENABLEn_B<0>	1	2	FB15	MC17	STD	SLOW	88	I/O	O	SET
chip_comp/ENABLEn_BReg<0>	2	15	FB16	MC2	STD		91	I/O	I	RESET
chip_comp/ACQENnB3Reg<1>	2	15	FB16	MC3	STD		92	I/O	(b)	RESET
chip_comp/ACQENnB2Reg<2>	2	15	FB16	MC5	STD		93	I/O	I	RESET
PT0	2	10	FB16	MC6	STD	SLOW	94	I/O	O	RESET
PT1	2	10	FB16	MC8	STD	SLOW	95	I/O	O	RESET
DR0	2	10	FB16	MC10	STD	SLOW	96	I/O	O	RESET
DR1	2	10	FB16	MC11	STD	SLOW	97	I/O	O	RESET
TMODE	2	10	FB16	MC12	STD	SLOW	98	I/O	O	RESET
ADCRST	2	4	FB14	MC3	STD	SLOW	100	I/O	O	RESET
chip_comp/StatusDataSel<4>	2	10	FB14	MC5	STD		101	I/O	(b)	RESET
chip_comp/StatusDataSel<3>	2	10	FB14	MC6	STD		102	I/O	(b)	RESET
chip_comp/StatusDataSel<0>	2	10	FB14	MC8	STD		103	I/O	(b)	RESET
chip_comp/GenDataCMD	2	11	FB14	MC10	STD		104	I/O	(b)	RESET
RESETn	1	1	FB14	MC11	STD	SLOW	105	I/O	O
RST_TIMERn	2	4	FB14	MC14	STD	SLOW	106	I/O	O	SET
chip_comp/DataPackageTXEn	2	10	FB14	MC15	STD		107	I/O	(b)	RESET
chip_comp/SimulData<6>	1	1	FB12	MC8	STD		113	I/O	(b)	RESET
chip_comp/SimulData<4>	1	1	FB12	MC10	STD		115	I/O	(b)	RESET
chip_comp/SimulData<2>	1	1	FB12	MC12	STD		116	I/O	(b)	RESET
chip_comp/ReceiveCommandComp/sr<9>	1	2	FB10	MC2	STD		117	I/O	(b)	RESET
chip_comp/ReceiveCommandComp/sr<8>	1	2	FB10	MC3	STD		118	I/O	(b)	RESET
uD_OEn_B<0>	0	0	FB10	MC5	STD	SLOW	119	I/O	O
uD_OEn_B<1>	0	0	FB10	MC6	STD	SLOW	120	I/O	O
uD_OEn_B<2>	0	0	FB10	MC8	STD	SLOW	121	I/O	O
uD_OEn_B<3>	0	0	FB10	MC10	STD	SLOW	124	I/O	O
uDw<7>	0	0	FB10	MC11	STD	SLOW	125	I/O	O
uDw<6>	0	0	FB10	MC12	STD	SLOW	126	I/O	O
uDw<5>	0	0	FB10	MC14	STD	SLOW	128	I/O	O
uDw<4>	0	0	FB10	MC17	STD	SLOW	129	I/O	O
uDw<3>	0	0	FB8	MC2	STD	SLOW	130	I/O	O
uDw<2>	0	0	FB8	MC3	STD	SLOW	131	I/O	O
uDw<1>	0	0	FB8	MC5	STD	SLOW	132	I/O	O
uDw<0>	0	0	FB8	MC8	STD	SLOW	133	I/O	O
SYNCn	1	1	FB8	MC10	STD	SLOW	134	I/O	O	RESET
chip_comp/ReceiveCommandComp/sr<2>	1	2	FB6	MC2	STD		135	I/O	(b)	RESET
chip_comp/ReceiveCommandComp/sr<1>	1	2	FB6	MC3	STD		136	I/O	(b)	RESET
chip_comp/ReceiveCommandComp/sr<18>	1	2	FB6	MC5	STD		137	I/O	(b)	RESET
chip_comp/ReceiveCommandComp/sr<17>	1	2	FB6	MC6	STD		138	I/O	(b)	RESET
chip_comp/ReceiveCommandComp/sr<15>	1	2	FB6	MC8	STD		139	I/O	(b)	RESET
chip_comp/ReceiveCommandComp/sr<13>	1	2	FB6	MC10	STD		140	I/O	(b)	RESET
chip_comp/ReceiveCommandComp/sr<0>	1	2	FB6	MC14	STD		142	I/O	(b)	RESET
chip_comp/ReceiveCommandComp/clr_sr	1	4	FB6	MC15	STD		143	I/O/GSR	GSR/I	RESET
chip_comp/TCLKCounter<0>	2	14	FB1	MC1	STD			(b)	(b)	T	RESET
chip_comp/TCLKCounter<1>	3	14	FB1	MC2	STD			(b)	(b)	T	RESET
chip_comp/TCLKCounter<9>	4	14	FB1	MC3	STD			(b)	(b)	T	RESET
chip_comp/TCLKCounter<8>	5	14	FB1	MC4	STD			(b)	(b)	T	RESET
chip_comp/TCLKCounter<2>	5	14	FB1	MC7	STD			(b)	(b)	T	RESET
chip_comp/TCLKCounter<3>	6	14	FB1	MC9	STD			(b)	(b)	T	RESET
chip_comp/TCLKCounter<7>	7	14	FB1	MC11	STD			(b)	(b)	T	RESET
chip_comp/TCLKCounter<6>	7	14	FB1	MC13	STD			(b)	(b)	T	RESET
chip_comp/TCLKCounter<5>	7	14	FB1	MC16	STD			(b)	(b)	T	RESET
chip_comp/TCLKCounter<4>	7	14	FB1	MC18	STD			(b)	(b)	T	RESET
chip_comp/ACQENnB2Reg<3>	2	15	FB2	MC13	STD			(b)	(b)	D	RESET
chip_comp/ACQENnB1Reg<3>	2	15	FB2	MC16	STD			(b)	(b)	D	RESET
chip_comp/ACQENnB0Reg<3>	2	15	FB2	MC18	STD			(b)	(b)	D	RESET
chip_comp/TXMAINSTATE_FFd1	1	5	FB3	MC3	STD			(b)	(b)	D	RESET
chip_comp/TCLKsig_1	1	1	FB3	MC4	STD			(b)	(b)	D	RESET
chip_comp/SimulData<9>	1	1	FB3	MC5	STD			(b)	(b)	D	RESET
chip_comp/ADCRestCMD	1	3	FB3	MC6	STD			(b)	(b)	T	SET
chip_comp/ACLKCounter<2>	1	2	FB3	MC7	STD			(b)	(b)	T	RESET
chip_comp/ACLKCounter<1>	1	1	FB3	MC8	STD			(b)	(b)	T	RESET
chip_comp/TimerInterval<1>	2	10	FB3	MC9	STD			(b)	(b)	D	RESET
chip_comp/SamplingClock<1>	2	10	FB3	MC11	STD			(b)	(b)	D	RESET
chip_comp/ACLKCounter<7>	3	11	FB3	MC13	STD			(b)	(b)	T	RESET
chip_comp/ACLKCounter<3>	4	11	FB3	MC16	STD			(b)	(b)	T	RESET
chip_comp/ACLKCounter<4>	5	10	FB3	MC17	STD			(b)	(b)	T	RESET
chip_comp/ACLKCounter<5>	6	11	FB3	MC18	STD			(b)	(b)	T	RESET
chip_comp/CommandAvailable	1	4	FB4	MC4	STD			(b)	(b)	D	RESET
chip_comp/CommandReceived<5>	2	5	FB4	MC7	STD			(b)	(b)	D	RESET
chip_comp/CommandReceived<3>	2	5	FB4	MC9	STD			(b)	(b)	D	RESET
chip_comp/CommandReceived<2>	2	5	FB4	MC10	STD			(b)	(b)	D	RESET
chip_comp/CommandReceived<1>	2	5	FB4	MC11	STD			(b)	(b)	D	RESET
chip_comp/CommandReceived<14>	2	5	FB4	MC13	STD			(b)	(b)	D	RESET
chip_comp/CommandReceived<12>	2	5	FB4	MC15	STD			(b)	(b)	D	RESET
chip_comp/CommandReceived<11>	2	5	FB4	MC16	STD			(b)	(b)	D	RESET
chip_comp/CommandReceived<10>	2	5	FB4	MC17	STD			(b)	(b)	D	RESET
chip_comp/CommandReceived<0>	2	5	FB4	MC18	STD			(b)	(b)	D	RESET
chip_comp/Datasig<9>	15	17	FB5	MC1	STD			(b)	(b)	D	RESET
DATA_TSsig	4	4	FB5	MC9	STD			(b)	(b)	D	SET
chip_comp/Datasig<14>	6	12	FB5	MC11	STD			(b)	(b)	D	RESET
chip_comp/ACLKCounter<0>	0	0	FB5	MC13	STD			(b)	(b)	T	RESET
chip_comp/Datasig<12>	6	12	FB5	MC16	STD			(b)	(b)	D	RESET
chip_comp/ReceiveCommandComp/sr<3>	1	2	FB6	MC1	STD			(b)	(b)	D	RESET
chip_comp/ReceiveCommandComp/sr<19>	1	2	FB6	MC4	STD			(b)	(b)	D	RESET
chip_comp/ReceiveCommandComp/sr<16>	1	2	FB6	MC7	STD			(b)	(b)	D	RESET
chip_comp/ReceiveCommandComp/sr<14>	1	2	FB6	MC9	STD			(b)	(b)	D	RESET
chip_comp/ReceiveCommandComp/sr<12>	1	2	FB6	MC11	STD			(b)	(b)	D	RESET
chip_comp/ReceiveCommandComp/sr<11>	1	2	FB6	MC12	STD			(b)	(b)	D	RESET
chip_comp/ReceiveCommandComp/sr<10>	1	2	FB6	MC13	STD			(b)	(b)	D	RESET
chip_comp/CommandReceived<9>	2	5	FB6	MC16	STD			(b)	(b)	D	RESET
chip_comp/CommandReceived<8>	2	5	FB6	MC17	STD			(b)	(b)	D	RESET
chip_comp/CommandReceived<7>	2	5	FB6	MC18	STD			(b)	(b)	D	RESET
chip_comp/Datasig<10>	6	12	FB7	MC2	STD			(b)	(b)	D	RESET
chip_comp/Datasig<5>	16	18	FB7	MC7	STD			(b)	(b)	D	RESET
chip_comp/Datasig<7>	16	18	FB7	MC11	STD			(b)	(b)	D	RESET
chip_comp/Datasig<8>	16	18	FB7	MC17	STD			(b)	(b)	D	RESET
chip_comp/SimulData<7>	1	1	FB8	MC1	STD			(b)	(b)	D	RESET
chip_comp/SimulData<14>	1	1	FB8	MC4	STD			(b)	(b)	D	RESET
chip_comp/TXMAINSTATE_FFd2	2	3	FB8	MC6	STD			(b)	(b)	D	RESET
chip_comp/LinkStablished	2	3	FB8	MC7	STD			(b)	(b)	D	RESET
chip_comp/GenDataCounter<6>	2	8	FB8	MC9	STD			(b)	(b)	T	RESET
chip_comp/GenDataCounter<5>	2	7	FB8	MC11	STD			(b)	(b)	T	RESET
chip_comp/GenDataCounter<4>	2	6	FB8	MC12	STD			(b)	(b)	T	RESET
chip_comp/GenDataCounter<3>	2	5	FB8	MC13	STD			(b)	(b)	T	RESET
chip_comp/GenDataCounter<2>	2	4	FB8	MC14	STD			(b)	(b)	T	RESET
chip_comp/GenDataCounter<1>	2	3	FB8	MC15	STD			(b)	(b)	D	RESET
chip_comp/TXREADOUTSTATE_FFd1	3	6	FB8	MC16	STD			(b)	(b)	T	RESET
chip_comp/TXREADOUTSTATE_FFd3	6	9	FB8	MC17	STD			(b)	(b)	D	RESET
chip_comp/Datasig<13>	10	12	FB8	MC18	STD			(b)	(b)	D	RESET
chip_comp/TXREADOUTSTATE_FFd4	12	12	FB9	MC1	STD			(b)	(b)	D	RESET
chip_comp/GenDatasig	5	8	FB9	MC7	STD			(b)	(b)	D	RESET
chip_comp/Datasig<15>	10	11	FB9	MC10	STD			(b)	(b)	D	RESET
chip_comp/TXREADOUTSTATE_FFd2	7	12	FB9	MC13	STD			(b)	(b)	D	RESET
chip_comp/Datasig<11>	10	12	FB9	MC16	STD			(b)	(b)	D	RESET
chip_comp/SimulData<0>	1	1	FB10	MC1	STD			(b)	(b)	D	RESET
chip_comp/ReceiveCommandComp/sr<7>	1	2	FB10	MC4	STD			(b)	(b)	D	RESET
chip_comp/ReceiveCommandComp/sr<6>	1	2	FB10	MC7	STD			(b)	(b)	D	RESET
chip_comp/ReceiveCommandComp/sr<5>	1	2	FB10	MC9	STD			(b)	(b)	D	RESET
chip_comp/ReceiveCommandComp/sr<4>	1	2	FB10	MC13	STD			(b)	(b)	D	RESET
chip_comp/ReceiveCommandComp/sr<20>	1	2	FB10	MC15	STD			(b)	(b)	D	RESET
chip_comp/GenDataCounter<0>	1	2	FB10	MC16	STD			(b)	(b)	D	RESET
chip_comp/ACLKsig_1	1	1	FB10	MC18	STD			(b)	(b)	D	RESET
chip_comp/Datasig<0>	18	21	FB11	MC1	STD			(b)	(b)	D	RESET
chip_comp/Datasig<4>	8	17	FB11	MC4	STD			(b)	(b)	D	RESET
chip_comp/Datasig<2>	18	21	FB11	MC15	STD			(b)	(b)	D	RESET
chip_comp/SimulData<8>	1	1	FB12	MC7	STD			(b)	(b)	D	RESET
chip_comp/SimulData<5>	1	1	FB12	MC9	STD			(b)	(b)	D	RESET
chip_comp/SimulData<3>	1	1	FB12	MC11	STD			(b)	(b)	D	RESET
chip_comp/SimulData<1>	1	1	FB12	MC13	STD			(b)	(b)	D	RESET
chip_comp/SimulData<15>	1	1	FB12	MC14	STD			(b)	(b)	D	RESET
chip_comp/SimulData<13>	1	1	FB12	MC15	STD			(b)	(b)	D	RESET
chip_comp/SimulData<12>	1	1	FB12	MC16	STD			(b)	(b)	D	RESET
chip_comp/SimulData<11>	1	1	FB12	MC17	STD			(b)	(b)	D	RESET
chip_comp/SimulData<10>	1	1	FB12	MC18	STD			(b)	(b)	D	RESET
chip_comp/Datasig<6>	16	18	FB13	MC4	STD			(b)	(b)	D	RESET
chip_comp/Datasig<3>	17	21	FB13	MC13	STD			(b)	(b)	D	RESET
chip_comp/Datasig<1>	17	21	FB13	MC18	STD			(b)	(b)	D	RESET
chip_comp/TimerRestCMD	2	11	FB14	MC1	STD			(b)	(b)	T	SET
chip_comp/TimerInterval<2>	2	10	FB14	MC2	STD			(b)	(b)	D	RESET
chip_comp/TimerInterval<0>	2	10	FB14	MC4	STD			(b)	(b)	D	RESET
chip_comp/StatusDataSel<2>	2	10	FB14	MC7	STD			(b)	(b)	D	RESET
chip_comp/SamplingClock<0>	2	10	FB14	MC9	STD			(b)	(b)	D	RESET
chip_comp/ENABLEn_BReg<3>	2	15	FB14	MC12	STD			(b)	(b)	D	RESET
chip_comp/ENABLEn_BReg<2>	2	15	FB14	MC13	STD			(b)	(b)	D	RESET
chip_comp/ACQENnB3Reg<3>	2	15	FB14	MC16	STD			(b)	(b)	D	RESET
chip_comp/ACQENnB3Reg<2>	2	15	FB14	MC17	STD			(b)	(b)	D	RESET
chip_comp/RunningFlag	3	10	FB14	MC18	STD			(b)	(b)	T	RESET
chip_comp/GenDataDonesig	1	16	FB15	MC1	STD			(b)	(b)	D	RESET
chip_comp/GenDataCounter<9>	2	11	FB15	MC4	STD			(b)	(b)	T	RESET
chip_comp/GenDataCounter<8>	2	10	FB15	MC5	STD			(b)	(b)	T	RESET
chip_comp/GenDataCounter<7>	2	9	FB15	MC6	STD			(b)	(b)	T	RESET
chip_comp/GenDataCounter<15>	2	17	FB15	MC7	STD			(b)	(b)	T	RESET
chip_comp/GenDataCounter<14>	2	16	FB15	MC9	STD			(b)	(b)	T	RESET
chip_comp/GenDataCounter<12>	2	14	FB15	MC13	STD			(b)	(b)	T	RESET
chip_comp/GenDataCounter<11>	2	13	FB15	MC16	STD			(b)	(b)	T	RESET
chip_comp/GenDataCounter<10>	2	12	FB15	MC18	STD			(b)	(b)	T	RESET
chip_comp/ENABLEn_BReg<1>	2	15	FB16	MC1	STD			(b)	(b)	D	RESET
chip_comp/ACQENnB3Reg<0>	2	15	FB16	MC4	STD			(b)	(b)	D	RESET
chip_comp/ACQENnB2Reg<1>	2	15	FB16	MC7	STD			(b)	(b)	D	RESET
chip_comp/ACQENnB2Reg<0>	2	15	FB16	MC9	STD			(b)	(b)	D	RESET
chip_comp/ACQENnB1Reg<2>	2	15	FB16	MC13	STD			(b)	(b)	D	RESET
chip_comp/ACQENnB1Reg<1>	2	15	FB16	MC14	STD			(b)	(b)	D	RESET
chip_comp/ACQENnB1Reg<0>	2	15	FB16	MC15	STD			(b)	(b)	D	RESET
chip_comp/ACQENnB0Reg<2>	2	15	FB16	MC16	STD			(b)	(b)	D	RESET
chip_comp/ACQENnB0Reg<1>	2	15	FB16	MC17	STD			(b)	(b)	D	RESET
chip_comp/ACQENnB0Reg<0>	2	15	FB16	MC18	STD			(b)	(b)	D	RESET