FB1
FB2
FB3
FB4
FB5
FB6
FB7
FB8
FB9
FB10
FB11
FB12
FB13
FB14
FB15
FB16
Signal Name
Total Product Terms
Product Terms
Location
Power Mode
Pin Number
PinType
Pin Use
chip_comp/TXREADOUTSTATE_FFd4
12
17_2
17_3
17_4
17_5
18_1
18_2
18_3
18_4
18_5
1_1
1_2
1_3
MC1
STD
(b)
(b)
DATA<6>
6
1_4
1_5
2_1
2_2
2_3
2_4
MC2
STD
50
I/O
O
DATA<5>
6
2_5
3_1
3_2
3_3
3_4
3_5
MC3
STD
51
I/O
O
(unused)
0
MC4
(b)
(b)
DATA<4>
6
4_1
4_2
4_3
5_1
5_2
5_3
MC5
STD
52
I/O
O
DATA<3>
6
5_4
5_5
6_1
6_2
6_3
6_4
MC6
STD
53
I/O
O
chip_comp/GenDatasig
5
6_5
7_1
7_2
7_3
7_4
MC7
STD
(b)
(b)
DATA<2>
6
7_5
8_1
8_2
8_3
8_4
8_5
MC8
STD
54
I/O
O
(unused)
0
MC9
(b)
(b)
chip_comp/Datasig<15>
10
10_1
10_2
10_3
10_4
10_5
9_1
9_2
9_3
9_4
9_5
MC10
STD
(b)
(b)
DATA<1>
6
11_1
11_2
11_3
11_4
11_5
12_5
MC11
STD
56
I/O
O
DATA<0>
6
12_1
12_2
12_3
12_4
13_4
13_5
MC12
STD
57
I/O
O
chip_comp/TXREADOUTSTATE_FFd2
7
13_1
13_2
13_3
14_2
14_3
14_4
14_5
MC13
STD
(b)
(b)
RST4n_B<0>
1
14_1
MC14
STD
58
I/O
O
(unused)
0
MC15
(b)
(b)
chip_comp/Datasig<11>
10
15_1
15_2
15_3
15_4
15_5
16_1
16_2
16_3
16_4
16_5
MC16
STD
(b)
(b)
D_OEn_B<0>
1
17_1
MC17
STD
59
I/O
O
(unused)
0
MC18
(b)
(b)
Signals Used By Logic in Function Block
DATA_TSsig
HFn_B<0>
HFn_B<1>
HFn_B<2>
HFn_B<3>
RST4n_B<0>
chip_comp/DataPackageTXEn
chip_comp/Datasig<0>
chip_comp/Datasig<11>
chip_comp/Datasig<15>
chip_comp/Datasig<1>
chip_comp/Datasig<2>
chip_comp/Datasig<3>
chip_comp/Datasig<4>
chip_comp/Datasig<5>
chip_comp/Datasig<6>
chip_comp/GenDataCMD
chip_comp/GenDataDonesig
chip_comp/LinkStablished
chip_comp/SimulData<0>
chip_comp/SimulData<1>
chip_comp/SimulData<2>
chip_comp/SimulData<3>
chip_comp/SimulData<4>
chip_comp/SimulData<5>
chip_comp/SimulData<6>
chip_comp/StatusDataSel<1>
chip_comp/TXREADOUTSTATE_FFd1
chip_comp/TXREADOUTSTATE_FFd2
chip_comp/TXREADOUTSTATE_FFd3
chip_comp/TXREADOUTSTATE_FFd4