Equations

********** Mapped Logic **********

FTCPE_ACLK: FTCPE port map (ACLK,'1',CLK_40MHZ,POR,'0',ACLK_CE);
     ACLK_CE <= (NOT chip_comp/ACLKCounter(0) AND
      NOT chip_comp/ACLKCounter(1) AND NOT chip_comp/ACLKCounter(2) AND
      NOT chip_comp/ACLKCounter(3) AND NOT chip_comp/ACLKCounter(4) AND
      NOT chip_comp/ACLKCounter(5) AND NOT chip_comp/ACLKCounter(6) AND
      NOT chip_comp/ACLKCounter(7) AND NOT chip_comp/ACLKCounter(8));

FDCPE_ACQENnB00: FDCPE port map (ACQENnB0(0),ACQENnB0_D(0),CLK_40MHZ,'0',POR);
ACQENnB0_D(0) <= (chip_comp/RunningFlag AND chip_comp/ACQENnB0Reg(0));

FDCPE_ACQENnB01: FDCPE port map (ACQENnB0(1),ACQENnB0_D(1),CLK_40MHZ,'0',POR);
ACQENnB0_D(1) <= (chip_comp/RunningFlag AND chip_comp/ACQENnB0Reg(1));

FDCPE_ACQENnB02: FDCPE port map (ACQENnB0(2),ACQENnB0_D(2),CLK_40MHZ,'0',POR);
ACQENnB0_D(2) <= (chip_comp/RunningFlag AND chip_comp/ACQENnB0Reg(2));

FDCPE_ACQENnB03: FDCPE port map (ACQENnB0(3),ACQENnB0_D(3),CLK_40MHZ,'0',POR);
ACQENnB0_D(3) <= (chip_comp/RunningFlag AND chip_comp/ACQENnB0Reg(3));

FDCPE_ACQENnB10: FDCPE port map (ACQENnB1(0),ACQENnB1_D(0),CLK_40MHZ,'0',POR);
ACQENnB1_D(0) <= (chip_comp/RunningFlag AND chip_comp/ACQENnB1Reg(0));

FDCPE_ACQENnB11: FDCPE port map (ACQENnB1(1),ACQENnB1_D(1),CLK_40MHZ,'0',POR);
ACQENnB1_D(1) <= (chip_comp/RunningFlag AND chip_comp/ACQENnB1Reg(1));

FDCPE_ACQENnB12: FDCPE port map (ACQENnB1(2),ACQENnB1_D(2),CLK_40MHZ,'0',POR);
ACQENnB1_D(2) <= (chip_comp/RunningFlag AND chip_comp/ACQENnB1Reg(2));

FDCPE_ACQENnB13: FDCPE port map (ACQENnB1(3),ACQENnB1_D(3),CLK_40MHZ,'0',POR);
ACQENnB1_D(3) <= (chip_comp/RunningFlag AND chip_comp/ACQENnB1Reg(3));

FDCPE_ACQENnB20: FDCPE port map (ACQENnB2(0),EXP19_.EXP,CLK_40MHZ,'0',POR);

FDCPE_ACQENnB21: FDCPE port map (ACQENnB2(1),ACQENnB2_D(1),CLK_40MHZ,'0',POR);
ACQENnB2_D(1) <= (chip_comp/RunningFlag AND chip_comp/ACQENnB2Reg(1));

FDCPE_ACQENnB22: FDCPE port map (ACQENnB2(2),ACQENnB2_D(2),CLK_40MHZ,'0',POR);
ACQENnB2_D(2) <= (chip_comp/RunningFlag AND chip_comp/ACQENnB2Reg(2));

FDCPE_ACQENnB23: FDCPE port map (ACQENnB2(3),ACQENnB2_D(3),CLK_40MHZ,'0',POR);
ACQENnB2_D(3) <= (chip_comp/RunningFlag AND chip_comp/ACQENnB2Reg(3));

FDCPE_ACQENnB30: FDCPE port map (ACQENnB3(0),ACQENnB3_D(0),CLK_40MHZ,'0',POR);
ACQENnB3_D(0) <= (chip_comp/RunningFlag AND chip_comp/ACQENnB3Reg(0));

FDCPE_ACQENnB31: FDCPE port map (ACQENnB3(1),ACQENnB3_D(1),CLK_40MHZ,'0',POR);
ACQENnB3_D(1) <= (chip_comp/RunningFlag AND chip_comp/ACQENnB3Reg(1));

FDCPE_ACQENnB32: FDCPE port map (ACQENnB3(2),ACQENnB3_D(2),CLK_40MHZ,'0',POR);
ACQENnB3_D(2) <= (chip_comp/RunningFlag AND chip_comp/ACQENnB3Reg(2));

FDCPE_ACQENnB33: FDCPE port map (ACQENnB3(3),ACQENnB3_D(3),CLK_40MHZ,'0',POR);
ACQENnB3_D(3) <= (chip_comp/RunningFlag AND chip_comp/ACQENnB3Reg(3));

FDCPE_ADCRST: FDCPE port map (ADCRST,ADCRST_D,CLK_40MHZ,'0',POR);
     ADCRST_D <= ((NOT ADCRST AND NOT chip_comp/ADCRestCMD)
      OR (ACLK AND NOT chip_comp/ADCRestCMD AND
      NOT chip_comp/ACLKsig_1));

DAC_CSn_B(0) <= '1';

DAC_CSn_B(1) <= '1';

DAC_CSn_B(2) <= '1';

DAC_CSn_B(3) <= '1';

DAC_DIN <= '0';

DAC_LOADn <= DAC_DINsig$BUF9.EXP;

DAC_SCLK <= EXP45_.EXP;

DATA_I(0) <= ((chip_comp/TXREADOUTSTATE_FFd2.EXP)
      OR (chip_comp/TXREADOUTSTATE_FFd3 AND
      chip_comp/Datasig(0))
      OR (NOT chip_comp/TXREADOUTSTATE_FFd4 AND
      chip_comp/Datasig(0))
      OR (chip_comp/TXREADOUTSTATE_FFd2 AND
      chip_comp/Datasig(0)));
     DATA(0) <= DATA_I(0) when DATA_OE(0) = '1' else 'Z';
     DATA_OE(0) <= NOT DATA_TSsig;

DATA_I(1) <= ((Datasig(0).EXP)
      OR (chip_comp/TXREADOUTSTATE_FFd3 AND
      chip_comp/Datasig(1))
      OR (NOT chip_comp/TXREADOUTSTATE_FFd4 AND
      chip_comp/Datasig(1))
      OR (chip_comp/TXREADOUTSTATE_FFd2 AND
      chip_comp/Datasig(1))
      OR (chip_comp/TXREADOUTSTATE_FFd1 AND
      chip_comp/Datasig(1)));
     DATA(1) <= DATA_I(1) when DATA_OE(1) = '1' else 'Z';
     DATA_OE(1) <= NOT DATA_TSsig;

DATA_I(2) <= ((chip_comp/GenDatasig.EXP)
      OR (chip_comp/TXREADOUTSTATE_FFd3 AND
      chip_comp/Datasig(2))
      OR (NOT chip_comp/TXREADOUTSTATE_FFd4 AND
      chip_comp/Datasig(2))
      OR (chip_comp/TXREADOUTSTATE_FFd2 AND
      chip_comp/Datasig(2))
      OR (chip_comp/TXREADOUTSTATE_FFd1 AND
      chip_comp/Datasig(2)));
     DATA(2) <= DATA_I(2) when DATA_OE(2) = '1' else 'Z';
     DATA_OE(2) <= NOT DATA_TSsig;

DATA_I(3) <= ((Datasig(4).EXP)
      OR (chip_comp/TXREADOUTSTATE_FFd3 AND
      chip_comp/Datasig(3))
      OR (NOT chip_comp/TXREADOUTSTATE_FFd4 AND
      chip_comp/Datasig(3))
      OR (chip_comp/TXREADOUTSTATE_FFd2 AND
      chip_comp/Datasig(3)));
     DATA(3) <= DATA_I(3) when DATA_OE(3) = '1' else 'Z';
     DATA_OE(3) <= NOT DATA_TSsig;

DATA_I(4) <= ((EXP32_.EXP)
      OR (chip_comp/TXREADOUTSTATE_FFd3 AND
      chip_comp/Datasig(4))
      OR (NOT chip_comp/TXREADOUTSTATE_FFd4 AND
      chip_comp/Datasig(4)));
     DATA(4) <= DATA_I(4) when DATA_OE(4) = '1' else 'Z';
     DATA_OE(4) <= NOT DATA_TSsig;

DATA_I(5) <= ((Datasig(6).EXP)
      OR (chip_comp/TXREADOUTSTATE_FFd3 AND
      chip_comp/Datasig(5))
      OR (NOT chip_comp/TXREADOUTSTATE_FFd4 AND
      chip_comp/Datasig(5))
      OR (chip_comp/TXREADOUTSTATE_FFd2 AND
      chip_comp/Datasig(5))
      OR (chip_comp/TXREADOUTSTATE_FFd1 AND
      chip_comp/Datasig(5)));
     DATA(5) <= DATA_I(5) when DATA_OE(5) = '1' else 'Z';
     DATA_OE(5) <= NOT DATA_TSsig;

DATA_I(6) <= ((chip_comp/TXREADOUTSTATE_FFd4.EXP)
      OR (chip_comp/TXREADOUTSTATE_FFd3 AND
      chip_comp/Datasig(6))
      OR (NOT chip_comp/TXREADOUTSTATE_FFd4 AND
      chip_comp/Datasig(6))
      OR (chip_comp/TXREADOUTSTATE_FFd2 AND
      chip_comp/Datasig(6)));
     DATA(6) <= DATA_I(6) when DATA_OE(6) = '1' else 'Z';
     DATA_OE(6) <= NOT DATA_TSsig;

DATA_I(7) <= ((EXP29_.EXP)
      OR (chip_comp/TXREADOUTSTATE_FFd3 AND
      chip_comp/Datasig(7))
      OR (NOT chip_comp/TXREADOUTSTATE_FFd4 AND
      chip_comp/Datasig(7))
      OR (chip_comp/TXREADOUTSTATE_FFd2 AND
      chip_comp/Datasig(7)));
     DATA(7) <= DATA_I(7) when DATA_OE(7) = '1' else 'Z';
     DATA_OE(7) <= NOT DATA_TSsig;

DATA_I(8) <= ((EXP28_.EXP)
      OR (chip_comp/TXREADOUTSTATE_FFd3 AND
      chip_comp/Datasig(8)));
     DATA(8) <= DATA_I(8) when DATA_OE(8) = '1' else 'Z';
     DATA_OE(8) <= NOT DATA_TSsig;

DATA_I(9) <= ((EXP23_.EXP)
      OR (chip_comp/TXREADOUTSTATE_FFd3 AND
      chip_comp/Datasig(9))
      OR (NOT chip_comp/TXREADOUTSTATE_FFd4 AND
      chip_comp/Datasig(9))
      OR (chip_comp/TXREADOUTSTATE_FFd2 AND
      chip_comp/Datasig(9)));
     DATA(9) <= DATA_I(9) when DATA_OE(9) = '1' else 'Z';
     DATA_OE(9) <= NOT DATA_TSsig;

DATA_I(10) <= ((chip_comp/Datasig(10).EXP)
      OR (chip_comp/TXREADOUTSTATE_FFd3 AND
      chip_comp/Datasig(10))
      OR (NOT chip_comp/TXREADOUTSTATE_FFd4 AND
      chip_comp/Datasig(10))
      OR (chip_comp/TXREADOUTSTATE_FFd2 AND
      chip_comp/Datasig(10))
      OR (chip_comp/TXREADOUTSTATE_FFd1 AND
      chip_comp/Datasig(10)));
     DATA(10) <= DATA_I(10) when DATA_OE(10) = '1' else 'Z';
     DATA_OE(10) <= NOT DATA_TSsig;

DATA_I(11) <= ((chip_comp/Datasig(12).EXP)
      OR (chip_comp/TXREADOUTSTATE_FFd3 AND
      chip_comp/Datasig(11))
      OR (NOT chip_comp/TXREADOUTSTATE_FFd4 AND
      chip_comp/Datasig(11))
      OR (chip_comp/TXREADOUTSTATE_FFd2 AND
      chip_comp/Datasig(11))
      OR (chip_comp/TXREADOUTSTATE_FFd1 AND
      chip_comp/Datasig(11)));
     DATA(11) <= DATA_I(11) when DATA_OE(11) = '1' else 'Z';
     DATA_OE(11) <= NOT DATA_TSsig;

DATA_I(12) <= ((Datasig(13).EXP)
      OR (chip_comp/TXREADOUTSTATE_FFd3 AND
      chip_comp/Datasig(12))
      OR (NOT chip_comp/TXREADOUTSTATE_FFd4 AND
      chip_comp/Datasig(12)));
     DATA(12) <= DATA_I(12) when DATA_OE(12) = '1' else 'Z';
     DATA_OE(12) <= NOT DATA_TSsig;

DATA_I(13) <= ((chip_comp/ACLKCounter(0).EXP)
      OR (chip_comp/TXREADOUTSTATE_FFd3 AND
      chip_comp/Datasig(13)));
     DATA(13) <= DATA_I(13) when DATA_OE(13) = '1' else 'Z';
     DATA_OE(13) <= NOT DATA_TSsig;

DATA_I(14) <= ((chip_comp/Datasig(14).EXP)
      OR (chip_comp/TXREADOUTSTATE_FFd3 AND
      chip_comp/Datasig(14))
      OR (NOT chip_comp/TXREADOUTSTATE_FFd4 AND
      chip_comp/Datasig(14))
      OR (chip_comp/TXREADOUTSTATE_FFd2 AND
      chip_comp/Datasig(14))
      OR (chip_comp/TXREADOUTSTATE_FFd1 AND
      chip_comp/Datasig(14)));
     DATA(14) <= DATA_I(14) when DATA_OE(14) = '1' else 'Z';
     DATA_OE(14) <= NOT DATA_TSsig;

DATA_I(15) <= ((DATA_TSsig.EXP)
      OR (chip_comp/TXREADOUTSTATE_FFd3 AND
      chip_comp/Datasig(15))
      OR (NOT chip_comp/TXREADOUTSTATE_FFd4 AND
      chip_comp/Datasig(15)));
     DATA(15) <= DATA_I(15) when DATA_OE(15) = '1' else 'Z';
     DATA_OE(15) <= NOT DATA_TSsig;

FDCPE_DATA_TSsig: FDCPE port map (DATA_TSsig,DATA_TSsig_D,CLK_40MHZ,'0',POR);
     DATA_TSsig_D <= ((EXP20_.EXP)
      OR (NOT chip_comp/TXREADOUTSTATE_FFd2 AND
      NOT chip_comp/TXREADOUTSTATE_FFd1)
      OR (NOT chip_comp/TXREADOUTSTATE_FFd3 AND
      chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd1));

FDCPE_DR0: FDCPE port map (DR0,chip_comp/CommandReceived(0),CLK_40MHZ,POR,'0',DR0_CE);
     DR0_CE <= (NOT chip_comp/CommandReceived(10) AND
      NOT chip_comp/CommandReceived(13) AND NOT chip_comp/CommandReceived(14) AND
      chip_comp/CommandReceived(9) AND chip_comp/CommandReceived(11) AND
      NOT chip_comp/CommandReceived(12) AND NOT chip_comp/CommandReceived(15) AND
      NOT chip_comp/CommandReceived(8) AND chip_comp/TXMAINSTATE_FFd1);

FDCPE_DR1: FDCPE port map (DR1,chip_comp/CommandReceived(1),CLK_40MHZ,POR,'0',DR1_CE);
     DR1_CE <= (NOT chip_comp/CommandReceived(10) AND
      NOT chip_comp/CommandReceived(13) AND NOT chip_comp/CommandReceived(14) AND
      chip_comp/CommandReceived(9) AND chip_comp/CommandReceived(11) AND
      NOT chip_comp/CommandReceived(12) AND NOT chip_comp/CommandReceived(15) AND
      NOT chip_comp/CommandReceived(8) AND chip_comp/TXMAINSTATE_FFd1);

FDCPE_D_OEn_B0: FDCPE port map (D_OEn_B(0),D_OEn_B_D(0),CLK_40MHZ,'0',POR);
     D_OEn_B_D(0) <= (NOT chip_comp/TXREADOUTSTATE_FFd3 AND
      NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND
      NOT chip_comp/TXREADOUTSTATE_FFd1);

FDCPE_D_OEn_B1: FDCPE port map (D_OEn_B(1),D_OEn_B_D(1),CLK_40MHZ,'0',POR);
     D_OEn_B_D(1) <= (chip_comp/TXREADOUTSTATE_FFd3 AND
      chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND
      NOT chip_comp/TXREADOUTSTATE_FFd1);

FDCPE_D_OEn_B2: FDCPE port map (D_OEn_B(2),EXP37_.EXP,CLK_40MHZ,'0',POR);

FDCPE_D_OEn_B3: FDCPE port map (D_OEn_B(3),D_OEn_B_D(3),CLK_40MHZ,'0',POR);
     D_OEn_B_D(3) <= (chip_comp/TXREADOUTSTATE_FFd3 AND
      NOT chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND
      chip_comp/TXREADOUTSTATE_FFd1);

FDCPE_ENABLEn_B0: FDCPE port map (ENABLEn_B(0),ENABLEn_B_D(0),CLK_40MHZ,'0',POR);
ENABLEn_B_D(0) <= (chip_comp/RunningFlag AND chip_comp/ENABLEn_BReg(0));

FDCPE_ENABLEn_B1: FDCPE port map (ENABLEn_B(1),ENABLEn_B_D(1),CLK_40MHZ,'0',POR);
ENABLEn_B_D(1) <= (chip_comp/RunningFlag AND chip_comp/ENABLEn_BReg(1));

FDCPE_ENABLEn_B2: FDCPE port map (ENABLEn_B(2),ENABLEn_B_D(2),CLK_40MHZ,'0',POR);
ENABLEn_B_D(2) <= (chip_comp/RunningFlag AND chip_comp/ENABLEn_BReg(2));

FDCPE_ENABLEn_B3: FDCPE port map (ENABLEn_B(3),ENABLEn_B_D(3),CLK_40MHZ,'0',POR);
ENABLEn_B_D(3) <= (chip_comp/RunningFlag AND chip_comp/ENABLEn_BReg(3));

FDCPE_PT0: FDCPE port map (PT0,chip_comp/CommandReceived(0),CLK_40MHZ,POR,'0',PT0_CE);
     PT0_CE <= (NOT chip_comp/CommandReceived(10) AND
      NOT chip_comp/CommandReceived(13) AND NOT chip_comp/CommandReceived(14) AND
      chip_comp/CommandReceived(9) AND chip_comp/CommandReceived(11) AND
      NOT chip_comp/CommandReceived(12) AND NOT chip_comp/CommandReceived(15) AND
      chip_comp/CommandReceived(8) AND chip_comp/TXMAINSTATE_FFd1);

FDCPE_PT1: FDCPE port map (PT1,chip_comp/CommandReceived(1),CLK_40MHZ,POR,'0',PT1_CE);
     PT1_CE <= (NOT chip_comp/CommandReceived(10) AND
      NOT chip_comp/CommandReceived(13) AND NOT chip_comp/CommandReceived(14) AND
      chip_comp/CommandReceived(9) AND chip_comp/CommandReceived(11) AND
      NOT chip_comp/CommandReceived(12) AND NOT chip_comp/CommandReceived(15) AND
      chip_comp/CommandReceived(8) AND chip_comp/TXMAINSTATE_FFd1);

RCLK3 <= CLK_40MHZ;

RCLK4_B(0) <= NOT ((NOT CLK_40MHZ AND chip_comp/TXREADOUTSTATE_FFd3 AND
chip_comp/TXREADOUTSTATE_FFd1));

RCLK4_B(1) <= NOT ((NOT CLK_40MHZ AND chip_comp/TXREADOUTSTATE_FFd3 AND
chip_comp/TXREADOUTSTATE_FFd1));

RCLK4_B(2) <= NOT ((NOT CLK_40MHZ AND chip_comp/TXREADOUTSTATE_FFd3 AND
chip_comp/TXREADOUTSTATE_FFd1));

RCLK4_B(3) <= NOT ((NOT CLK_40MHZ AND chip_comp/TXREADOUTSTATE_FFd3 AND
chip_comp/TXREADOUTSTATE_FFd1));

RESETn <= NOT POR;

FTCPE_RST4n_B0: FTCPE port map (RST4n_B(0),RST4n_B_T(0),CLK_40MHZ,POR,'0');
     RST4n_B_T(0) <= (NOT RST4n_B(0) AND NOT chip_comp/TXREADOUTSTATE_FFd3 AND
      NOT chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND
      NOT chip_comp/TXREADOUTSTATE_FFd1);

FTCPE_RST4n_B1: FTCPE port map (RST4n_B(1),RST4n_B_T(1),CLK_40MHZ,POR,'0');
     RST4n_B_T(1) <= (NOT RST4n_B(1) AND NOT chip_comp/TXREADOUTSTATE_FFd3 AND
      NOT chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND
      NOT chip_comp/TXREADOUTSTATE_FFd1);

FTCPE_RST4n_B2: FTCPE port map (RST4n_B(2),RST4n_B_T(2),CLK_40MHZ,POR,'0');
     RST4n_B_T(2) <= (NOT RST4n_B(2) AND NOT chip_comp/TXREADOUTSTATE_FFd3 AND
      NOT chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND
      NOT chip_comp/TXREADOUTSTATE_FFd1);

FTCPE_RST4n_B3: FTCPE port map (RST4n_B(3),RST4n_B_T(3),CLK_40MHZ,POR,'0');
     RST4n_B_T(3) <= (NOT RST4n_B(3) AND NOT chip_comp/TXREADOUTSTATE_FFd3 AND
      NOT chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND
      NOT chip_comp/TXREADOUTSTATE_FFd1);

FDCPE_RST_TIMERn: FDCPE port map (RST_TIMERn,RST_TIMERn_D,CLK_40MHZ,POR,'0');
     RST_TIMERn_D <= ((NOT chip_comp/TimerRestCMD AND RST_TIMERn)
      OR (TCLK AND NOT chip_comp/TimerRestCMD AND
      NOT chip_comp/TCLKsig_1));

FDCPE_SYNCn: FDCPE port map (SYNCn,NOT chip_comp/TXMAINSTATE_FFd2,CLK_40MHZ,POR,'0');

SYSCLK <= CLK_40MHZ;

FTCPE_TCLK: FTCPE port map (TCLK,'1',CLK_40MHZ,POR,'0',TCLK_CE);
     TCLK_CE <= (NOT chip_comp/TCLKCounter(0) AND
      NOT chip_comp/TCLKCounter(1) AND NOT chip_comp/TCLKCounter(2) AND
      NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND
      NOT chip_comp/TCLKCounter(5) AND NOT chip_comp/TCLKCounter(6) AND
      NOT chip_comp/TCLKCounter(7) AND NOT chip_comp/TCLKCounter(8) AND
      NOT chip_comp/TCLKCounter(9) AND NOT chip_comp/TCLKCounter(10));

FDCPE_TMODE: FDCPE port map (TMODE,chip_comp/CommandReceived(0),CLK_40MHZ,POR,'0',TMODE_CE);
     TMODE_CE <= (chip_comp/CommandReceived(10) AND
      NOT chip_comp/CommandReceived(13) AND NOT chip_comp/CommandReceived(14) AND
      NOT chip_comp/CommandReceived(9) AND chip_comp/CommandReceived(11) AND
      NOT chip_comp/CommandReceived(12) AND NOT chip_comp/CommandReceived(15) AND
      chip_comp/CommandReceived(8) AND chip_comp/TXMAINSTATE_FFd1);

FTCPE_chip_comp/ACLKCounter0: FTCPE port map (chip_comp/ACLKCounter(0),'1',CLK_40MHZ,POR,'0');

FTCPE_chip_comp/ACLKCounter1: FTCPE port map (chip_comp/ACLKCounter(1),chip_comp/ACLKCounter(0),CLK_40MHZ,POR,'0');

FTCPE_chip_comp/ACLKCounter2: FTCPE port map (chip_comp/ACLKCounter(2),chip_comp/ACLKCounter_T(2),CLK_40MHZ,POR,'0');
chip_comp/ACLKCounter_T(2) <= (NOT chip_comp/ACLKCounter(0) AND
NOT chip_comp/ACLKCounter(1));

FTCPE_chip_comp/ACLKCounter3: FTCPE port map (chip_comp/ACLKCounter(3),chip_comp/ACLKCounter_T(3),CLK_40MHZ,POR,'0');
     chip_comp/ACLKCounter_T(3) <= ((chip_comp/ACLKCounter(0))
      OR (chip_comp/ACLKCounter(1))
      OR (chip_comp/ACLKCounter(2))
      OR (NOT chip_comp/SamplingClock(1) AND
      NOT chip_comp/SamplingClock(0) AND NOT chip_comp/ACLKCounter(3) AND
      NOT chip_comp/ACLKCounter(4) AND NOT chip_comp/ACLKCounter(5) AND
      NOT chip_comp/ACLKCounter(6) AND NOT chip_comp/ACLKCounter(7) AND
      NOT chip_comp/ACLKCounter(8)));

FTCPE_chip_comp/ACLKCounter4: FTCPE port map (chip_comp/ACLKCounter(4),chip_comp/ACLKCounter_T(4),CLK_40MHZ,POR,'0');
     chip_comp/ACLKCounter_T(4) <= ((chip_comp/ACLKCounter(0))
      OR (chip_comp/ACLKCounter(1))
      OR (chip_comp/ACLKCounter(2))
      OR (chip_comp/ACLKCounter(3))
      OR (NOT chip_comp/SamplingClock(1) AND
      NOT chip_comp/ACLKCounter(4) AND NOT chip_comp/ACLKCounter(5) AND
      NOT chip_comp/ACLKCounter(6) AND NOT chip_comp/ACLKCounter(7) AND
      NOT chip_comp/ACLKCounter(8)));

FTCPE_chip_comp/ACLKCounter5: FTCPE port map (chip_comp/ACLKCounter(5),chip_comp/ACLKCounter_T(5),CLK_40MHZ,POR,'0');
     chip_comp/ACLKCounter_T(5) <= ((EXP18_.EXP)
      OR (NOT chip_comp/ACLKCounter(0) AND
      NOT chip_comp/ACLKCounter(1) AND NOT chip_comp/ACLKCounter(2) AND
      NOT chip_comp/ACLKCounter(3) AND NOT chip_comp/ACLKCounter(4) AND
      chip_comp/ACLKCounter(5))
      OR (NOT chip_comp/ACLKCounter(0) AND
      NOT chip_comp/ACLKCounter(1) AND NOT chip_comp/ACLKCounter(2) AND
      NOT chip_comp/ACLKCounter(3) AND NOT chip_comp/ACLKCounter(4) AND
      chip_comp/ACLKCounter(6))
      OR (NOT chip_comp/ACLKCounter(0) AND
      NOT chip_comp/ACLKCounter(1) AND NOT chip_comp/ACLKCounter(2) AND
      NOT chip_comp/ACLKCounter(3) AND NOT chip_comp/ACLKCounter(4) AND
      chip_comp/ACLKCounter(7))
      OR (NOT chip_comp/ACLKCounter(0) AND
      NOT chip_comp/ACLKCounter(1) AND NOT chip_comp/ACLKCounter(2) AND
      NOT chip_comp/ACLKCounter(3) AND NOT chip_comp/ACLKCounter(4) AND
      chip_comp/ACLKCounter(8))
      OR (chip_comp/SamplingClock(1) AND
      chip_comp/SamplingClock(0) AND NOT chip_comp/ACLKCounter(0) AND
      NOT chip_comp/ACLKCounter(1) AND NOT chip_comp/ACLKCounter(2) AND
      NOT chip_comp/ACLKCounter(3) AND NOT chip_comp/ACLKCounter(4)));

FTCPE_chip_comp/ACLKCounter6: FTCPE port map (chip_comp/ACLKCounter(6),chip_comp/ACLKCounter_T(6),CLK_40MHZ,POR,'0');
     chip_comp/ACLKCounter_T(6) <= ((NOT chip_comp/ACLKCounter(0) AND
      NOT chip_comp/ACLKCounter(1) AND NOT chip_comp/ACLKCounter(2) AND
      NOT chip_comp/ACLKCounter(3) AND NOT chip_comp/ACLKCounter(4) AND
      NOT chip_comp/ACLKCounter(5) AND chip_comp/ACLKCounter(6))
      OR (NOT chip_comp/ACLKCounter(0) AND
      NOT chip_comp/ACLKCounter(1) AND NOT chip_comp/ACLKCounter(2) AND
      NOT chip_comp/ACLKCounter(3) AND NOT chip_comp/ACLKCounter(4) AND
      NOT chip_comp/ACLKCounter(5) AND chip_comp/ACLKCounter(7))
      OR (NOT chip_comp/ACLKCounter(0) AND
      NOT chip_comp/ACLKCounter(1) AND NOT chip_comp/ACLKCounter(2) AND
      NOT chip_comp/ACLKCounter(3) AND NOT chip_comp/ACLKCounter(4) AND
      NOT chip_comp/ACLKCounter(5) AND chip_comp/ACLKCounter(8))
      OR (NOT chip_comp/SamplingClock(1) AND
      chip_comp/SamplingClock(0) AND NOT chip_comp/ACLKCounter(0) AND
      NOT chip_comp/ACLKCounter(1) AND NOT chip_comp/ACLKCounter(2) AND
      NOT chip_comp/ACLKCounter(3) AND NOT chip_comp/ACLKCounter(4) AND
      NOT chip_comp/ACLKCounter(5)));

FTCPE_chip_comp/ACLKCounter7: FTCPE port map (chip_comp/ACLKCounter(7),chip_comp/ACLKCounter_T(7),CLK_40MHZ,POR,'0');
     chip_comp/ACLKCounter_T(7) <= ((NOT chip_comp/ACLKCounter(0) AND
      NOT chip_comp/ACLKCounter(1) AND NOT chip_comp/ACLKCounter(2) AND
      NOT chip_comp/ACLKCounter(3) AND NOT chip_comp/ACLKCounter(4) AND
      NOT chip_comp/ACLKCounter(5) AND NOT chip_comp/ACLKCounter(6) AND
      chip_comp/ACLKCounter(7))
      OR (NOT chip_comp/ACLKCounter(0) AND
      NOT chip_comp/ACLKCounter(1) AND NOT chip_comp/ACLKCounter(2) AND
      NOT chip_comp/ACLKCounter(3) AND NOT chip_comp/ACLKCounter(4) AND
      NOT chip_comp/ACLKCounter(5) AND NOT chip_comp/ACLKCounter(6) AND
      chip_comp/ACLKCounter(8))
      OR (chip_comp/SamplingClock(1) AND
      NOT chip_comp/SamplingClock(0) AND NOT chip_comp/ACLKCounter(0) AND
      NOT chip_comp/ACLKCounter(1) AND NOT chip_comp/ACLKCounter(2) AND
      NOT chip_comp/ACLKCounter(3) AND NOT chip_comp/ACLKCounter(4) AND
      NOT chip_comp/ACLKCounter(5) AND NOT chip_comp/ACLKCounter(6)));

FTCPE_chip_comp/ACLKCounter8: FTCPE port map (chip_comp/ACLKCounter(8),chip_comp/ACLKCounter_T(8),CLK_40MHZ,POR,'0');
     chip_comp/ACLKCounter_T(8) <= ((NOT chip_comp/ACLKCounter(0) AND
      NOT chip_comp/ACLKCounter(1) AND NOT chip_comp/ACLKCounter(2) AND
      NOT chip_comp/ACLKCounter(3) AND NOT chip_comp/ACLKCounter(4) AND
      NOT chip_comp/ACLKCounter(5) AND NOT chip_comp/ACLKCounter(6) AND
      NOT chip_comp/ACLKCounter(7) AND chip_comp/ACLKCounter(8))
      OR (chip_comp/SamplingClock(1) AND
      chip_comp/SamplingClock(0) AND NOT chip_comp/ACLKCounter(0) AND
      NOT chip_comp/ACLKCounter(1) AND NOT chip_comp/ACLKCounter(2) AND
      NOT chip_comp/ACLKCounter(3) AND NOT chip_comp/ACLKCounter(4) AND
      NOT chip_comp/ACLKCounter(5) AND NOT chip_comp/ACLKCounter(6) AND
      NOT chip_comp/ACLKCounter(7)));

FDCPE_chip_comp/ACLKsig_1: FDCPE port map (chip_comp/ACLKsig_1,ACLK,CLK_40MHZ,POR,'0');

FDCPE_chip_comp/ACQENnB0Reg0: FDCPE port map (chip_comp/ACQENnB0Reg(0),chip_comp/CommandReceived(0),CLK_40MHZ,POR,'0',chip_comp/ACQENnB0Reg_CE(0));
     chip_comp/ACQENnB0Reg_CE(0) <= (NOT chip_comp/RunningFlag AND
      NOT chip_comp/CommandReceived(10) AND NOT chip_comp/CommandReceived(13) AND
      NOT chip_comp/CommandReceived(14) AND NOT chip_comp/CommandReceived(9) AND
      NOT chip_comp/CommandReceived(11) AND NOT chip_comp/CommandReceived(12) AND
      NOT chip_comp/CommandReceived(15) AND chip_comp/CommandReceived(8) AND
      NOT chip_comp/CommandReceived(4) AND NOT chip_comp/CommandReceived(5) AND
      NOT chip_comp/CommandReceived(6) AND NOT chip_comp/CommandReceived(7) AND
      chip_comp/TXMAINSTATE_FFd1);

FDCPE_chip_comp/ACQENnB0Reg1: FDCPE port map (chip_comp/ACQENnB0Reg(1),chip_comp/CommandReceived(1),CLK_40MHZ,POR,'0',chip_comp/ACQENnB0Reg_CE(1));
     chip_comp/ACQENnB0Reg_CE(1) <= (NOT chip_comp/RunningFlag AND
      NOT chip_comp/CommandReceived(10) AND NOT chip_comp/CommandReceived(13) AND
      NOT chip_comp/CommandReceived(14) AND NOT chip_comp/CommandReceived(9) AND
      NOT chip_comp/CommandReceived(11) AND NOT chip_comp/CommandReceived(12) AND
      NOT chip_comp/CommandReceived(15) AND chip_comp/CommandReceived(8) AND
      NOT chip_comp/CommandReceived(4) AND NOT chip_comp/CommandReceived(5) AND
      NOT chip_comp/CommandReceived(6) AND NOT chip_comp/CommandReceived(7) AND
      chip_comp/TXMAINSTATE_FFd1);

FDCPE_chip_comp/ACQENnB0Reg2: FDCPE port map (chip_comp/ACQENnB0Reg(2),chip_comp/CommandReceived(2),CLK_40MHZ,POR,'0',chip_comp/ACQENnB0Reg_CE(2));
     chip_comp/ACQENnB0Reg_CE(2) <= (NOT chip_comp/RunningFlag AND
      NOT chip_comp/CommandReceived(10) AND NOT chip_comp/CommandReceived(13) AND
      NOT chip_comp/CommandReceived(14) AND NOT chip_comp/CommandReceived(9) AND
      NOT chip_comp/CommandReceived(11) AND NOT chip_comp/CommandReceived(12) AND
      NOT chip_comp/CommandReceived(15) AND chip_comp/CommandReceived(8) AND
      NOT chip_comp/CommandReceived(4) AND NOT chip_comp/CommandReceived(5) AND
      NOT chip_comp/CommandReceived(6) AND NOT chip_comp/CommandReceived(7) AND
      chip_comp/TXMAINSTATE_FFd1);

FDCPE_chip_comp/ACQENnB0Reg3: FDCPE port map (chip_comp/ACQENnB0Reg(3),chip_comp/CommandReceived(3),CLK_40MHZ,POR,'0',chip_comp/ACQENnB0Reg_CE(3));
     chip_comp/ACQENnB0Reg_CE(3) <= (NOT chip_comp/RunningFlag AND
      NOT chip_comp/CommandReceived(10) AND NOT chip_comp/CommandReceived(13) AND
      NOT chip_comp/CommandReceived(14) AND NOT chip_comp/CommandReceived(9) AND
      NOT chip_comp/CommandReceived(11) AND NOT chip_comp/CommandReceived(12) AND
      NOT chip_comp/CommandReceived(15) AND chip_comp/CommandReceived(8) AND
      NOT chip_comp/CommandReceived(4) AND NOT chip_comp/CommandReceived(5) AND
      NOT chip_comp/CommandReceived(6) AND NOT chip_comp/CommandReceived(7) AND
      chip_comp/TXMAINSTATE_FFd1);

FDCPE_chip_comp/ACQENnB1Reg0: FDCPE port map (chip_comp/ACQENnB1Reg(0),chip_comp/CommandReceived(0),CLK_40MHZ,POR,'0',chip_comp/ACQENnB1Reg_CE(0));
     chip_comp/ACQENnB1Reg_CE(0) <= (NOT chip_comp/RunningFlag AND
      NOT chip_comp/CommandReceived(10) AND NOT chip_comp/CommandReceived(13) AND
      NOT chip_comp/CommandReceived(14) AND NOT chip_comp/CommandReceived(9) AND
      NOT chip_comp/CommandReceived(11) AND NOT chip_comp/CommandReceived(12) AND
      NOT chip_comp/CommandReceived(15) AND chip_comp/CommandReceived(8) AND
      chip_comp/CommandReceived(4) AND NOT chip_comp/CommandReceived(5) AND
      NOT chip_comp/CommandReceived(6) AND NOT chip_comp/CommandReceived(7) AND
      chip_comp/TXMAINSTATE_FFd1);

FDCPE_chip_comp/ACQENnB1Reg1: FDCPE port map (chip_comp/ACQENnB1Reg(1),chip_comp/CommandReceived(1),CLK_40MHZ,POR,'0',chip_comp/ACQENnB1Reg_CE(1));
     chip_comp/ACQENnB1Reg_CE(1) <= (NOT chip_comp/RunningFlag AND
      NOT chip_comp/CommandReceived(10) AND NOT chip_comp/CommandReceived(13) AND
      NOT chip_comp/CommandReceived(14) AND NOT chip_comp/CommandReceived(9) AND
      NOT chip_comp/CommandReceived(11) AND NOT chip_comp/CommandReceived(12) AND
      NOT chip_comp/CommandReceived(15) AND chip_comp/CommandReceived(8) AND
      chip_comp/CommandReceived(4) AND NOT chip_comp/CommandReceived(5) AND
      NOT chip_comp/CommandReceived(6) AND NOT chip_comp/CommandReceived(7) AND
      chip_comp/TXMAINSTATE_FFd1);

FDCPE_chip_comp/ACQENnB1Reg2: FDCPE port map (chip_comp/ACQENnB1Reg(2),chip_comp/CommandReceived(2),CLK_40MHZ,POR,'0',chip_comp/ACQENnB1Reg_CE(2));
     chip_comp/ACQENnB1Reg_CE(2) <= (NOT chip_comp/RunningFlag AND
      NOT chip_comp/CommandReceived(10) AND NOT chip_comp/CommandReceived(13) AND
      NOT chip_comp/CommandReceived(14) AND NOT chip_comp/CommandReceived(9) AND
      NOT chip_comp/CommandReceived(11) AND NOT chip_comp/CommandReceived(12) AND
      NOT chip_comp/CommandReceived(15) AND chip_comp/CommandReceived(8) AND
      chip_comp/CommandReceived(4) AND NOT chip_comp/CommandReceived(5) AND
      NOT chip_comp/CommandReceived(6) AND NOT chip_comp/CommandReceived(7) AND
      chip_comp/TXMAINSTATE_FFd1);

FDCPE_chip_comp/ACQENnB1Reg3: FDCPE port map (chip_comp/ACQENnB1Reg(3),chip_comp/CommandReceived(3),CLK_40MHZ,POR,'0',chip_comp/ACQENnB1Reg_CE(3));
     chip_comp/ACQENnB1Reg_CE(3) <= (NOT chip_comp/RunningFlag AND
      NOT chip_comp/CommandReceived(10) AND NOT chip_comp/CommandReceived(13) AND
      NOT chip_comp/CommandReceived(14) AND NOT chip_comp/CommandReceived(9) AND
      NOT chip_comp/CommandReceived(11) AND NOT chip_comp/CommandReceived(12) AND
      NOT chip_comp/CommandReceived(15) AND chip_comp/CommandReceived(8) AND
      chip_comp/CommandReceived(4) AND NOT chip_comp/CommandReceived(5) AND
      NOT chip_comp/CommandReceived(6) AND NOT chip_comp/CommandReceived(7) AND
      chip_comp/TXMAINSTATE_FFd1);

FDCPE_chip_comp/ACQENnB2Reg0: FDCPE port map (chip_comp/ACQENnB2Reg(0),chip_comp/CommandReceived(0),CLK_40MHZ,POR,'0',chip_comp/ACQENnB2Reg_CE(0));
     chip_comp/ACQENnB2Reg_CE(0) <= (NOT chip_comp/RunningFlag AND
      NOT chip_comp/CommandReceived(10) AND NOT chip_comp/CommandReceived(13) AND
      NOT chip_comp/CommandReceived(14) AND NOT chip_comp/CommandReceived(9) AND
      NOT chip_comp/CommandReceived(11) AND NOT chip_comp/CommandReceived(12) AND
      NOT chip_comp/CommandReceived(15) AND chip_comp/CommandReceived(8) AND
      NOT chip_comp/CommandReceived(4) AND chip_comp/CommandReceived(5) AND
      NOT chip_comp/CommandReceived(6) AND NOT chip_comp/CommandReceived(7) AND
      chip_comp/TXMAINSTATE_FFd1);

FDCPE_chip_comp/ACQENnB2Reg1: FDCPE port map (chip_comp/ACQENnB2Reg(1),chip_comp/CommandReceived(1),CLK_40MHZ,POR,'0',chip_comp/ACQENnB2Reg_CE(1));
     chip_comp/ACQENnB2Reg_CE(1) <= (NOT chip_comp/RunningFlag AND
      NOT chip_comp/CommandReceived(10) AND NOT chip_comp/CommandReceived(13) AND
      NOT chip_comp/CommandReceived(14) AND NOT chip_comp/CommandReceived(9) AND
      NOT chip_comp/CommandReceived(11) AND NOT chip_comp/CommandReceived(12) AND
      NOT chip_comp/CommandReceived(15) AND chip_comp/CommandReceived(8) AND
      NOT chip_comp/CommandReceived(4) AND chip_comp/CommandReceived(5) AND
      NOT chip_comp/CommandReceived(6) AND NOT chip_comp/CommandReceived(7) AND
      chip_comp/TXMAINSTATE_FFd1);

FDCPE_chip_comp/ACQENnB2Reg2: FDCPE port map (chip_comp/ACQENnB2Reg(2),chip_comp/CommandReceived(2),CLK_40MHZ,POR,'0',chip_comp/ACQENnB2Reg_CE(2));
     chip_comp/ACQENnB2Reg_CE(2) <= (NOT chip_comp/RunningFlag AND
      NOT chip_comp/CommandReceived(10) AND NOT chip_comp/CommandReceived(13) AND
      NOT chip_comp/CommandReceived(14) AND NOT chip_comp/CommandReceived(9) AND
      NOT chip_comp/CommandReceived(11) AND NOT chip_comp/CommandReceived(12) AND
      NOT chip_comp/CommandReceived(15) AND chip_comp/CommandReceived(8) AND
      NOT chip_comp/CommandReceived(4) AND chip_comp/CommandReceived(5) AND
      NOT chip_comp/CommandReceived(6) AND NOT chip_comp/CommandReceived(7) AND
      chip_comp/TXMAINSTATE_FFd1);

FDCPE_chip_comp/ACQENnB2Reg3: FDCPE port map (chip_comp/ACQENnB2Reg(3),chip_comp/CommandReceived(3),CLK_40MHZ,POR,'0',chip_comp/ACQENnB2Reg_CE(3));
     chip_comp/ACQENnB2Reg_CE(3) <= (NOT chip_comp/RunningFlag AND
      NOT chip_comp/CommandReceived(10) AND NOT chip_comp/CommandReceived(13) AND
      NOT chip_comp/CommandReceived(14) AND NOT chip_comp/CommandReceived(9) AND
      NOT chip_comp/CommandReceived(11) AND NOT chip_comp/CommandReceived(12) AND
      NOT chip_comp/CommandReceived(15) AND chip_comp/CommandReceived(8) AND
      NOT chip_comp/CommandReceived(4) AND chip_comp/CommandReceived(5) AND
      NOT chip_comp/CommandReceived(6) AND NOT chip_comp/CommandReceived(7) AND
      chip_comp/TXMAINSTATE_FFd1);

FDCPE_chip_comp/ACQENnB3Reg0: FDCPE port map (chip_comp/ACQENnB3Reg(0),chip_comp/CommandReceived(0),CLK_40MHZ,POR,'0',chip_comp/ACQENnB3Reg_CE(0));
     chip_comp/ACQENnB3Reg_CE(0) <= (NOT chip_comp/RunningFlag AND
      NOT chip_comp/CommandReceived(10) AND NOT chip_comp/CommandReceived(13) AND
      NOT chip_comp/CommandReceived(14) AND NOT chip_comp/CommandReceived(9) AND
      NOT chip_comp/CommandReceived(11) AND NOT chip_comp/CommandReceived(12) AND
      NOT chip_comp/CommandReceived(15) AND chip_comp/CommandReceived(8) AND
      chip_comp/CommandReceived(4) AND chip_comp/CommandReceived(5) AND
      NOT chip_comp/CommandReceived(6) AND NOT chip_comp/CommandReceived(7) AND
      chip_comp/TXMAINSTATE_FFd1);

FDCPE_chip_comp/ACQENnB3Reg1: FDCPE port map (chip_comp/ACQENnB3Reg(1),chip_comp/CommandReceived(1),CLK_40MHZ,POR,'0',chip_comp/ACQENnB3Reg_CE(1));
     chip_comp/ACQENnB3Reg_CE(1) <= (NOT chip_comp/RunningFlag AND
      NOT chip_comp/CommandReceived(10) AND NOT chip_comp/CommandReceived(13) AND
      NOT chip_comp/CommandReceived(14) AND NOT chip_comp/CommandReceived(9) AND
      NOT chip_comp/CommandReceived(11) AND NOT chip_comp/CommandReceived(12) AND
      NOT chip_comp/CommandReceived(15) AND chip_comp/CommandReceived(8) AND
      chip_comp/CommandReceived(4) AND chip_comp/CommandReceived(5) AND
      NOT chip_comp/CommandReceived(6) AND NOT chip_comp/CommandReceived(7) AND
      chip_comp/TXMAINSTATE_FFd1);

FDCPE_chip_comp/ACQENnB3Reg2: FDCPE port map (chip_comp/ACQENnB3Reg(2),chip_comp/CommandReceived(2),CLK_40MHZ,POR,'0',chip_comp/ACQENnB3Reg_CE(2));
     chip_comp/ACQENnB3Reg_CE(2) <= (NOT chip_comp/RunningFlag AND
      NOT chip_comp/CommandReceived(10) AND NOT chip_comp/CommandReceived(13) AND
      NOT chip_comp/CommandReceived(14) AND NOT chip_comp/CommandReceived(9) AND
      NOT chip_comp/CommandReceived(11) AND NOT chip_comp/CommandReceived(12) AND
      NOT chip_comp/CommandReceived(15) AND chip_comp/CommandReceived(8) AND
      chip_comp/CommandReceived(4) AND chip_comp/CommandReceived(5) AND
      NOT chip_comp/CommandReceived(6) AND NOT chip_comp/CommandReceived(7) AND
      chip_comp/TXMAINSTATE_FFd1);

FDCPE_chip_comp/ACQENnB3Reg3: FDCPE port map (chip_comp/ACQENnB3Reg(3),chip_comp/CommandReceived(3),CLK_40MHZ,POR,'0',chip_comp/ACQENnB3Reg_CE(3));
     chip_comp/ACQENnB3Reg_CE(3) <= (NOT chip_comp/RunningFlag AND
      NOT chip_comp/CommandReceived(10) AND NOT chip_comp/CommandReceived(13) AND
      NOT chip_comp/CommandReceived(14) AND NOT chip_comp/CommandReceived(9) AND
      NOT chip_comp/CommandReceived(11) AND NOT chip_comp/CommandReceived(12) AND
      NOT chip_comp/CommandReceived(15) AND chip_comp/CommandReceived(8) AND
      chip_comp/CommandReceived(4) AND chip_comp/CommandReceived(5) AND
      NOT chip_comp/CommandReceived(6) AND NOT chip_comp/CommandReceived(7) AND
      chip_comp/TXMAINSTATE_FFd1);

FTCPE_chip_comp/ADCRestCMD: FTCPE port map (chip_comp/ADCRestCMD,chip_comp/ADCRestCMD_T,CLK_40MHZ,'0',POR);
chip_comp/ADCRestCMD_T <= (NOT chip_comp/TXMAINSTATE_FFd1 AND
NOT chip_comp/TXMAINSTATE_FFd2 AND chip_comp/ADCRestCMD);

FDCPE_chip_comp/CommandAvailable: FDCPE port map (chip_comp/CommandAvailable,chip_comp/CommandAvailable_D,CLK_40MHZ,POR,'0');
     chip_comp/CommandAvailable_D <= (chip_comp/ReceiveCommandComp/sr(1) AND
      chip_comp/ReceiveCommandComp/sr(2) AND NOT chip_comp/ReceiveCommandComp/sr(3) AND
      chip_comp/ReceiveCommandComp/sr(4));

FDCPE_chip_comp/CommandReceived0: FDCPE port map (chip_comp/CommandReceived(0),chip_comp/ReceiveCommandComp/sr(5),CLK_40MHZ,POR,'0',chip_comp/CommandReceived_CE(0));
     chip_comp/CommandReceived_CE(0) <= (chip_comp/ReceiveCommandComp/sr(1) AND
      chip_comp/ReceiveCommandComp/sr(2) AND NOT chip_comp/ReceiveCommandComp/sr(3) AND
      chip_comp/ReceiveCommandComp/sr(4));

FDCPE_chip_comp/CommandReceived1: FDCPE port map (chip_comp/CommandReceived(1),chip_comp/ReceiveCommandComp/sr(6),CLK_40MHZ,POR,'0',chip_comp/CommandReceived_CE(1));
     chip_comp/CommandReceived_CE(1) <= (chip_comp/ReceiveCommandComp/sr(1) AND
      chip_comp/ReceiveCommandComp/sr(2) AND NOT chip_comp/ReceiveCommandComp/sr(3) AND
      chip_comp/ReceiveCommandComp/sr(4));

FDCPE_chip_comp/CommandReceived2: FDCPE port map (chip_comp/CommandReceived(2),chip_comp/ReceiveCommandComp/sr(7),CLK_40MHZ,POR,'0',chip_comp/CommandReceived_CE(2));
     chip_comp/CommandReceived_CE(2) <= (chip_comp/ReceiveCommandComp/sr(1) AND
      chip_comp/ReceiveCommandComp/sr(2) AND NOT chip_comp/ReceiveCommandComp/sr(3) AND
      chip_comp/ReceiveCommandComp/sr(4));

FDCPE_chip_comp/CommandReceived3: FDCPE port map (chip_comp/CommandReceived(3),chip_comp/ReceiveCommandComp/sr(8),CLK_40MHZ,POR,'0',chip_comp/CommandReceived_CE(3));
     chip_comp/CommandReceived_CE(3) <= (chip_comp/ReceiveCommandComp/sr(1) AND
      chip_comp/ReceiveCommandComp/sr(2) AND NOT chip_comp/ReceiveCommandComp/sr(3) AND
      chip_comp/ReceiveCommandComp/sr(4));

FDCPE_chip_comp/CommandReceived4: FDCPE port map (chip_comp/CommandReceived(4),chip_comp/ReceiveCommandComp/sr(9),CLK_40MHZ,POR,'0',chip_comp/CommandReceived_CE(4));
     chip_comp/CommandReceived_CE(4) <= (chip_comp/ReceiveCommandComp/sr(1) AND
      chip_comp/ReceiveCommandComp/sr(2) AND NOT chip_comp/ReceiveCommandComp/sr(3) AND
      chip_comp/ReceiveCommandComp/sr(4));

FDCPE_chip_comp/CommandReceived5: FDCPE port map (chip_comp/CommandReceived(5),chip_comp/ReceiveCommandComp/sr(10),CLK_40MHZ,POR,'0',chip_comp/CommandReceived_CE(5));
     chip_comp/CommandReceived_CE(5) <= (chip_comp/ReceiveCommandComp/sr(1) AND
      chip_comp/ReceiveCommandComp/sr(2) AND NOT chip_comp/ReceiveCommandComp/sr(3) AND
      chip_comp/ReceiveCommandComp/sr(4));

FDCPE_chip_comp/CommandReceived6: FDCPE port map (chip_comp/CommandReceived(6),chip_comp/ReceiveCommandComp/sr(11),CLK_40MHZ,POR,'0',chip_comp/CommandReceived_CE(6));
     chip_comp/CommandReceived_CE(6) <= (chip_comp/ReceiveCommandComp/sr(1) AND
      chip_comp/ReceiveCommandComp/sr(2) AND NOT chip_comp/ReceiveCommandComp/sr(3) AND
      chip_comp/ReceiveCommandComp/sr(4));

FDCPE_chip_comp/CommandReceived7: FDCPE port map (chip_comp/CommandReceived(7),chip_comp/ReceiveCommandComp/sr(12),CLK_40MHZ,POR,'0',chip_comp/CommandReceived_CE(7));
     chip_comp/CommandReceived_CE(7) <= (chip_comp/ReceiveCommandComp/sr(1) AND
      chip_comp/ReceiveCommandComp/sr(2) AND NOT chip_comp/ReceiveCommandComp/sr(3) AND
      chip_comp/ReceiveCommandComp/sr(4));

FDCPE_chip_comp/CommandReceived8: FDCPE port map (chip_comp/CommandReceived(8),chip_comp/ReceiveCommandComp/sr(13),CLK_40MHZ,POR,'0',chip_comp/CommandReceived_CE(8));
     chip_comp/CommandReceived_CE(8) <= (chip_comp/ReceiveCommandComp/sr(1) AND
      chip_comp/ReceiveCommandComp/sr(2) AND NOT chip_comp/ReceiveCommandComp/sr(3) AND
      chip_comp/ReceiveCommandComp/sr(4));

FDCPE_chip_comp/CommandReceived9: FDCPE port map (chip_comp/CommandReceived(9),chip_comp/ReceiveCommandComp/sr(14),CLK_40MHZ,POR,'0',chip_comp/CommandReceived_CE(9));
     chip_comp/CommandReceived_CE(9) <= (chip_comp/ReceiveCommandComp/sr(1) AND
      chip_comp/ReceiveCommandComp/sr(2) AND NOT chip_comp/ReceiveCommandComp/sr(3) AND
      chip_comp/ReceiveCommandComp/sr(4));

FDCPE_chip_comp/CommandReceived10: FDCPE port map (chip_comp/CommandReceived(10),chip_comp/ReceiveCommandComp/sr(15),CLK_40MHZ,POR,'0',chip_comp/CommandReceived_CE(10));
     chip_comp/CommandReceived_CE(10) <= (chip_comp/ReceiveCommandComp/sr(1) AND
      chip_comp/ReceiveCommandComp/sr(2) AND NOT chip_comp/ReceiveCommandComp/sr(3) AND
      chip_comp/ReceiveCommandComp/sr(4));

FDCPE_chip_comp/CommandReceived11: FDCPE port map (chip_comp/CommandReceived(11),chip_comp/ReceiveCommandComp/sr(16),CLK_40MHZ,POR,'0',chip_comp/CommandReceived_CE(11));
     chip_comp/CommandReceived_CE(11) <= (chip_comp/ReceiveCommandComp/sr(1) AND
      chip_comp/ReceiveCommandComp/sr(2) AND NOT chip_comp/ReceiveCommandComp/sr(3) AND
      chip_comp/ReceiveCommandComp/sr(4));

FDCPE_chip_comp/CommandReceived12: FDCPE port map (chip_comp/CommandReceived(12),chip_comp/ReceiveCommandComp/sr(17),CLK_40MHZ,POR,'0',chip_comp/CommandReceived_CE(12));
     chip_comp/CommandReceived_CE(12) <= (chip_comp/ReceiveCommandComp/sr(1) AND
      chip_comp/ReceiveCommandComp/sr(2) AND NOT chip_comp/ReceiveCommandComp/sr(3) AND
      chip_comp/ReceiveCommandComp/sr(4));

FDCPE_chip_comp/CommandReceived13: FDCPE port map (chip_comp/CommandReceived(13),chip_comp/ReceiveCommandComp/sr(18),CLK_40MHZ,POR,'0',chip_comp/CommandReceived_CE(13));
     chip_comp/CommandReceived_CE(13) <= (chip_comp/ReceiveCommandComp/sr(1) AND
      chip_comp/ReceiveCommandComp/sr(2) AND NOT chip_comp/ReceiveCommandComp/sr(3) AND
      chip_comp/ReceiveCommandComp/sr(4));

FDCPE_chip_comp/CommandReceived14: FDCPE port map (chip_comp/CommandReceived(14),chip_comp/ReceiveCommandComp/sr(19),CLK_40MHZ,POR,'0',chip_comp/CommandReceived_CE(14));
     chip_comp/CommandReceived_CE(14) <= (chip_comp/ReceiveCommandComp/sr(1) AND
      chip_comp/ReceiveCommandComp/sr(2) AND NOT chip_comp/ReceiveCommandComp/sr(3) AND
      chip_comp/ReceiveCommandComp/sr(4));

FDCPE_chip_comp/CommandReceived15: FDCPE port map (chip_comp/CommandReceived(15),chip_comp/ReceiveCommandComp/sr(20),CLK_40MHZ,POR,'0',chip_comp/CommandReceived_CE(15));
     chip_comp/CommandReceived_CE(15) <= (chip_comp/ReceiveCommandComp/sr(1) AND
      chip_comp/ReceiveCommandComp/sr(2) AND NOT chip_comp/ReceiveCommandComp/sr(3) AND
      chip_comp/ReceiveCommandComp/sr(4));

FDCPE_chip_comp/DataPackageTXEn: FDCPE port map (chip_comp/DataPackageTXEn,chip_comp/CommandReceived(0),CLK_40MHZ,POR,'0',chip_comp/DataPackageTXEn_CE);
     chip_comp/DataPackageTXEn_CE <= (NOT chip_comp/CommandReceived(10) AND
      chip_comp/CommandReceived(13) AND chip_comp/CommandReceived(14) AND
      NOT chip_comp/CommandReceived(9) AND chip_comp/CommandReceived(11) AND
      NOT chip_comp/CommandReceived(12) AND NOT chip_comp/CommandReceived(15) AND
      chip_comp/CommandReceived(8) AND chip_comp/TXMAINSTATE_FFd1);

FDCPE_chip_comp/Datasig0: FDCPE port map (chip_comp/Datasig(0),chip_comp/Datasig_D(0),CLK_40MHZ,POR,'0');
     chip_comp/Datasig_D(0) <= ((EXP36_.EXP)
      OR (EXP39_.EXP)
      OR (HFn_B(3) AND NOT chip_comp/TXREADOUTSTATE_FFd3 AND
      NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd1 AND
      chip_comp/Datasig(0))
      OR (HFn_B(2) AND chip_comp/TXREADOUTSTATE_FFd3 AND
      NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND
      chip_comp/Datasig(0))
      OR (HFn_B(1) AND chip_comp/TXREADOUTSTATE_FFd3 AND
      chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND
      chip_comp/Datasig(0))
      OR (HFn_B(0) AND NOT chip_comp/TXREADOUTSTATE_FFd3 AND
      chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND
      chip_comp/Datasig(0))
      OR (chip_comp/StatusDataSel(2) AND
      chip_comp/ENABLEn_BReg(0) AND NOT chip_comp/TXREADOUTSTATE_FFd3 AND
      NOT chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND
      NOT chip_comp/TXREADOUTSTATE_FFd1 AND NOT chip_comp/GenDataCMD));

FDCPE_chip_comp/Datasig1: FDCPE port map (chip_comp/Datasig(1),chip_comp/Datasig_D(1),CLK_40MHZ,POR,'0');
     chip_comp/Datasig_D(1) <= ((EXP40_.EXP)
      OR (DAC_DINsig$BUF7.EXP)
      OR (NOT HFn_B(2) AND chip_comp/TXREADOUTSTATE_FFd3 AND
      NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2)
      OR (chip_comp/TXREADOUTSTATE_FFd3 AND
      chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND
      chip_comp/Datasig(1))
      OR (chip_comp/TXREADOUTSTATE_FFd3 AND
      NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND
      chip_comp/Datasig(1))
      OR (chip_comp/TXREADOUTSTATE_FFd3 AND
      NOT chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND
      NOT chip_comp/TXREADOUTSTATE_FFd1)
      OR (NOT chip_comp/TXREADOUTSTATE_FFd3 AND
      chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND
      chip_comp/Datasig(1)));

FDCPE_chip_comp/Datasig2: FDCPE port map (chip_comp/Datasig(2),chip_comp/Datasig_D(2),CLK_40MHZ,POR,'0');
     chip_comp/Datasig_D(2) <= ((D_OEn_Bsig(2).EXP)
      OR (EXP38_.EXP)
      OR (HFn_B(3) AND NOT chip_comp/TXREADOUTSTATE_FFd3 AND
      NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd1 AND
      chip_comp/Datasig(2))
      OR (HFn_B(2) AND chip_comp/TXREADOUTSTATE_FFd3 AND
      NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND
      chip_comp/Datasig(2))
      OR (HFn_B(1) AND chip_comp/TXREADOUTSTATE_FFd3 AND
      chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND
      chip_comp/Datasig(2))
      OR (HFn_B(0) AND NOT chip_comp/TXREADOUTSTATE_FFd3 AND
      chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND
      chip_comp/Datasig(2))
      OR (chip_comp/StatusDataSel(2) AND
      chip_comp/ENABLEn_BReg(2) AND NOT chip_comp/TXREADOUTSTATE_FFd3 AND
      NOT chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND
      NOT chip_comp/TXREADOUTSTATE_FFd1 AND NOT chip_comp/GenDataCMD));

FDCPE_chip_comp/Datasig3: FDCPE port map (chip_comp/Datasig(3),chip_comp/Datasig_D(3),CLK_40MHZ,POR,'0');
     chip_comp/Datasig_D(3) <= ((EXP44_.EXP)
      OR (DAC_DINsig$BUF8.EXP)
      OR (NOT HFn_B(3) AND NOT chip_comp/TXREADOUTSTATE_FFd3 AND
      NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd1)
      OR (chip_comp/TXREADOUTSTATE_FFd3 AND
      chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND
      chip_comp/Datasig(3))
      OR (chip_comp/TXREADOUTSTATE_FFd3 AND
      NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND
      chip_comp/Datasig(3))
      OR (chip_comp/TXREADOUTSTATE_FFd3 AND
      NOT chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND
      NOT chip_comp/TXREADOUTSTATE_FFd1)
      OR (NOT chip_comp/TXREADOUTSTATE_FFd3 AND
      chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND
      chip_comp/Datasig(3)));

FDCPE_chip_comp/Datasig4: FDCPE port map (chip_comp/Datasig(4),chip_comp/Datasig_D(4),CLK_40MHZ,POR,'0');
     chip_comp/Datasig_D(4) <= ((RST4n_Bsig(1).EXP)
      OR (HFn_B(3) AND NOT chip_comp/TXREADOUTSTATE_FFd3 AND
      NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd1 AND
      chip_comp/Datasig(4))
      OR (HFn_B(2) AND chip_comp/TXREADOUTSTATE_FFd3 AND
      NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND
      chip_comp/Datasig(4))
      OR (HFn_B(1) AND chip_comp/TXREADOUTSTATE_FFd3 AND
      chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND
      chip_comp/Datasig(4))
      OR (HFn_B(0) AND NOT chip_comp/TXREADOUTSTATE_FFd3 AND
      chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND
      chip_comp/Datasig(4))
      OR (NOT chip_comp/StatusDataSel(2) AND
      NOT chip_comp/StatusDataSel(3) AND NOT chip_comp/StatusDataSel(4) AND
      NOT chip_comp/TXREADOUTSTATE_FFd3 AND NOT chip_comp/TXREADOUTSTATE_FFd4 AND
      NOT chip_comp/TXREADOUTSTATE_FFd2 AND NOT chip_comp/TXREADOUTSTATE_FFd1 AND
      NOT chip_comp/GenDataCMD AND chip_comp/Datasig(4)));

FDCPE_chip_comp/Datasig5: FDCPE port map (chip_comp/Datasig(5),chip_comp/Datasig_D(5),CLK_40MHZ,POR,'0');
     chip_comp/Datasig_D(5) <= ((EXP24_.EXP)
      OR (EXP25_.EXP)
      OR (chip_comp/TXREADOUTSTATE_FFd3 AND
      chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND
      chip_comp/Datasig(5))
      OR (chip_comp/TXREADOUTSTATE_FFd3 AND
      NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND
      chip_comp/Datasig(5))
      OR (chip_comp/TXREADOUTSTATE_FFd3 AND
      NOT chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND
      NOT chip_comp/TXREADOUTSTATE_FFd1)
      OR (NOT chip_comp/TXREADOUTSTATE_FFd3 AND
      chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND
      chip_comp/Datasig(5))
      OR (NOT chip_comp/TXREADOUTSTATE_FFd3 AND
      NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd1 AND
      chip_comp/Datasig(5)));

FDCPE_chip_comp/Datasig6: FDCPE port map (chip_comp/Datasig(6),chip_comp/Datasig_D(6),CLK_40MHZ,POR,'0');
     chip_comp/Datasig_D(6) <= ((EXP41_.EXP)
      OR (EXP42_.EXP)
      OR (HFn_B(3) AND NOT chip_comp/TXREADOUTSTATE_FFd3 AND
      NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd1 AND
      chip_comp/Datasig(6))
      OR (HFn_B(2) AND chip_comp/TXREADOUTSTATE_FFd3 AND
      NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND
      chip_comp/Datasig(6))
      OR (HFn_B(1) AND chip_comp/TXREADOUTSTATE_FFd3 AND
      chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND
      chip_comp/Datasig(6))
      OR (HFn_B(0) AND NOT chip_comp/TXREADOUTSTATE_FFd3 AND
      chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND
      chip_comp/Datasig(6))
      OR (DR1 AND chip_comp/StatusDataSel(3) AND
      NOT chip_comp/TXREADOUTSTATE_FFd3 AND NOT chip_comp/TXREADOUTSTATE_FFd4 AND
      NOT chip_comp/TXREADOUTSTATE_FFd2 AND NOT chip_comp/TXREADOUTSTATE_FFd1 AND
      NOT chip_comp/GenDataCMD));

FDCPE_chip_comp/Datasig7: FDCPE port map (chip_comp/Datasig(7),chip_comp/Datasig_D(7),CLK_40MHZ,POR,'0');
     chip_comp/Datasig_D(7) <= ((EXP27_.EXP)
      OR (Datasig(8).EXP)
      OR (chip_comp/TXREADOUTSTATE_FFd3 AND
      chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND
      chip_comp/Datasig(7))
      OR (chip_comp/TXREADOUTSTATE_FFd3 AND
      NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND
      chip_comp/Datasig(7))
      OR (chip_comp/TXREADOUTSTATE_FFd3 AND
      NOT chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND
      NOT chip_comp/TXREADOUTSTATE_FFd1)
      OR (NOT chip_comp/TXREADOUTSTATE_FFd3 AND
      chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND
      chip_comp/Datasig(7))
      OR (NOT chip_comp/TXREADOUTSTATE_FFd3 AND
      NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd1 AND
      chip_comp/Datasig(7)));

FDCPE_chip_comp/Datasig8: FDCPE port map (chip_comp/Datasig(8),chip_comp/Datasig_D(8),CLK_40MHZ,POR,'0');
     chip_comp/Datasig_D(8) <= ((EXP30_.EXP)
      OR (EXP31_.EXP)
      OR (HFn_B(3) AND NOT chip_comp/TXREADOUTSTATE_FFd3 AND
      NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd1 AND
      chip_comp/Datasig(8))
      OR (HFn_B(2) AND chip_comp/TXREADOUTSTATE_FFd3 AND
      NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND
      chip_comp/Datasig(8))
      OR (HFn_B(1) AND chip_comp/TXREADOUTSTATE_FFd3 AND
      chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND
      chip_comp/Datasig(8))
      OR (HFn_B(0) AND NOT chip_comp/TXREADOUTSTATE_FFd3 AND
      chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND
      chip_comp/Datasig(8))
      OR (PT0 AND chip_comp/StatusDataSel(3) AND
      NOT chip_comp/TXREADOUTSTATE_FFd3 AND NOT chip_comp/TXREADOUTSTATE_FFd4 AND
      NOT chip_comp/TXREADOUTSTATE_FFd2 AND NOT chip_comp/TXREADOUTSTATE_FFd1 AND
      NOT chip_comp/GenDataCMD));

FDCPE_chip_comp/Datasig9: FDCPE port map (chip_comp/Datasig(9),chip_comp/Datasig_D(9),CLK_40MHZ,POR,'0');
     chip_comp/Datasig_D(9) <= ((ACQENnB2sig(0).EXP)
      OR (EXP21_.EXP)
      OR (chip_comp/TXREADOUTSTATE_FFd3 AND
      chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND
      chip_comp/Datasig(9))
      OR (chip_comp/TXREADOUTSTATE_FFd3 AND
      NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND
      chip_comp/Datasig(9))
      OR (chip_comp/TXREADOUTSTATE_FFd3 AND
      NOT chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND
      NOT chip_comp/TXREADOUTSTATE_FFd1)
      OR (NOT chip_comp/TXREADOUTSTATE_FFd3 AND
      chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND
      chip_comp/Datasig(9))
      OR (NOT chip_comp/TXREADOUTSTATE_FFd3 AND
      NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd1 AND
      chip_comp/Datasig(9)));

FDCPE_chip_comp/Datasig10: FDCPE port map (chip_comp/Datasig(10),chip_comp/Datasig_D(10),CLK_40MHZ,POR,'0');
     chip_comp/Datasig_D(10) <= ((EXP22_.EXP)
      OR (HFn_B(3) AND NOT chip_comp/TXREADOUTSTATE_FFd3 AND
      NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd1 AND
      chip_comp/Datasig(10))
      OR (HFn_B(2) AND chip_comp/TXREADOUTSTATE_FFd3 AND
      NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND
      chip_comp/Datasig(10))
      OR (HFn_B(1) AND chip_comp/TXREADOUTSTATE_FFd3 AND
      chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND
      chip_comp/Datasig(10))
      OR (HFn_B(0) AND NOT chip_comp/TXREADOUTSTATE_FFd3 AND
      chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND
      chip_comp/Datasig(10)));

FDCPE_chip_comp/Datasig11: FDCPE port map (chip_comp/Datasig(11),chip_comp/Datasig_D(11),CLK_40MHZ,POR,'0');
     chip_comp/Datasig_D(11) <= ((EXP34_.EXP)
      OR (chip_comp/TXREADOUTSTATE_FFd3 AND
      chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2)
      OR (NOT chip_comp/TXREADOUTSTATE_FFd3 AND
      chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2)
      OR (HFn_B(2) AND chip_comp/TXREADOUTSTATE_FFd3 AND
      chip_comp/TXREADOUTSTATE_FFd2 AND NOT chip_comp/Datasig(11))
      OR (chip_comp/TXREADOUTSTATE_FFd3 AND
      NOT chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND
      chip_comp/TXREADOUTSTATE_FFd1)
      OR (NOT chip_comp/TXREADOUTSTATE_FFd3 AND
      NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND
      NOT chip_comp/TXREADOUTSTATE_FFd1));

FDCPE_chip_comp/Datasig12: FDCPE port map (chip_comp/Datasig(12),chip_comp/Datasig_D(12),CLK_40MHZ,POR,'0');
     chip_comp/Datasig_D(12) <= ((Datasig(12).EXP)
      OR (HFn_B(3) AND NOT chip_comp/TXREADOUTSTATE_FFd3 AND
      NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd1 AND
      chip_comp/Datasig(12))
      OR (HFn_B(2) AND chip_comp/TXREADOUTSTATE_FFd3 AND
      NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND
      chip_comp/Datasig(12))
      OR (HFn_B(1) AND chip_comp/TXREADOUTSTATE_FFd3 AND
      chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND
      chip_comp/Datasig(12))
      OR (HFn_B(0) AND NOT chip_comp/TXREADOUTSTATE_FFd3 AND
      chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND
      chip_comp/Datasig(12)));

FDCPE_chip_comp/Datasig13: FDCPE port map (chip_comp/Datasig(13),chip_comp/Datasig_D(13),CLK_40MHZ,POR,'0');
     chip_comp/Datasig_D(13) <= ((chip_comp/SimulData(7).EXP)
      OR (chip_comp/TXREADOUTSTATE_FFd3.EXP)
      OR (chip_comp/TXREADOUTSTATE_FFd3 AND
      chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2)
      OR (NOT chip_comp/TXREADOUTSTATE_FFd3 AND
      chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2)
      OR (HFn_B(2) AND chip_comp/TXREADOUTSTATE_FFd3 AND
      chip_comp/TXREADOUTSTATE_FFd2 AND NOT chip_comp/Datasig(13))
      OR (chip_comp/TXREADOUTSTATE_FFd3 AND
      NOT chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND
      chip_comp/TXREADOUTSTATE_FFd1)
      OR (NOT chip_comp/TXREADOUTSTATE_FFd3 AND
      NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND
      NOT chip_comp/TXREADOUTSTATE_FFd1));

FDCPE_chip_comp/Datasig14: FDCPE port map (chip_comp/Datasig(14),chip_comp/Datasig_D(14),CLK_40MHZ,POR,'0');
     chip_comp/Datasig_D(14) <= ((Datasig(15).EXP)
      OR (HFn_B(3) AND NOT chip_comp/TXREADOUTSTATE_FFd3 AND
      NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd1 AND
      chip_comp/Datasig(14))
      OR (HFn_B(2) AND chip_comp/TXREADOUTSTATE_FFd3 AND
      NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND
      chip_comp/Datasig(14))
      OR (HFn_B(1) AND chip_comp/TXREADOUTSTATE_FFd3 AND
      chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND
      chip_comp/Datasig(14))
      OR (HFn_B(0) AND NOT chip_comp/TXREADOUTSTATE_FFd3 AND
      chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND
      chip_comp/Datasig(14)));

FDCPE_chip_comp/Datasig15: FDCPE port map (chip_comp/Datasig(15),chip_comp/Datasig_D(15),CLK_40MHZ,POR,'0');
     chip_comp/Datasig_D(15) <= ((EXP33_.EXP)
      OR (NOT HFn_B(3) AND NOT chip_comp/TXREADOUTSTATE_FFd3 AND
      NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd1)
      OR (chip_comp/TXREADOUTSTATE_FFd3 AND
      chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND
      chip_comp/Datasig(15))
      OR (chip_comp/TXREADOUTSTATE_FFd3 AND
      NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND
      chip_comp/Datasig(15))
      OR (NOT chip_comp/TXREADOUTSTATE_FFd3 AND
      chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND
      chip_comp/Datasig(15))
      OR (NOT chip_comp/TXREADOUTSTATE_FFd3 AND
      NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd1 AND
      chip_comp/Datasig(15)));

FDCPE_chip_comp/ENABLEn_BReg0: FDCPE port map (chip_comp/ENABLEn_BReg(0),chip_comp/CommandReceived(0),CLK_40MHZ,POR,'0',chip_comp/ENABLEn_BReg_CE(0));
     chip_comp/ENABLEn_BReg_CE(0) <= (NOT chip_comp/RunningFlag AND
      NOT chip_comp/CommandReceived(10) AND NOT chip_comp/CommandReceived(13) AND
      NOT chip_comp/CommandReceived(14) AND NOT chip_comp/CommandReceived(9) AND
      NOT chip_comp/CommandReceived(11) AND NOT chip_comp/CommandReceived(12) AND
      NOT chip_comp/CommandReceived(15) AND chip_comp/CommandReceived(8) AND
      NOT chip_comp/CommandReceived(4) AND NOT chip_comp/CommandReceived(5) AND
      chip_comp/CommandReceived(6) AND NOT chip_comp/CommandReceived(7) AND
      chip_comp/TXMAINSTATE_FFd1);

FDCPE_chip_comp/ENABLEn_BReg1: FDCPE port map (chip_comp/ENABLEn_BReg(1),chip_comp/CommandReceived(1),CLK_40MHZ,POR,'0',chip_comp/ENABLEn_BReg_CE(1));
     chip_comp/ENABLEn_BReg_CE(1) <= (NOT chip_comp/RunningFlag AND
      NOT chip_comp/CommandReceived(10) AND NOT chip_comp/CommandReceived(13) AND
      NOT chip_comp/CommandReceived(14) AND NOT chip_comp/CommandReceived(9) AND
      NOT chip_comp/CommandReceived(11) AND NOT chip_comp/CommandReceived(12) AND
      NOT chip_comp/CommandReceived(15) AND chip_comp/CommandReceived(8) AND
      NOT chip_comp/CommandReceived(4) AND NOT chip_comp/CommandReceived(5) AND
      chip_comp/CommandReceived(6) AND NOT chip_comp/CommandReceived(7) AND
      chip_comp/TXMAINSTATE_FFd1);

FDCPE_chip_comp/ENABLEn_BReg2: FDCPE port map (chip_comp/ENABLEn_BReg(2),chip_comp/CommandReceived(2),CLK_40MHZ,POR,'0',chip_comp/ENABLEn_BReg_CE(2));
     chip_comp/ENABLEn_BReg_CE(2) <= (NOT chip_comp/RunningFlag AND
      NOT chip_comp/CommandReceived(10) AND NOT chip_comp/CommandReceived(13) AND
      NOT chip_comp/CommandReceived(14) AND NOT chip_comp/CommandReceived(9) AND
      NOT chip_comp/CommandReceived(11) AND NOT chip_comp/CommandReceived(12) AND
      NOT chip_comp/CommandReceived(15) AND chip_comp/CommandReceived(8) AND
      NOT chip_comp/CommandReceived(4) AND NOT chip_comp/CommandReceived(5) AND
      chip_comp/CommandReceived(6) AND NOT chip_comp/CommandReceived(7) AND
      chip_comp/TXMAINSTATE_FFd1);

FDCPE_chip_comp/ENABLEn_BReg3: FDCPE port map (chip_comp/ENABLEn_BReg(3),chip_comp/CommandReceived(3),CLK_40MHZ,POR,'0',chip_comp/ENABLEn_BReg_CE(3));
     chip_comp/ENABLEn_BReg_CE(3) <= (NOT chip_comp/RunningFlag AND
      NOT chip_comp/CommandReceived(10) AND NOT chip_comp/CommandReceived(13) AND
      NOT chip_comp/CommandReceived(14) AND NOT chip_comp/CommandReceived(9) AND
      NOT chip_comp/CommandReceived(11) AND NOT chip_comp/CommandReceived(12) AND
      NOT chip_comp/CommandReceived(15) AND chip_comp/CommandReceived(8) AND
      NOT chip_comp/CommandReceived(4) AND NOT chip_comp/CommandReceived(5) AND
      chip_comp/CommandReceived(6) AND NOT chip_comp/CommandReceived(7) AND
      chip_comp/TXMAINSTATE_FFd1);

FTCPE_chip_comp/GenDataCMD: FTCPE port map (chip_comp/GenDataCMD,chip_comp/GenDataCMD_T,CLK_40MHZ,POR,'0');
     chip_comp/GenDataCMD_T <= ((chip_comp/GenDataCMD AND NOT chip_comp/TXMAINSTATE_FFd1 AND
      NOT chip_comp/TXMAINSTATE_FFd2)
      OR (chip_comp/CommandReceived(10) AND
      chip_comp/CommandReceived(13) AND chip_comp/CommandReceived(14) AND
      chip_comp/CommandReceived(9) AND NOT chip_comp/CommandReceived(11) AND
      NOT chip_comp/CommandReceived(12) AND NOT chip_comp/CommandReceived(15) AND
      chip_comp/CommandReceived(8) AND NOT chip_comp/GenDataCMD AND chip_comp/TXMAINSTATE_FFd1));

FDCPE_chip_comp/GenDataCounter0: FDCPE port map (chip_comp/GenDataCounter(0),chip_comp/GenDataCounter_D(0),CLK_40MHZ,POR,'0');
chip_comp/GenDataCounter_D(0) <= (chip_comp/GenDatasig AND
NOT chip_comp/GenDataCounter(0));

FDCPE_chip_comp/GenDataCounter1: FDCPE port map (chip_comp/GenDataCounter(1),chip_comp/GenDataCounter_D(1),CLK_40MHZ,POR,'0');
     chip_comp/GenDataCounter_D(1) <= ((chip_comp/GenDatasig AND
      chip_comp/GenDataCounter(0) AND NOT chip_comp/GenDataCounter(1))
      OR (chip_comp/GenDatasig AND
      NOT chip_comp/GenDataCounter(0) AND chip_comp/GenDataCounter(1)));

FTCPE_chip_comp/GenDataCounter2: FTCPE port map (chip_comp/GenDataCounter(2),chip_comp/GenDataCounter_T(2),CLK_40MHZ,POR,'0');
     chip_comp/GenDataCounter_T(2) <= ((NOT chip_comp/GenDatasig AND
      chip_comp/GenDataCounter(2))
      OR (chip_comp/GenDatasig AND
      chip_comp/GenDataCounter(0) AND chip_comp/GenDataCounter(1)));

FTCPE_chip_comp/GenDataCounter3: FTCPE port map (chip_comp/GenDataCounter(3),chip_comp/GenDataCounter_T(3),CLK_40MHZ,POR,'0');
     chip_comp/GenDataCounter_T(3) <= ((NOT chip_comp/GenDatasig AND
      chip_comp/GenDataCounter(3))
      OR (chip_comp/GenDatasig AND
      chip_comp/GenDataCounter(0) AND chip_comp/GenDataCounter(1) AND
      chip_comp/GenDataCounter(2)));

FTCPE_chip_comp/GenDataCounter4: FTCPE port map (chip_comp/GenDataCounter(4),chip_comp/GenDataCounter_T(4),CLK_40MHZ,POR,'0');
     chip_comp/GenDataCounter_T(4) <= ((NOT chip_comp/GenDatasig AND
      chip_comp/GenDataCounter(4))
      OR (chip_comp/GenDatasig AND
      chip_comp/GenDataCounter(0) AND chip_comp/GenDataCounter(1) AND
      chip_comp/GenDataCounter(2) AND chip_comp/GenDataCounter(3)));

FTCPE_chip_comp/GenDataCounter5: FTCPE port map (chip_comp/GenDataCounter(5),chip_comp/GenDataCounter_T(5),CLK_40MHZ,POR,'0');
     chip_comp/GenDataCounter_T(5) <= ((NOT chip_comp/GenDatasig AND
      chip_comp/GenDataCounter(5))
      OR (chip_comp/GenDatasig AND
      chip_comp/GenDataCounter(0) AND chip_comp/GenDataCounter(1) AND
      chip_comp/GenDataCounter(2) AND chip_comp/GenDataCounter(3) AND
      chip_comp/GenDataCounter(4)));

FTCPE_chip_comp/GenDataCounter6: FTCPE port map (chip_comp/GenDataCounter(6),chip_comp/GenDataCounter_T(6),CLK_40MHZ,POR,'0');
     chip_comp/GenDataCounter_T(6) <= ((NOT chip_comp/GenDatasig AND
      chip_comp/GenDataCounter(6))
      OR (chip_comp/GenDatasig AND
      chip_comp/GenDataCounter(0) AND chip_comp/GenDataCounter(1) AND
      chip_comp/GenDataCounter(2) AND chip_comp/GenDataCounter(3) AND
      chip_comp/GenDataCounter(4) AND chip_comp/GenDataCounter(5)));

FTCPE_chip_comp/GenDataCounter7: FTCPE port map (chip_comp/GenDataCounter(7),chip_comp/GenDataCounter_T(7),CLK_40MHZ,POR,'0');
     chip_comp/GenDataCounter_T(7) <= ((NOT chip_comp/GenDatasig AND
      chip_comp/GenDataCounter(7))
      OR (chip_comp/GenDatasig AND
      chip_comp/GenDataCounter(0) AND chip_comp/GenDataCounter(1) AND
      chip_comp/GenDataCounter(2) AND chip_comp/GenDataCounter(3) AND
      chip_comp/GenDataCounter(4) AND chip_comp/GenDataCounter(5) AND
      chip_comp/GenDataCounter(6)));

FTCPE_chip_comp/GenDataCounter8: FTCPE port map (chip_comp/GenDataCounter(8),chip_comp/GenDataCounter_T(8),CLK_40MHZ,POR,'0');
     chip_comp/GenDataCounter_T(8) <= ((NOT chip_comp/GenDatasig AND
      chip_comp/GenDataCounter(8))
      OR (chip_comp/GenDatasig AND
      chip_comp/GenDataCounter(0) AND chip_comp/GenDataCounter(1) AND
      chip_comp/GenDataCounter(2) AND chip_comp/GenDataCounter(3) AND
      chip_comp/GenDataCounter(4) AND chip_comp/GenDataCounter(5) AND
      chip_comp/GenDataCounter(6) AND chip_comp/GenDataCounter(7)));

FTCPE_chip_comp/GenDataCounter9: FTCPE port map (chip_comp/GenDataCounter(9),chip_comp/GenDataCounter_T(9),CLK_40MHZ,POR,'0');
     chip_comp/GenDataCounter_T(9) <= ((NOT chip_comp/GenDatasig AND
      chip_comp/GenDataCounter(9))
      OR (chip_comp/GenDatasig AND
      chip_comp/GenDataCounter(0) AND chip_comp/GenDataCounter(1) AND
      chip_comp/GenDataCounter(2) AND chip_comp/GenDataCounter(3) AND
      chip_comp/GenDataCounter(4) AND chip_comp/GenDataCounter(5) AND
      chip_comp/GenDataCounter(6) AND chip_comp/GenDataCounter(7) AND
      chip_comp/GenDataCounter(8)));

FTCPE_chip_comp/GenDataCounter10: FTCPE port map (chip_comp/GenDataCounter(10),chip_comp/GenDataCounter_T(10),CLK_40MHZ,POR,'0');
     chip_comp/GenDataCounter_T(10) <= ((NOT chip_comp/GenDatasig AND
      chip_comp/GenDataCounter(10))
      OR (chip_comp/GenDatasig AND
      chip_comp/GenDataCounter(0) AND chip_comp/GenDataCounter(1) AND
      chip_comp/GenDataCounter(2) AND chip_comp/GenDataCounter(3) AND
      chip_comp/GenDataCounter(4) AND chip_comp/GenDataCounter(5) AND
      chip_comp/GenDataCounter(6) AND chip_comp/GenDataCounter(7) AND
      chip_comp/GenDataCounter(8) AND chip_comp/GenDataCounter(9)));

FTCPE_chip_comp/GenDataCounter11: FTCPE port map (chip_comp/GenDataCounter(11),chip_comp/GenDataCounter_T(11),CLK_40MHZ,POR,'0');
     chip_comp/GenDataCounter_T(11) <= ((NOT chip_comp/GenDatasig AND
      chip_comp/GenDataCounter(11))
      OR (chip_comp/GenDatasig AND
      chip_comp/GenDataCounter(0) AND chip_comp/GenDataCounter(10) AND
      chip_comp/GenDataCounter(1) AND chip_comp/GenDataCounter(2) AND
      chip_comp/GenDataCounter(3) AND chip_comp/GenDataCounter(4) AND
      chip_comp/GenDataCounter(5) AND chip_comp/GenDataCounter(6) AND
      chip_comp/GenDataCounter(7) AND chip_comp/GenDataCounter(8) AND
      chip_comp/GenDataCounter(9)));

FTCPE_chip_comp/GenDataCounter12: FTCPE port map (chip_comp/GenDataCounter(12),chip_comp/GenDataCounter_T(12),CLK_40MHZ,POR,'0');
     chip_comp/GenDataCounter_T(12) <= ((NOT chip_comp/GenDatasig AND
      chip_comp/GenDataCounter(12))
      OR (chip_comp/GenDatasig AND
      chip_comp/GenDataCounter(0) AND chip_comp/GenDataCounter(10) AND
      chip_comp/GenDataCounter(11) AND chip_comp/GenDataCounter(1) AND
      chip_comp/GenDataCounter(2) AND chip_comp/GenDataCounter(3) AND
      chip_comp/GenDataCounter(4) AND chip_comp/GenDataCounter(5) AND
      chip_comp/GenDataCounter(6) AND chip_comp/GenDataCounter(7) AND
      chip_comp/GenDataCounter(8) AND chip_comp/GenDataCounter(9)));

FTCPE_chip_comp/GenDataCounter13: FTCPE port map (chip_comp/GenDataCounter(13),chip_comp/GenDataCounter_T(13),CLK_40MHZ,POR,'0');
     chip_comp/GenDataCounter_T(13) <= ((NOT chip_comp/GenDatasig AND
      chip_comp/GenDataCounter(13))
      OR (chip_comp/GenDatasig AND
      chip_comp/GenDataCounter(0) AND chip_comp/GenDataCounter(10) AND
      chip_comp/GenDataCounter(11) AND chip_comp/GenDataCounter(12) AND
      chip_comp/GenDataCounter(1) AND chip_comp/GenDataCounter(2) AND
      chip_comp/GenDataCounter(3) AND chip_comp/GenDataCounter(4) AND
      chip_comp/GenDataCounter(5) AND chip_comp/GenDataCounter(6) AND
      chip_comp/GenDataCounter(7) AND chip_comp/GenDataCounter(8) AND
      chip_comp/GenDataCounter(9)));

FTCPE_chip_comp/GenDataCounter14: FTCPE port map (chip_comp/GenDataCounter(14),chip_comp/GenDataCounter_T(14),CLK_40MHZ,POR,'0');
     chip_comp/GenDataCounter_T(14) <= ((NOT chip_comp/GenDatasig AND
      chip_comp/GenDataCounter(14))
      OR (chip_comp/GenDatasig AND
      chip_comp/GenDataCounter(0) AND chip_comp/GenDataCounter(10) AND
      chip_comp/GenDataCounter(11) AND chip_comp/GenDataCounter(12) AND
      chip_comp/GenDataCounter(13) AND chip_comp/GenDataCounter(1) AND
      chip_comp/GenDataCounter(2) AND chip_comp/GenDataCounter(3) AND
      chip_comp/GenDataCounter(4) AND chip_comp/GenDataCounter(5) AND
      chip_comp/GenDataCounter(6) AND chip_comp/GenDataCounter(7) AND
      chip_comp/GenDataCounter(8) AND chip_comp/GenDataCounter(9)));

FTCPE_chip_comp/GenDataCounter15: FTCPE port map (chip_comp/GenDataCounter(15),chip_comp/GenDataCounter_T(15),CLK_40MHZ,POR,'0');
     chip_comp/GenDataCounter_T(15) <= ((NOT chip_comp/GenDatasig AND
      chip_comp/GenDataCounter(15))
      OR (chip_comp/GenDatasig AND
      chip_comp/GenDataCounter(0) AND chip_comp/GenDataCounter(10) AND
      chip_comp/GenDataCounter(11) AND chip_comp/GenDataCounter(12) AND
      chip_comp/GenDataCounter(13) AND chip_comp/GenDataCounter(14) AND
      chip_comp/GenDataCounter(1) AND chip_comp/GenDataCounter(2) AND
      chip_comp/GenDataCounter(3) AND chip_comp/GenDataCounter(4) AND
      chip_comp/GenDataCounter(5) AND chip_comp/GenDataCounter(6) AND
      chip_comp/GenDataCounter(7) AND chip_comp/GenDataCounter(8) AND
      chip_comp/GenDataCounter(9)));

FDCPE_chip_comp/GenDataDonesig: FDCPE port map (chip_comp/GenDataDonesig,chip_comp/GenDataDonesig_D,CLK_40MHZ,POR,'0');
     chip_comp/GenDataDonesig_D <= (NOT chip_comp/GenDataCounter(0) AND
      chip_comp/GenDataCounter(10) AND chip_comp/GenDataCounter(11) AND
      NOT chip_comp/GenDataCounter(12) AND NOT chip_comp/GenDataCounter(13) AND
      NOT chip_comp/GenDataCounter(14) AND chip_comp/GenDataCounter(1) AND
      chip_comp/GenDataCounter(2) AND chip_comp/GenDataCounter(3) AND
      chip_comp/GenDataCounter(4) AND chip_comp/GenDataCounter(5) AND
      chip_comp/GenDataCounter(6) AND chip_comp/GenDataCounter(7) AND
      chip_comp/GenDataCounter(8) AND chip_comp/GenDataCounter(9) AND
      NOT chip_comp/GenDataCounter(15));

FDCPE_chip_comp/GenDatasig: FDCPE port map (chip_comp/GenDatasig,chip_comp/GenDatasig_D,CLK_40MHZ,POR,'0');
     chip_comp/GenDatasig_D <= ((Datasig(3).EXP)
      OR (HFn_B(3) AND NOT chip_comp/TXREADOUTSTATE_FFd3 AND
      NOT chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2)
      OR (NOT chip_comp/TXREADOUTSTATE_FFd3 AND
      NOT chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND
      NOT chip_comp/TXREADOUTSTATE_FFd1)
      OR (HFn_B(2) AND chip_comp/TXREADOUTSTATE_FFd3 AND
      NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND
      NOT chip_comp/TXREADOUTSTATE_FFd1)
      OR (HFn_B(1) AND chip_comp/TXREADOUTSTATE_FFd3 AND
      chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND
      NOT chip_comp/TXREADOUTSTATE_FFd1));

FDCPE_chip_comp/LinkStablished: FDCPE port map (chip_comp/LinkStablished,chip_comp/LinkStablished_D,CLK_40MHZ,POR,'0');
     chip_comp/LinkStablished_D <= ((chip_comp/LinkStablished AND
      chip_comp/TXMAINSTATE_FFd1)
      OR (NOT chip_comp/TXMAINSTATE_FFd1 AND
      NOT chip_comp/TXMAINSTATE_FFd2));

FDCPE_chip_comp/ReceiveCommandComp/clr_sr: FDCPE port map (chip_comp/ReceiveCommandComp/clr_sr,chip_comp/ReceiveCommandComp/clr_sr_D,CLK_40MHZ,POR,'0');
     chip_comp/ReceiveCommandComp/clr_sr_D <= (chip_comp/ReceiveCommandComp/sr(1) AND
      NOT chip_comp/ReceiveCommandComp/sr(2) AND chip_comp/ReceiveCommandComp/sr(3) AND
      chip_comp/ReceiveCommandComp/sr(0));

FDCPE_chip_comp/ReceiveCommandComp/sr0: FDCPE port map (chip_comp/ReceiveCommandComp/sr(0),chip_comp/ReceiveCommandComp/sr_D(0),NOT CLK_40MHZ,POR,'0');
chip_comp/ReceiveCommandComp/sr_D(0) <= (NOT chip_comp/ReceiveCommandComp/clr_sr AND
chip_comp/ReceiveCommandComp/sr(1));

FDCPE_chip_comp/ReceiveCommandComp/sr1: FDCPE port map (chip_comp/ReceiveCommandComp/sr(1),chip_comp/ReceiveCommandComp/sr_D(1),NOT CLK_40MHZ,POR,'0');
chip_comp/ReceiveCommandComp/sr_D(1) <= (NOT chip_comp/ReceiveCommandComp/clr_sr AND
chip_comp/ReceiveCommandComp/sr(2));

FDCPE_chip_comp/ReceiveCommandComp/sr2: FDCPE port map (chip_comp/ReceiveCommandComp/sr(2),chip_comp/ReceiveCommandComp/sr_D(2),NOT CLK_40MHZ,POR,'0');
chip_comp/ReceiveCommandComp/sr_D(2) <= (NOT chip_comp/ReceiveCommandComp/clr_sr AND
chip_comp/ReceiveCommandComp/sr(3));

FDCPE_chip_comp/ReceiveCommandComp/sr3: FDCPE port map (chip_comp/ReceiveCommandComp/sr(3),chip_comp/ReceiveCommandComp/sr_D(3),NOT CLK_40MHZ,POR,'0');
chip_comp/ReceiveCommandComp/sr_D(3) <= (NOT chip_comp/ReceiveCommandComp/clr_sr AND
chip_comp/ReceiveCommandComp/sr(4));

FDCPE_chip_comp/ReceiveCommandComp/sr4: FDCPE port map (chip_comp/ReceiveCommandComp/sr(4),chip_comp/ReceiveCommandComp/sr_D(4),NOT CLK_40MHZ,POR,'0');
chip_comp/ReceiveCommandComp/sr_D(4) <= (NOT chip_comp/ReceiveCommandComp/clr_sr AND
chip_comp/ReceiveCommandComp/sr(5));

FDCPE_chip_comp/ReceiveCommandComp/sr5: FDCPE port map (chip_comp/ReceiveCommandComp/sr(5),chip_comp/ReceiveCommandComp/sr_D(5),NOT CLK_40MHZ,POR,'0');
chip_comp/ReceiveCommandComp/sr_D(5) <= (NOT chip_comp/ReceiveCommandComp/clr_sr AND
chip_comp/ReceiveCommandComp/sr(6));

FDCPE_chip_comp/ReceiveCommandComp/sr6: FDCPE port map (chip_comp/ReceiveCommandComp/sr(6),chip_comp/ReceiveCommandComp/sr_D(6),NOT CLK_40MHZ,POR,'0');
chip_comp/ReceiveCommandComp/sr_D(6) <= (NOT chip_comp/ReceiveCommandComp/clr_sr AND
chip_comp/ReceiveCommandComp/sr(7));

FDCPE_chip_comp/ReceiveCommandComp/sr7: FDCPE port map (chip_comp/ReceiveCommandComp/sr(7),chip_comp/ReceiveCommandComp/sr_D(7),NOT CLK_40MHZ,POR,'0');
chip_comp/ReceiveCommandComp/sr_D(7) <= (NOT chip_comp/ReceiveCommandComp/clr_sr AND
chip_comp/ReceiveCommandComp/sr(8));

FDCPE_chip_comp/ReceiveCommandComp/sr8: FDCPE port map (chip_comp/ReceiveCommandComp/sr(8),chip_comp/ReceiveCommandComp/sr_D(8),NOT CLK_40MHZ,POR,'0');
chip_comp/ReceiveCommandComp/sr_D(8) <= (NOT chip_comp/ReceiveCommandComp/clr_sr AND
chip_comp/ReceiveCommandComp/sr(9));

FDCPE_chip_comp/ReceiveCommandComp/sr9: FDCPE port map (chip_comp/ReceiveCommandComp/sr(9),chip_comp/ReceiveCommandComp/sr_D(9),NOT CLK_40MHZ,POR,'0');
chip_comp/ReceiveCommandComp/sr_D(9) <= (NOT chip_comp/ReceiveCommandComp/clr_sr AND
chip_comp/ReceiveCommandComp/sr(10));

FDCPE_chip_comp/ReceiveCommandComp/sr10: FDCPE port map (chip_comp/ReceiveCommandComp/sr(10),chip_comp/ReceiveCommandComp/sr_D(10),NOT CLK_40MHZ,POR,'0');
chip_comp/ReceiveCommandComp/sr_D(10) <= (NOT chip_comp/ReceiveCommandComp/clr_sr AND
chip_comp/ReceiveCommandComp/sr(11));

FDCPE_chip_comp/ReceiveCommandComp/sr11: FDCPE port map (chip_comp/ReceiveCommandComp/sr(11),chip_comp/ReceiveCommandComp/sr_D(11),NOT CLK_40MHZ,POR,'0');
chip_comp/ReceiveCommandComp/sr_D(11) <= (NOT chip_comp/ReceiveCommandComp/clr_sr AND
chip_comp/ReceiveCommandComp/sr(12));

FDCPE_chip_comp/ReceiveCommandComp/sr12: FDCPE port map (chip_comp/ReceiveCommandComp/sr(12),chip_comp/ReceiveCommandComp/sr_D(12),NOT CLK_40MHZ,POR,'0');
chip_comp/ReceiveCommandComp/sr_D(12) <= (NOT chip_comp/ReceiveCommandComp/clr_sr AND
chip_comp/ReceiveCommandComp/sr(13));

FDCPE_chip_comp/ReceiveCommandComp/sr13: FDCPE port map (chip_comp/ReceiveCommandComp/sr(13),chip_comp/ReceiveCommandComp/sr_D(13),NOT CLK_40MHZ,POR,'0');
chip_comp/ReceiveCommandComp/sr_D(13) <= (NOT chip_comp/ReceiveCommandComp/clr_sr AND
chip_comp/ReceiveCommandComp/sr(14));

FDCPE_chip_comp/ReceiveCommandComp/sr14: FDCPE port map (chip_comp/ReceiveCommandComp/sr(14),chip_comp/ReceiveCommandComp/sr_D(14),NOT CLK_40MHZ,POR,'0');
chip_comp/ReceiveCommandComp/sr_D(14) <= (NOT chip_comp/ReceiveCommandComp/clr_sr AND
chip_comp/ReceiveCommandComp/sr(15));

FDCPE_chip_comp/ReceiveCommandComp/sr15: FDCPE port map (chip_comp/ReceiveCommandComp/sr(15),chip_comp/ReceiveCommandComp/sr_D(15),NOT CLK_40MHZ,POR,'0');
chip_comp/ReceiveCommandComp/sr_D(15) <= (NOT chip_comp/ReceiveCommandComp/clr_sr AND
chip_comp/ReceiveCommandComp/sr(16));

FDCPE_chip_comp/ReceiveCommandComp/sr16: FDCPE port map (chip_comp/ReceiveCommandComp/sr(16),chip_comp/ReceiveCommandComp/sr_D(16),NOT CLK_40MHZ,POR,'0');
chip_comp/ReceiveCommandComp/sr_D(16) <= (NOT chip_comp/ReceiveCommandComp/clr_sr AND
chip_comp/ReceiveCommandComp/sr(17));

FDCPE_chip_comp/ReceiveCommandComp/sr17: FDCPE port map (chip_comp/ReceiveCommandComp/sr(17),chip_comp/ReceiveCommandComp/sr_D(17),NOT CLK_40MHZ,POR,'0');
chip_comp/ReceiveCommandComp/sr_D(17) <= (NOT chip_comp/ReceiveCommandComp/clr_sr AND
chip_comp/ReceiveCommandComp/sr(18));

FDCPE_chip_comp/ReceiveCommandComp/sr18: FDCPE port map (chip_comp/ReceiveCommandComp/sr(18),chip_comp/ReceiveCommandComp/sr_D(18),NOT CLK_40MHZ,POR,'0');
chip_comp/ReceiveCommandComp/sr_D(18) <= (NOT chip_comp/ReceiveCommandComp/clr_sr AND
chip_comp/ReceiveCommandComp/sr(19));

FDCPE_chip_comp/ReceiveCommandComp/sr19: FDCPE port map (chip_comp/ReceiveCommandComp/sr(19),chip_comp/ReceiveCommandComp/sr_D(19),NOT CLK_40MHZ,POR,'0');
chip_comp/ReceiveCommandComp/sr_D(19) <= (NOT chip_comp/ReceiveCommandComp/clr_sr AND
chip_comp/ReceiveCommandComp/sr(20));

FDCPE_chip_comp/ReceiveCommandComp/sr20: FDCPE port map (chip_comp/ReceiveCommandComp/sr(20),chip_comp/ReceiveCommandComp/sr_D(20),NOT CLK_40MHZ,POR,'0');
chip_comp/ReceiveCommandComp/sr_D(20) <= (NOT chip_comp/ReceiveCommandComp/clr_sr AND CTRL);

FTCPE_chip_comp/RunningFlag: FTCPE port map (chip_comp/RunningFlag,chip_comp/RunningFlag_T,CLK_40MHZ,POR,'0',chip_comp/TXMAINSTATE_FFd1);
     chip_comp/RunningFlag_T <= ((chip_comp/RunningFlag AND
      NOT chip_comp/CommandReceived(10) AND NOT chip_comp/CommandReceived(13) AND
      NOT chip_comp/CommandReceived(14) AND chip_comp/CommandReceived(9) AND
      NOT chip_comp/CommandReceived(11) AND NOT chip_comp/CommandReceived(12) AND
      NOT chip_comp/CommandReceived(15) AND chip_comp/CommandReceived(8))
      OR (NOT chip_comp/RunningFlag AND
      NOT chip_comp/CommandReceived(10) AND NOT chip_comp/CommandReceived(13) AND
      NOT chip_comp/CommandReceived(14) AND chip_comp/CommandReceived(9) AND
      NOT chip_comp/CommandReceived(11) AND NOT chip_comp/CommandReceived(12) AND
      NOT chip_comp/CommandReceived(15) AND NOT chip_comp/CommandReceived(8)));

FDCPE_chip_comp/SamplingClock0: FDCPE port map (chip_comp/SamplingClock(0),chip_comp/CommandReceived(0),CLK_40MHZ,POR,'0',chip_comp/SamplingClock_CE(0));
     chip_comp/SamplingClock_CE(0) <= (NOT chip_comp/CommandReceived(10) AND
      NOT chip_comp/CommandReceived(13) AND NOT chip_comp/CommandReceived(14) AND
      NOT chip_comp/CommandReceived(9) AND chip_comp/CommandReceived(11) AND
      NOT chip_comp/CommandReceived(12) AND NOT chip_comp/CommandReceived(15) AND
      chip_comp/CommandReceived(8) AND chip_comp/TXMAINSTATE_FFd1);

FDCPE_chip_comp/SamplingClock1: FDCPE port map (chip_comp/SamplingClock(1),chip_comp/CommandReceived(1),CLK_40MHZ,POR,'0',chip_comp/SamplingClock_CE(1));
     chip_comp/SamplingClock_CE(1) <= (NOT chip_comp/CommandReceived(10) AND
      NOT chip_comp/CommandReceived(13) AND NOT chip_comp/CommandReceived(14) AND
      NOT chip_comp/CommandReceived(9) AND chip_comp/CommandReceived(11) AND
      NOT chip_comp/CommandReceived(12) AND NOT chip_comp/CommandReceived(15) AND
      chip_comp/CommandReceived(8) AND chip_comp/TXMAINSTATE_FFd1);

FDCPE_chip_comp/SimulData0: FDCPE port map (chip_comp/SimulData(0),chip_comp/GenDataCounter(0),CLK_40MHZ,POR,'0');

FDCPE_chip_comp/SimulData1: FDCPE port map (chip_comp/SimulData(1),chip_comp/GenDataCounter(1),CLK_40MHZ,POR,'0');

FDCPE_chip_comp/SimulData2: FDCPE port map (chip_comp/SimulData(2),chip_comp/GenDataCounter(2),CLK_40MHZ,POR,'0');

FDCPE_chip_comp/SimulData3: FDCPE port map (chip_comp/SimulData(3),chip_comp/GenDataCounter(3),CLK_40MHZ,POR,'0');

FDCPE_chip_comp/SimulData4: FDCPE port map (chip_comp/SimulData(4),chip_comp/GenDataCounter(4),CLK_40MHZ,POR,'0');

FDCPE_chip_comp/SimulData5: FDCPE port map (chip_comp/SimulData(5),chip_comp/GenDataCounter(5),CLK_40MHZ,POR,'0');

FDCPE_chip_comp/SimulData6: FDCPE port map (chip_comp/SimulData(6),chip_comp/GenDataCounter(6),CLK_40MHZ,POR,'0');

FDCPE_chip_comp/SimulData7: FDCPE port map (chip_comp/SimulData(7),chip_comp/GenDataCounter(7),CLK_40MHZ,POR,'0');

FDCPE_chip_comp/SimulData8: FDCPE port map (chip_comp/SimulData(8),chip_comp/GenDataCounter(8),CLK_40MHZ,POR,'0');

FDCPE_chip_comp/SimulData9: FDCPE port map (chip_comp/SimulData(9),chip_comp/GenDataCounter(9),CLK_40MHZ,POR,'0');

FDCPE_chip_comp/SimulData10: FDCPE port map (chip_comp/SimulData(10),chip_comp/GenDataCounter(10),CLK_40MHZ,POR,'0');

FDCPE_chip_comp/SimulData11: FDCPE port map (chip_comp/SimulData(11),chip_comp/GenDataCounter(11),CLK_40MHZ,POR,'0');

FDCPE_chip_comp/SimulData12: FDCPE port map (chip_comp/SimulData(12),chip_comp/GenDataCounter(12),CLK_40MHZ,POR,'0');

FDCPE_chip_comp/SimulData13: FDCPE port map (chip_comp/SimulData(13),chip_comp/GenDataCounter(13),CLK_40MHZ,POR,'0');

FDCPE_chip_comp/SimulData14: FDCPE port map (chip_comp/SimulData(14),chip_comp/GenDataCounter(14),CLK_40MHZ,POR,'0');

FDCPE_chip_comp/SimulData15: FDCPE port map (chip_comp/SimulData(15),chip_comp/GenDataCounter(15),CLK_40MHZ,POR,'0');

FDCPE_chip_comp/StatusDataSel0: FDCPE port map (chip_comp/StatusDataSel(0),chip_comp/CommandReceived(0),CLK_40MHZ,POR,'0',chip_comp/StatusDataSel_CE(0));
     chip_comp/StatusDataSel_CE(0) <= (chip_comp/CommandReceived(10) AND
      NOT chip_comp/CommandReceived(13) AND NOT chip_comp/CommandReceived(14) AND
      NOT chip_comp/CommandReceived(9) AND chip_comp/CommandReceived(11) AND
      NOT chip_comp/CommandReceived(12) AND NOT chip_comp/CommandReceived(15) AND
      NOT chip_comp/CommandReceived(8) AND chip_comp/TXMAINSTATE_FFd1);

FDCPE_chip_comp/StatusDataSel1: FDCPE port map (chip_comp/StatusDataSel(1),chip_comp/CommandReceived(1),CLK_40MHZ,POR,'0',chip_comp/StatusDataSel_CE(1));
     chip_comp/StatusDataSel_CE(1) <= (chip_comp/CommandReceived(10) AND
      NOT chip_comp/CommandReceived(13) AND NOT chip_comp/CommandReceived(14) AND
      NOT chip_comp/CommandReceived(9) AND chip_comp/CommandReceived(11) AND
      NOT chip_comp/CommandReceived(12) AND NOT chip_comp/CommandReceived(15) AND
      NOT chip_comp/CommandReceived(8) AND chip_comp/TXMAINSTATE_FFd1);

FDCPE_chip_comp/StatusDataSel2: FDCPE port map (chip_comp/StatusDataSel(2),chip_comp/CommandReceived(2),CLK_40MHZ,POR,'0',chip_comp/StatusDataSel_CE(2));
     chip_comp/StatusDataSel_CE(2) <= (chip_comp/CommandReceived(10) AND
      NOT chip_comp/CommandReceived(13) AND NOT chip_comp/CommandReceived(14) AND
      NOT chip_comp/CommandReceived(9) AND chip_comp/CommandReceived(11) AND
      NOT chip_comp/CommandReceived(12) AND NOT chip_comp/CommandReceived(15) AND
      NOT chip_comp/CommandReceived(8) AND chip_comp/TXMAINSTATE_FFd1);

FDCPE_chip_comp/StatusDataSel3: FDCPE port map (chip_comp/StatusDataSel(3),chip_comp/CommandReceived(3),CLK_40MHZ,POR,'0',chip_comp/StatusDataSel_CE(3));
     chip_comp/StatusDataSel_CE(3) <= (chip_comp/CommandReceived(10) AND
      NOT chip_comp/CommandReceived(13) AND NOT chip_comp/CommandReceived(14) AND
      NOT chip_comp/CommandReceived(9) AND chip_comp/CommandReceived(11) AND
      NOT chip_comp/CommandReceived(12) AND NOT chip_comp/CommandReceived(15) AND
      NOT chip_comp/CommandReceived(8) AND chip_comp/TXMAINSTATE_FFd1);

FDCPE_chip_comp/StatusDataSel4: FDCPE port map (chip_comp/StatusDataSel(4),chip_comp/CommandReceived(4),CLK_40MHZ,POR,'0',chip_comp/StatusDataSel_CE(4));
     chip_comp/StatusDataSel_CE(4) <= (chip_comp/CommandReceived(10) AND
      NOT chip_comp/CommandReceived(13) AND NOT chip_comp/CommandReceived(14) AND
      NOT chip_comp/CommandReceived(9) AND chip_comp/CommandReceived(11) AND
      NOT chip_comp/CommandReceived(12) AND NOT chip_comp/CommandReceived(15) AND
      NOT chip_comp/CommandReceived(8) AND chip_comp/TXMAINSTATE_FFd1);

FTCPE_chip_comp/TCLKCounter0: FTCPE port map (chip_comp/TCLKCounter(0),chip_comp/TCLKCounter_T(0),CLK_40MHZ,POR,'0');
     chip_comp/TCLKCounter_T(0) <= ((chip_comp/TimerInterval(2) AND
      chip_comp/TimerInterval(0) AND NOT chip_comp/TCLKCounter(0) AND
      NOT chip_comp/TCLKCounter(1) AND NOT chip_comp/TCLKCounter(2) AND
      NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND
      NOT chip_comp/TCLKCounter(5) AND NOT chip_comp/TCLKCounter(6) AND
      NOT chip_comp/TCLKCounter(7) AND NOT chip_comp/TCLKCounter(8) AND
      NOT chip_comp/TCLKCounter(9) AND NOT chip_comp/TCLKCounter(10))
      OR (chip_comp/TimerInterval(2) AND
      chip_comp/TimerInterval(1) AND NOT chip_comp/TCLKCounter(0) AND
      NOT chip_comp/TCLKCounter(1) AND NOT chip_comp/TCLKCounter(2) AND
      NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND
      NOT chip_comp/TCLKCounter(5) AND NOT chip_comp/TCLKCounter(6) AND
      NOT chip_comp/TCLKCounter(7) AND NOT chip_comp/TCLKCounter(8) AND
      NOT chip_comp/TCLKCounter(9) AND NOT chip_comp/TCLKCounter(10)));

FTCPE_chip_comp/TCLKCounter1: FTCPE port map (chip_comp/TCLKCounter(1),chip_comp/TCLKCounter_T(1),CLK_40MHZ,POR,'0');
     chip_comp/TCLKCounter_T(1) <= ((chip_comp/TCLKCounter(0))
      OR (chip_comp/TimerInterval(2) AND
      chip_comp/TimerInterval(0) AND NOT chip_comp/TCLKCounter(1) AND
      NOT chip_comp/TCLKCounter(2) AND NOT chip_comp/TCLKCounter(3) AND
      NOT chip_comp/TCLKCounter(4) AND NOT chip_comp/TCLKCounter(5) AND
      NOT chip_comp/TCLKCounter(6) AND NOT chip_comp/TCLKCounter(7) AND
      NOT chip_comp/TCLKCounter(8) AND NOT chip_comp/TCLKCounter(9) AND
      NOT chip_comp/TCLKCounter(10))
      OR (chip_comp/TimerInterval(2) AND
      chip_comp/TimerInterval(1) AND NOT chip_comp/TCLKCounter(1) AND
      NOT chip_comp/TCLKCounter(2) AND NOT chip_comp/TCLKCounter(3) AND
      NOT chip_comp/TCLKCounter(4) AND NOT chip_comp/TCLKCounter(5) AND
      NOT chip_comp/TCLKCounter(6) AND NOT chip_comp/TCLKCounter(7) AND
      NOT chip_comp/TCLKCounter(8) AND NOT chip_comp/TCLKCounter(9) AND
      NOT chip_comp/TCLKCounter(10)));

FTCPE_chip_comp/TCLKCounter2: FTCPE port map (chip_comp/TCLKCounter(2),chip_comp/TCLKCounter_T(2),CLK_40MHZ,POR,'0');
     chip_comp/TCLKCounter_T(2) <= ((chip_comp/TCLKCounter(0))
      OR (chip_comp/TCLKCounter(1))
      OR (chip_comp/TimerInterval(2) AND
      chip_comp/TimerInterval(0) AND NOT chip_comp/TCLKCounter(2) AND
      NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND
      NOT chip_comp/TCLKCounter(5) AND NOT chip_comp/TCLKCounter(6) AND
      NOT chip_comp/TCLKCounter(7) AND NOT chip_comp/TCLKCounter(8) AND
      NOT chip_comp/TCLKCounter(9) AND NOT chip_comp/TCLKCounter(10))
      OR (chip_comp/TimerInterval(2) AND
      chip_comp/TimerInterval(1) AND NOT chip_comp/TCLKCounter(2) AND
      NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND
      NOT chip_comp/TCLKCounter(5) AND NOT chip_comp/TCLKCounter(6) AND
      NOT chip_comp/TCLKCounter(7) AND NOT chip_comp/TCLKCounter(8) AND
      NOT chip_comp/TCLKCounter(9) AND NOT chip_comp/TCLKCounter(10))
      OR (NOT chip_comp/TimerInterval(2) AND
      NOT chip_comp/TimerInterval(0) AND NOT chip_comp/TimerInterval(1) AND
      NOT chip_comp/TCLKCounter(2) AND NOT chip_comp/TCLKCounter(3) AND
      NOT chip_comp/TCLKCounter(4) AND NOT chip_comp/TCLKCounter(5) AND
      NOT chip_comp/TCLKCounter(6) AND NOT chip_comp/TCLKCounter(7) AND
      NOT chip_comp/TCLKCounter(8) AND NOT chip_comp/TCLKCounter(9) AND
      NOT chip_comp/TCLKCounter(10)));

FTCPE_chip_comp/TCLKCounter3: FTCPE port map (chip_comp/TCLKCounter(3),chip_comp/TCLKCounter_T(3),CLK_40MHZ,POR,'0');
     chip_comp/TCLKCounter_T(3) <= ((chip_comp/TCLKCounter(0))
      OR (chip_comp/TCLKCounter(1))
      OR (chip_comp/TCLKCounter(2))
      OR (ACQENnB2sig(1).EXP)
      OR (chip_comp/TimerInterval(0) AND
      NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND
      NOT chip_comp/TCLKCounter(5) AND NOT chip_comp/TCLKCounter(6) AND
      NOT chip_comp/TCLKCounter(7) AND NOT chip_comp/TCLKCounter(8) AND
      NOT chip_comp/TCLKCounter(9) AND NOT chip_comp/TCLKCounter(10))
      OR (NOT chip_comp/TimerInterval(2) AND
      NOT chip_comp/TimerInterval(1) AND NOT chip_comp/TCLKCounter(3) AND
      NOT chip_comp/TCLKCounter(4) AND NOT chip_comp/TCLKCounter(5) AND
      NOT chip_comp/TCLKCounter(6) AND NOT chip_comp/TCLKCounter(7) AND
      NOT chip_comp/TCLKCounter(8) AND NOT chip_comp/TCLKCounter(9) AND
      NOT chip_comp/TCLKCounter(10)));

FTCPE_chip_comp/TCLKCounter4: FTCPE port map (chip_comp/TCLKCounter(4),chip_comp/TCLKCounter_T(4),CLK_40MHZ,POR,'0');
     chip_comp/TCLKCounter_T(4) <= ((chip_comp/TCLKCounter(0))
      OR (chip_comp/TCLKCounter(1))
      OR (chip_comp/TCLKCounter(2))
      OR (chip_comp/TCLKCounter(3))
      OR (chip_comp/TCLKCounter(0).EXP)
      OR (chip_comp/TimerInterval(0) AND
      NOT chip_comp/TCLKCounter(4) AND NOT chip_comp/TCLKCounter(5) AND
      NOT chip_comp/TCLKCounter(6) AND NOT chip_comp/TCLKCounter(7) AND
      NOT chip_comp/TCLKCounter(8) AND NOT chip_comp/TCLKCounter(9) AND
      NOT chip_comp/TCLKCounter(10)));

FTCPE_chip_comp/TCLKCounter5: FTCPE port map (chip_comp/TCLKCounter(5),chip_comp/TCLKCounter_T(5),CLK_40MHZ,POR,'0');
     chip_comp/TCLKCounter_T(5) <= ((TCLKsig.EXP)
      OR (ACLKsig.EXP)
      OR (NOT chip_comp/TCLKCounter(0) AND
      NOT chip_comp/TCLKCounter(1) AND NOT chip_comp/TCLKCounter(2) AND
      NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND
      chip_comp/TCLKCounter(5))
      OR (NOT chip_comp/TCLKCounter(0) AND
      NOT chip_comp/TCLKCounter(1) AND NOT chip_comp/TCLKCounter(2) AND
      NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND
      chip_comp/TCLKCounter(6))
      OR (NOT chip_comp/TCLKCounter(0) AND
      NOT chip_comp/TCLKCounter(1) AND NOT chip_comp/TCLKCounter(2) AND
      NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND
      chip_comp/TCLKCounter(7))
      OR (NOT chip_comp/TCLKCounter(0) AND
      NOT chip_comp/TCLKCounter(1) AND NOT chip_comp/TCLKCounter(2) AND
      NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND
      chip_comp/TCLKCounter(8))
      OR (NOT chip_comp/TCLKCounter(0) AND
      NOT chip_comp/TCLKCounter(1) AND NOT chip_comp/TCLKCounter(2) AND
      NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND
      chip_comp/TCLKCounter(9)));

FTCPE_chip_comp/TCLKCounter6: FTCPE port map (chip_comp/TCLKCounter(6),chip_comp/TCLKCounter_T(6),CLK_40MHZ,POR,'0');
     chip_comp/TCLKCounter_T(6) <= ((CLK_40MHZsig$BUF0.EXP)
      OR (NOT chip_comp/TCLKCounter(0) AND
      NOT chip_comp/TCLKCounter(1) AND NOT chip_comp/TCLKCounter(2) AND
      NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND
      NOT chip_comp/TCLKCounter(5) AND chip_comp/TCLKCounter(6))
      OR (NOT chip_comp/TCLKCounter(0) AND
      NOT chip_comp/TCLKCounter(1) AND NOT chip_comp/TCLKCounter(2) AND
      NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND
      NOT chip_comp/TCLKCounter(5) AND chip_comp/TCLKCounter(7))
      OR (NOT chip_comp/TCLKCounter(0) AND
      NOT chip_comp/TCLKCounter(1) AND NOT chip_comp/TCLKCounter(2) AND
      NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND
      NOT chip_comp/TCLKCounter(5) AND chip_comp/TCLKCounter(8))
      OR (NOT chip_comp/TCLKCounter(0) AND
      NOT chip_comp/TCLKCounter(1) AND NOT chip_comp/TCLKCounter(2) AND
      NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND
      NOT chip_comp/TCLKCounter(5) AND chip_comp/TCLKCounter(9))
      OR (NOT chip_comp/TCLKCounter(0) AND
      NOT chip_comp/TCLKCounter(1) AND NOT chip_comp/TCLKCounter(2) AND
      NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND
      NOT chip_comp/TCLKCounter(5) AND chip_comp/TCLKCounter(10)));

FTCPE_chip_comp/TCLKCounter7: FTCPE port map (chip_comp/TCLKCounter(7),chip_comp/TCLKCounter_T(7),CLK_40MHZ,POR,'0');
     chip_comp/TCLKCounter_T(7) <= ((ACQENnB3sig(1).EXP)
      OR (ACQENnB0sig(0).EXP)
      OR (NOT chip_comp/TCLKCounter(0) AND
      NOT chip_comp/TCLKCounter(1) AND NOT chip_comp/TCLKCounter(2) AND
      NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND
      NOT chip_comp/TCLKCounter(5) AND NOT chip_comp/TCLKCounter(6) AND
      chip_comp/TCLKCounter(7))
      OR (NOT chip_comp/TCLKCounter(0) AND
      NOT chip_comp/TCLKCounter(1) AND NOT chip_comp/TCLKCounter(2) AND
      NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND
      NOT chip_comp/TCLKCounter(5) AND NOT chip_comp/TCLKCounter(6) AND
      chip_comp/TCLKCounter(8))
      OR (NOT chip_comp/TCLKCounter(0) AND
      NOT chip_comp/TCLKCounter(1) AND NOT chip_comp/TCLKCounter(2) AND
      NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND
      NOT chip_comp/TCLKCounter(5) AND NOT chip_comp/TCLKCounter(6) AND
      chip_comp/TCLKCounter(9))
      OR (NOT chip_comp/TCLKCounter(0) AND
      NOT chip_comp/TCLKCounter(1) AND NOT chip_comp/TCLKCounter(2) AND
      NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND
      NOT chip_comp/TCLKCounter(5) AND NOT chip_comp/TCLKCounter(6) AND
      chip_comp/TCLKCounter(10))
      OR (NOT chip_comp/TimerInterval(2) AND
      chip_comp/TimerInterval(0) AND NOT chip_comp/TCLKCounter(0) AND
      NOT chip_comp/TCLKCounter(1) AND NOT chip_comp/TCLKCounter(2) AND
      NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND
      NOT chip_comp/TCLKCounter(5) AND NOT chip_comp/TCLKCounter(6)));

FTCPE_chip_comp/TCLKCounter8: FTCPE port map (chip_comp/TCLKCounter(8),chip_comp/TCLKCounter_T(8),CLK_40MHZ,POR,'0');
     chip_comp/TCLKCounter_T(8) <= ((NOT chip_comp/TCLKCounter(0) AND
      NOT chip_comp/TCLKCounter(1) AND NOT chip_comp/TCLKCounter(2) AND
      NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND
      NOT chip_comp/TCLKCounter(5) AND NOT chip_comp/TCLKCounter(6) AND
      NOT chip_comp/TCLKCounter(7) AND chip_comp/TCLKCounter(8))
      OR (NOT chip_comp/TCLKCounter(0) AND
      NOT chip_comp/TCLKCounter(1) AND NOT chip_comp/TCLKCounter(2) AND
      NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND
      NOT chip_comp/TCLKCounter(5) AND NOT chip_comp/TCLKCounter(6) AND
      NOT chip_comp/TCLKCounter(7) AND chip_comp/TCLKCounter(9))
      OR (NOT chip_comp/TCLKCounter(0) AND
      NOT chip_comp/TCLKCounter(1) AND NOT chip_comp/TCLKCounter(2) AND
      NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND
      NOT chip_comp/TCLKCounter(5) AND NOT chip_comp/TCLKCounter(6) AND
      NOT chip_comp/TCLKCounter(7) AND chip_comp/TCLKCounter(10))
      OR (NOT chip_comp/TimerInterval(2) AND
      chip_comp/TimerInterval(1) AND NOT chip_comp/TCLKCounter(0) AND
      NOT chip_comp/TCLKCounter(1) AND NOT chip_comp/TCLKCounter(2) AND
      NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND
      NOT chip_comp/TCLKCounter(5) AND NOT chip_comp/TCLKCounter(6) AND
      NOT chip_comp/TCLKCounter(7))
      OR (chip_comp/TimerInterval(2) AND
      NOT chip_comp/TimerInterval(0) AND NOT chip_comp/TimerInterval(1) AND
      NOT chip_comp/TCLKCounter(0) AND NOT chip_comp/TCLKCounter(1) AND
      NOT chip_comp/TCLKCounter(2) AND NOT chip_comp/TCLKCounter(3) AND
      NOT chip_comp/TCLKCounter(4) AND NOT chip_comp/TCLKCounter(5) AND
      NOT chip_comp/TCLKCounter(6) AND NOT chip_comp/TCLKCounter(7)));

FTCPE_chip_comp/TCLKCounter9: FTCPE port map (chip_comp/TCLKCounter(9),chip_comp/TCLKCounter_T(9),CLK_40MHZ,POR,'0');
     chip_comp/TCLKCounter_T(9) <= ((NOT chip_comp/TCLKCounter(0) AND
      NOT chip_comp/TCLKCounter(1) AND NOT chip_comp/TCLKCounter(2) AND
      NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND
      NOT chip_comp/TCLKCounter(5) AND NOT chip_comp/TCLKCounter(6) AND
      NOT chip_comp/TCLKCounter(7) AND NOT chip_comp/TCLKCounter(8) AND
      chip_comp/TCLKCounter(9))
      OR (NOT chip_comp/TCLKCounter(0) AND
      NOT chip_comp/TCLKCounter(1) AND NOT chip_comp/TCLKCounter(2) AND
      NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND
      NOT chip_comp/TCLKCounter(5) AND NOT chip_comp/TCLKCounter(6) AND
      NOT chip_comp/TCLKCounter(7) AND NOT chip_comp/TCLKCounter(8) AND
      chip_comp/TCLKCounter(10))
      OR (chip_comp/TimerInterval(2) AND
      NOT chip_comp/TimerInterval(0) AND NOT chip_comp/TimerInterval(1) AND
      NOT chip_comp/TCLKCounter(0) AND NOT chip_comp/TCLKCounter(1) AND
      NOT chip_comp/TCLKCounter(2) AND NOT chip_comp/TCLKCounter(3) AND
      NOT chip_comp/TCLKCounter(4) AND NOT chip_comp/TCLKCounter(5) AND
      NOT chip_comp/TCLKCounter(6) AND NOT chip_comp/TCLKCounter(7) AND
      NOT chip_comp/TCLKCounter(8))
      OR (NOT chip_comp/TimerInterval(2) AND
      chip_comp/TimerInterval(0) AND chip_comp/TimerInterval(1) AND
      NOT chip_comp/TCLKCounter(0) AND NOT chip_comp/TCLKCounter(1) AND
      NOT chip_comp/TCLKCounter(2) AND NOT chip_comp/TCLKCounter(3) AND
      NOT chip_comp/TCLKCounter(4) AND NOT chip_comp/TCLKCounter(5) AND
      NOT chip_comp/TCLKCounter(6) AND NOT chip_comp/TCLKCounter(7) AND
      NOT chip_comp/TCLKCounter(8)));

FTCPE_chip_comp/TCLKCounter10: FTCPE port map (chip_comp/TCLKCounter(10),chip_comp/TCLKCounter_T(10),CLK_40MHZ,POR,'0');
     chip_comp/TCLKCounter_T(10) <= ((NOT chip_comp/TCLKCounter(0) AND
      NOT chip_comp/TCLKCounter(1) AND NOT chip_comp/TCLKCounter(2) AND
      NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND
      NOT chip_comp/TCLKCounter(5) AND NOT chip_comp/TCLKCounter(6) AND
      NOT chip_comp/TCLKCounter(7) AND NOT chip_comp/TCLKCounter(8) AND
      NOT chip_comp/TCLKCounter(9) AND chip_comp/TCLKCounter(10))
      OR (chip_comp/TimerInterval(2) AND
      NOT chip_comp/TimerInterval(0) AND NOT chip_comp/TimerInterval(1) AND
      NOT chip_comp/TCLKCounter(0) AND NOT chip_comp/TCLKCounter(1) AND
      NOT chip_comp/TCLKCounter(2) AND NOT chip_comp/TCLKCounter(3) AND
      NOT chip_comp/TCLKCounter(4) AND NOT chip_comp/TCLKCounter(5) AND
      NOT chip_comp/TCLKCounter(6) AND NOT chip_comp/TCLKCounter(7) AND
      NOT chip_comp/TCLKCounter(8) AND NOT chip_comp/TCLKCounter(9)));

FDCPE_chip_comp/TCLKsig_1: FDCPE port map (chip_comp/TCLKsig_1,TCLK,CLK_40MHZ,POR,'0');

FDCPE_chip_comp/TXMAINSTATE_FFd1: FDCPE port map (chip_comp/TXMAINSTATE_FFd1,chip_comp/TXMAINSTATE_FFd1_D,CLK_40MHZ,POR,'0');
chip_comp/TXMAINSTATE_FFd1_D <= (NOT chip_comp/TXMAINSTATE_FFd1 AND
NOT chip_comp/TXMAINSTATE_FFd2 AND chip_comp/CommandAvailable AND LOCKED AND CTRL_OK);

FDCPE_chip_comp/TXMAINSTATE_FFd2: FDCPE port map (chip_comp/TXMAINSTATE_FFd2,chip_comp/TXMAINSTATE_FFd2_D,CLK_40MHZ,'0',POR);
chip_comp/TXMAINSTATE_FFd2_D <= ((NOT chip_comp/TXMAINSTATE_FFd1 AND NOT LOCKED)
OR (NOT chip_comp/TXMAINSTATE_FFd1 AND NOT CTRL_OK));

FTCPE_chip_comp/TXREADOUTSTATE_FFd1: FTCPE port map (chip_comp/TXREADOUTSTATE_FFd1,chip_comp/TXREADOUTSTATE_FFd1_T,CLK_40MHZ,POR,'0');
     chip_comp/TXREADOUTSTATE_FFd1_T <= ((HFn_B(3) AND NOT chip_comp/TXREADOUTSTATE_FFd3 AND
      NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd1)
      OR (chip_comp/TXREADOUTSTATE_FFd3 AND
      NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND
      NOT chip_comp/TXREADOUTSTATE_FFd1)
      OR (chip_comp/TXREADOUTSTATE_FFd3 AND
      NOT chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND
      chip_comp/TXREADOUTSTATE_FFd1 AND chip_comp/GenDataDonesig));

FDCPE_chip_comp/TXREADOUTSTATE_FFd2: FDCPE port map (chip_comp/TXREADOUTSTATE_FFd2,chip_comp/TXREADOUTSTATE_FFd2_D,CLK_40MHZ,POR,'0');
     chip_comp/TXREADOUTSTATE_FFd2_D <= ((RST4n_Bsig(0).EXP)
      OR (chip_comp/TXREADOUTSTATE_FFd3 AND
      chip_comp/TXREADOUTSTATE_FFd4)
      OR (NOT HFn_B(0) AND chip_comp/TXREADOUTSTATE_FFd4 AND
      chip_comp/TXREADOUTSTATE_FFd2)
      OR (NOT chip_comp/TXREADOUTSTATE_FFd3 AND
      NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND
      NOT chip_comp/GenDataDonesig));

FDCPE_chip_comp/TXREADOUTSTATE_FFd3: FDCPE port map (chip_comp/TXREADOUTSTATE_FFd3,chip_comp/TXREADOUTSTATE_FFd3_D,CLK_40MHZ,POR,'0');
     chip_comp/TXREADOUTSTATE_FFd3_D <= ((chip_comp/TXREADOUTSTATE_FFd1.EXP)
      OR (chip_comp/TXREADOUTSTATE_FFd3 AND
      chip_comp/TXREADOUTSTATE_FFd4)
      OR (HFn_B(0) AND chip_comp/TXREADOUTSTATE_FFd4 AND
      chip_comp/TXREADOUTSTATE_FFd2)
      OR (chip_comp/TXREADOUTSTATE_FFd3 AND
      chip_comp/TXREADOUTSTATE_FFd1 AND NOT chip_comp/GenDataDonesig)
      OR (NOT chip_comp/TXREADOUTSTATE_FFd3 AND
      NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND
      chip_comp/GenDataDonesig));

FDCPE_chip_comp/TXREADOUTSTATE_FFd4: FDCPE port map (chip_comp/TXREADOUTSTATE_FFd4,chip_comp/TXREADOUTSTATE_FFd4_D,CLK_40MHZ,POR,'0');
     chip_comp/TXREADOUTSTATE_FFd4_D <= ((EXP35_.EXP)
      OR (chip_comp/TXREADOUTSTATE_FFd4 AND
      chip_comp/TXREADOUTSTATE_FFd1 AND NOT chip_comp/GenDataDonesig)
      OR (NOT HFn_B(2) AND chip_comp/TXREADOUTSTATE_FFd3 AND
      NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2)
      OR (HFn_B(0) AND NOT chip_comp/TXREADOUTSTATE_FFd3 AND
      chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2));

FDCPE_chip_comp/TimerInterval0: FDCPE port map (chip_comp/TimerInterval(0),chip_comp/CommandReceived(0),CLK_40MHZ,'0',POR,chip_comp/TimerInterval_CE(0));
     chip_comp/TimerInterval_CE(0) <= (chip_comp/CommandReceived(10) AND
      NOT chip_comp/CommandReceived(13) AND NOT chip_comp/CommandReceived(14) AND
      chip_comp/CommandReceived(9) AND NOT chip_comp/CommandReceived(11) AND
      NOT chip_comp/CommandReceived(12) AND NOT chip_comp/CommandReceived(15) AND
      chip_comp/CommandReceived(8) AND chip_comp/TXMAINSTATE_FFd1);

FDCPE_chip_comp/TimerInterval1: FDCPE port map (chip_comp/TimerInterval(1),chip_comp/CommandReceived(1),CLK_40MHZ,POR,'0',chip_comp/TimerInterval_CE(1));
     chip_comp/TimerInterval_CE(1) <= (chip_comp/CommandReceived(10) AND
      NOT chip_comp/CommandReceived(13) AND NOT chip_comp/CommandReceived(14) AND
      chip_comp/CommandReceived(9) AND NOT chip_comp/CommandReceived(11) AND
      NOT chip_comp/CommandReceived(12) AND NOT chip_comp/CommandReceived(15) AND
      chip_comp/CommandReceived(8) AND chip_comp/TXMAINSTATE_FFd1);

FDCPE_chip_comp/TimerInterval2: FDCPE port map (chip_comp/TimerInterval(2),chip_comp/CommandReceived(2),CLK_40MHZ,POR,'0',chip_comp/TimerInterval_CE(2));
     chip_comp/TimerInterval_CE(2) <= (chip_comp/CommandReceived(10) AND
      NOT chip_comp/CommandReceived(13) AND NOT chip_comp/CommandReceived(14) AND
      chip_comp/CommandReceived(9) AND NOT chip_comp/CommandReceived(11) AND
      NOT chip_comp/CommandReceived(12) AND NOT chip_comp/CommandReceived(15) AND
      chip_comp/CommandReceived(8) AND chip_comp/TXMAINSTATE_FFd1);

FTCPE_chip_comp/TimerRestCMD: FTCPE port map (chip_comp/TimerRestCMD,chip_comp/TimerRestCMD_T,CLK_40MHZ,'0',POR);
     chip_comp/TimerRestCMD_T <= ((NOT chip_comp/TXMAINSTATE_FFd1 AND
      NOT chip_comp/TXMAINSTATE_FFd2 AND chip_comp/TimerRestCMD)
      OR (chip_comp/CommandReceived(10) AND
      NOT chip_comp/CommandReceived(13) AND NOT chip_comp/CommandReceived(14) AND
      NOT chip_comp/CommandReceived(9) AND NOT chip_comp/CommandReceived(11) AND
      NOT chip_comp/CommandReceived(12) AND NOT chip_comp/CommandReceived(15) AND
      NOT chip_comp/CommandReceived(8) AND chip_comp/TXMAINSTATE_FFd1 AND
      NOT chip_comp/TimerRestCMD));

uD_OEn_B(0) <= '1';

uD_OEn_B(1) <= '1';

uD_OEn_B(2) <= '1';

uD_OEn_B(3) <= '1';

uDw(0) <= '0';

uDw(1) <= '0';

uDw(2) <= '0';

uDw(3) <= '0';

uDw(4) <= '0';

uDw(5) <= '0';

uDw(6) <= '0';

uDw(7) <= '0';