----------------------------------------------------------------------------------
-- Company: 			LBNL
-- Engineer: 			Dionisio Doering
-- 
-- Create Date:    	14:21:26 01/31/2007 
-- Design Name: 		TX board
-- Module Name:    	top - Behavioral 
-- Project Name: 		SAO DAQ
-- Target Devices: 	XC95288XL-7TQ144
-- Tool versions: 	ISE 8.2
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;

entity top is
    Port ( 
				POR			: in  STD_LOGIC; -- RESET
				CLK_40MHZ	: in  STD_LOGIC; --Main clock
				CLK_40MHZ_OK: in  STD_LOGIC; --Status of main clock link
				CTRL			: in  STD_LOGIC; --Serial input for Control data
				CTRL_OK		: in  STD_LOGIC; --Status of the Control link
				LOCKED		: in  STD_LOGIC; --PLL of the GLINK is locked
				DATA			: out STD_LOGIC_VECTOR(15 downto 0); -- Data that will be transmitted
				HFn_B			: in  STD_LOGIC_VECTOR( 3 downto 0); --
				FFn_B			: in  STD_LOGIC_VECTOR( 3 downto 0); --
				RST_TIMERn	: out STD_LOGIC; --
				DAC_LOADn	: out STD_LOGIC; -- DAC Signals
				DAC_DIN		: out STD_LOGIC; -- DAC Signals
				DAC_SCLK		: out STD_LOGIC; -- DAC Signals
				DAC_CSn_B	: out STD_LOGIC_VECTOR( 3 downto 0); -- DAC Signals
				RST4n_B		: out STD_LOGIC_VECTOR( 3 downto 0); --
				RCLK4_B		: out STD_LOGIC_VECTOR( 3 downto 0); --
				D_OEn_B		: out STD_LOGIC_VECTOR( 3 downto 0); --
				ACQENnB0		: out STD_LOGIC_VECTOR( 3 downto 0); -- Acquire enable Board 0
				ACQENnB1		: out STD_LOGIC_VECTOR( 3 downto 0); -- Acquire enable Board 1
				ACQENnB2		: out STD_LOGIC_VECTOR( 3 downto 0); -- Acquire enable Board 2
				ACQENnB3		: out STD_LOGIC_VECTOR( 3 downto 0); -- Acquire enable Board 3
				ACLK			: out STD_LOGIC; -- Acquire clock
				RESETn		: out STD_LOGIC; --
				SYSCLK		: out STD_LOGIC; --
				ENABLEn_B	: out STD_LOGIC_VECTOR( 3 downto 0); --
				TCLK			: out STD_LOGIC; --
				RCLK3			: out STD_LOGIC; --
				ADCRST		: out STD_LOGIC; -- 
				TMODE			: out STD_LOGIC; --Trigger Mode (0 = with trigger; 1 = without trigger)
				DR0			: out STD_LOGIC; --Data Ratio
				DR1			: out STD_LOGIC; --Data Ratio
				PT0			: out STD_LOGIC; --Pre trigger
				PT1			: out STD_LOGIC; --Pre trigger
				uD_OEn_B		: out STD_LOGIC_VECTOR( 3 downto 0); --user defined enable
				uDw			: out STD_LOGIC_VECTOR( 7 downto 0); --user defined write
				uDr			: in  STD_LOGIC_VECTOR( 7 downto 0); --user defined read
				SYNCn			: out STD_LOGIC -- when high GLINK will send data, when low GLINK will send IDLE words
			 );
end top;

architecture Behavioral of top is
--------------------------------------------------------------------
-- Component Instantiation														--
--------------------------------------------------------------------
component chip is
    Port ( 	RST 			: in  STD_LOGIC; --POR			: in  STD_LOGIC; -- RESET
				CLK 			: in  STD_LOGIC; --CLK_40MHZ	: in  STD_LOGIC; --Main clock
				CLK_OK		: in  STD_LOGIC; --CLK_40MHZ_OK: in  STD_LOGIC; --Status of main clock link
				CTRL			: in  STD_LOGIC; --Serial input for Control data
				CTRL_OK		: in  STD_LOGIC; --Status of the Control link
				LOCKED		: in  STD_LOGIC; --PLL of the GLINK is locked
				DATA			: out STD_LOGIC_VECTOR(15 downto 0); -- Data that will be transmitted
				DATA_TS		: out STD_LOGIC; -- TS signal for Data (internal to CPLD)
				uDr			: in  STD_LOGIC_VECTOR( 7 downto 0); --
				HFn_B			: in  STD_LOGIC_VECTOR( 3 downto 0); --
				FFn_B			: in  STD_LOGIC_VECTOR( 3 downto 0); --
				RST_TIMERn	: out STD_LOGIC; --
				DAC_LOADn	: out STD_LOGIC; --
				DAC_DIN		: out STD_LOGIC; --
				DAC_SCLK		: out STD_LOGIC; --
				DAC_CSn_B	: out STD_LOGIC_VECTOR( 3 downto 0); --
				RST4n_B		: out STD_LOGIC_VECTOR( 3 downto 0); --
				RCLK4_B		: out STD_LOGIC_VECTOR( 3 downto 0); --
				D_OEn_B		: out STD_LOGIC_VECTOR( 3 downto 0); --
				ACQENnB0		: out STD_LOGIC_VECTOR( 3 downto 0); --
				ACQENnB1		: out STD_LOGIC_VECTOR( 3 downto 0); --
				ACQENnB2		: out STD_LOGIC_VECTOR( 3 downto 0); --
				ACQENnB3		: out STD_LOGIC_VECTOR( 3 downto 0); --
				RESETn		: out STD_LOGIC; --
				SYSCLK		: out STD_LOGIC; --
				ENABLEn_B	: out STD_LOGIC_VECTOR( 3 downto 0); --
				TCLK			: out STD_LOGIC; --
				ACLK			: out STD_LOGIC; --
				RCLK3			: out STD_LOGIC; --
				ADCRST		: out STD_LOGIC; --
				TMODE			: out STD_LOGIC; --
				DR0			: out STD_LOGIC; --
				DR1			: out STD_LOGIC; --
				PT0			: out STD_LOGIC; --
				PT1			: out STD_LOGIC; --
				uD_OEn_B		: out STD_LOGIC_VECTOR( 3 downto 0); --
				uDw			: out STD_LOGIC_VECTOR( 7 downto 0); --
				SYNCn			: out STD_LOGIC -- when high GLINK will send data, when low GLINK will send IDLE words
			 );
end component;
--------------------------------------------------------------------
-- Signal Declaration															--
--------------------------------------------------------------------
--input signals
signal RST			 		: STD_LOGIC;
signal CLK_40MHZsig 		: STD_LOGIC;
signal CLK_40MHZ_OKsig 	: STD_LOGIC;
signal CTRLsig 			: STD_LOGIC;
signal CTRL_OKsig 		: STD_LOGIC;
signal LOCKEDsig	 		: STD_LOGIC;
signal Datasig		 		: STD_LOGIC_VECTOR(15 downto 0);
signal DATA_TSsig	 		: STD_LOGIC;
signal HFn_Bsig	 		: STD_LOGIC_VECTOR(3 downto 0);
signal FFn_Bsig	 		: STD_LOGIC_VECTOR(3 downto 0);
signal RST_TIMERnsig		: STD_LOGIC;
signal RST4n_Bsig	 		: STD_LOGIC_VECTOR(3 downto 0);
signal RCLK4_Bsig	 		: STD_LOGIC_VECTOR(3 downto 0);
signal D_OEn_Bsig	 		: STD_LOGIC_VECTOR(3 downto 0);
signal ACQENnB0sig	 	: STD_LOGIC_VECTOR(3 downto 0);
signal ACQENnB1sig	 	: STD_LOGIC_VECTOR(3 downto 0);
signal ACQENnB2sig	 	: STD_LOGIC_VECTOR(3 downto 0);
signal ACQENnB3sig	 	: STD_LOGIC_VECTOR(3 downto 0);
signal RESETnsig			: STD_LOGIC;
signal SYSCLKsig			: STD_LOGIC;
signal ENABLEn_Bsig 		: STD_LOGIC_VECTOR(3 downto 0);
signal TCLKsig				: STD_LOGIC;
signal ACLKsig				: STD_LOGIC;
signal RCLK3sig			: STD_LOGIC;
signal ADCRSTsig			: STD_LOGIC;
signal TMODEsig			: STD_LOGIC;
signal DR0sig				: STD_LOGIC;
signal DR1sig				: STD_LOGIC;
signal PT0sig				: STD_LOGIC;
signal PT1sig				: STD_LOGIC;
signal uD_OEn_Bsig 		: STD_LOGIC_VECTOR(3 downto 0);
signal uDwsig 				: STD_LOGIC_VECTOR(7 downto 0);
signal uDrsig 				: STD_LOGIC_VECTOR(7 downto 0);
signal DAC_LOADnsig		: STD_LOGIC; -- DAC Signals
signal DAC_DINsig			: STD_LOGIC; -- DAC Signals
signal DAC_SCLKsig		: STD_LOGIC; -- DAC Signals
signal DAC_CSn_Bsig		: STD_LOGIC_VECTOR( 3 downto 0); -- DAC Signals
--output signals
signal SYNCnsig	 		: STD_LOGIC;

begin

--------------------------------------------------------------------
-- Component Declaration														--
--------------------------------------------------------------------
IBUF_POR : IBUF
   generic map (
						IOSTANDARD => "DEFAULT"  -- LVTTL
					)
   port map (
					O => RST,	-- Buffer output
					I => POR			-- Buffer input (connect directly to top-level port)
				);
				
BUFG_CLK_40MHZ : BUFG
   port map (
					O => CLK_40MHZsig,	-- Clock buffer output
					I => CLK_40MHZ			-- Clock buffer input
				);

IBUF_CLK_40MHZ_OK : IBUF
   generic map (
						IOSTANDARD => "DEFAULT"  -- LVTTL
					)
   port map (
					O => CLK_40MHZ_OKsig,	-- Buffer output
					I => CLK_40MHZ_OK			-- Buffer input (connect directly to top-level port)
				);
				
IBUF_CTRL : IBUF
   generic map (
						IOSTANDARD => "DEFAULT"  -- LVTTL
					)
   port map (
					O => CTRLsig,	-- Buffer output
					I => CTRL			-- Buffer input (connect directly to top-level port)
				);
				
IBUF_CTRL_OK : IBUF
   generic map (
						IOSTANDARD => "DEFAULT"  -- LVTTL
					)
   port map (
					O => CTRL_OKsig,	-- Buffer output
					I => CTRL_OK			-- Buffer input (connect directly to top-level port)
				);
				
IBUF_LOCKED : IBUF
   generic map (
						IOSTANDARD => "DEFAULT"  -- LVTTL
					)
   port map (
					O => LOCKEDsig,	-- Buffer output
					I => LOCKED			-- Buffer input (connect directly to top-level port)
				);				

OBUF_Data_for:
	for i in 0 to 15 generate
		OBUF_DATA : OBUFT
			generic map (
				DRIVE => 12,
				IOSTANDARD => "DEFAULT",
				SLEW => "SLOW")
			port map (
				O => Data(i),		-- Buffer output (connect directly to top-level port)
				I => Datasig(i),   -- Buffer input 
				T => DATA_TSsig
			);	
	end generate;

OBUF_SYNCn : OBUF
   generic map (
      DRIVE => 12,
      IOSTANDARD => "DEFAULT",
      SLEW => "SLOW")
   port map (
      O => SYNCn,			-- Buffer output (connect directly to top-level port)
      I => SYNCnsig		-- Buffer input 
   );	

IBUF_HFnB_for:
	for i in 0 to 3 generate
		IBUF_HFnB : IBUF
			generic map (
						IOSTANDARD => "DEFAULT"  -- LVTTL
					)
			port map (
					O => HFn_Bsig(i),	-- Buffer output
					I => HFn_B(i)		-- Buffer input (connect directly to top-level port)
				);				
	end generate;

IBUF_FFnB_for:
	for i in 0 to 3 generate
		IBUF_FFnB : IBUF
			generic map (
						IOSTANDARD => "DEFAULT"  -- LVTTL
					)
			port map (
					O => FFn_Bsig(i),	-- Buffer output
					I => FFn_B(i)		-- Buffer input (connect directly to top-level port)
				);				
	end generate;

OBUF_RST_TIMERn : OBUF
   generic map (
      DRIVE => 12,
      IOSTANDARD => "DEFAULT",
      SLEW => "SLOW")
   port map (
      O => RST_TIMERn,			-- Buffer output (connect directly to top-level port)
      I => RST_TIMERnsig		-- Buffer input 
   );	

OBUF_RST4n_B_for:
	for i in 0 to 3 generate
		OBUF_RST4n_B : OBUF
			generic map (
				DRIVE => 12,
				IOSTANDARD => "DEFAULT",
				SLEW => "SLOW")
			port map (
				O => RST4n_B(i),		-- Buffer output (connect directly to top-level port)
				I => RST4n_Bsig(i)   -- Buffer input 
			);	
	end generate;

OBUF_RCLK4_B_for:
	for i in 0 to 3 generate
		OBUF_RCLK4_B : OBUF
			generic map (
				DRIVE => 12,
				IOSTANDARD => "DEFAULT",
				SLEW => "SLOW")
			port map (
				O => RCLK4_B(i),		-- Buffer output (connect directly to top-level port)
				I => RCLK4_Bsig(i)   -- Buffer input 
			);	
	end generate;

OBUF_D_OEn_B_for:
	for i in 0 to 3 generate
		OBUF_D_OEn_B : OBUF
			generic map (
				DRIVE => 12,
				IOSTANDARD => "DEFAULT",
				SLEW => "SLOW")
			port map (
				O => D_OEn_B(i),		-- Buffer output (connect directly to top-level port)
				I => D_OEn_Bsig(i)   -- Buffer input 
			);	
	end generate;

OBUF_ACQENnB0_for:
	for i in 0 to 3 generate
		OBUF_ACQENnB0 : OBUF
			generic map (
				DRIVE => 12,
				IOSTANDARD => "DEFAULT",
				SLEW => "SLOW")
			port map (
				O => ACQENnB0(i),		-- Buffer output (connect directly to top-level port)
				I => ACQENnB0sig(i)   -- Buffer input 
			);	
	end generate;

OBUF_ACQENnB1_for:
	for i in 0 to 3 generate
		OBUF_ACQENnB1 : OBUF
			generic map (
				DRIVE => 12,
				IOSTANDARD => "DEFAULT",
				SLEW => "SLOW")
			port map (
				O => ACQENnB1(i),		-- Buffer output (connect directly to top-level port)
				I => ACQENnB1sig(i)   -- Buffer input 
			);	
	end generate;

OBUF_ACQENnB2_for:
	for i in 0 to 3 generate
		OBUF_ACQENnB2 : OBUF
			generic map (
				DRIVE => 12,
				IOSTANDARD => "DEFAULT",
				SLEW => "SLOW")
			port map (
				O => ACQENnB2(i),		-- Buffer output (connect directly to top-level port)
				I => ACQENnB2sig(i)   -- Buffer input 
			);	
	end generate;	

OBUF_ACQENnB3_for:
	for i in 0 to 3 generate
		OBUF_ACQENnB3 : OBUF
			generic map (
				DRIVE => 12,
				IOSTANDARD => "DEFAULT",
				SLEW => "SLOW")
			port map (
				O => ACQENnB3(i),		-- Buffer output (connect directly to top-level port)
				I => ACQENnB3sig(i)   -- Buffer input 
			);	
	end generate;	

OBUF_RESETn : OBUF
   generic map (
      DRIVE => 12,
      IOSTANDARD => "DEFAULT",
      SLEW => "SLOW")
   port map (
      O => RESETn,			-- Buffer output (connect directly to top-level port)
      I => RESETnsig		-- Buffer input 
   );	

OBUF_SYSCLK : OBUF
   generic map (
      DRIVE => 12,
      IOSTANDARD => "DEFAULT",
      SLEW => "SLOW")
   port map (
      O => SYSCLK,			-- Buffer output (connect directly to top-level port)
      I => SYSCLKsig		-- Buffer input 
   );	

OBUF_ENABLEn_B_for:
	for i in 0 to 3 generate
		OBUF_ENABLEn_B : OBUF
			generic map (
				DRIVE => 12,
				IOSTANDARD => "DEFAULT",
				SLEW => "SLOW")
			port map (
				O => ENABLEn_B(i),		-- Buffer output (connect directly to top-level port)
				I => ENABLEn_Bsig(i)   -- Buffer input 
			);	
	end generate;	

OBUF_TCLK : OBUF
   generic map (
      DRIVE => 12,
      IOSTANDARD => "DEFAULT",
      SLEW => "SLOW")
   port map (
      O => TCLK,			-- Buffer output (connect directly to top-level port)
      I => TCLKsig		-- Buffer input 
   );	
	
OBUF_ACLK : OBUF
   generic map (
      DRIVE => 12,
      IOSTANDARD => "DEFAULT",
      SLEW => "SLOW")
   port map (
      O => ACLK,			-- Buffer output (connect directly to top-level port)
      I => ACLKsig		-- Buffer input 
   );	
	
OBUF_RCLK3 : OBUF
   generic map (
      DRIVE => 12,
      IOSTANDARD => "DEFAULT",
      SLEW => "SLOW")
   port map (
      O => RCLK3,			-- Buffer output (connect directly to top-level port)
      I => RCLK3sig		-- Buffer input 
   );	
	
OBUF_ADCRST : OBUF
   generic map (
      DRIVE => 12,
      IOSTANDARD => "DEFAULT",
      SLEW => "SLOW")
   port map (
      O => ADCRST,			-- Buffer output (connect directly to top-level port)
      I => ADCRSTsig		-- Buffer input 
   );	
	
OBUF_TMODE : OBUF
   generic map (
      DRIVE => 12,
      IOSTANDARD => "DEFAULT",
      SLEW => "SLOW")
   port map (
      O => TMODE,			-- Buffer output (connect directly to top-level port)
      I => TMODEsig		-- Buffer input 
   );	
	
OBUF_DR0 : OBUF
   generic map (
      DRIVE => 12,
      IOSTANDARD => "DEFAULT",
      SLEW => "SLOW")
   port map (
      O => DR0,			-- Buffer output (connect directly to top-level port)
      I => DR0sig		-- Buffer input 
   );	
	
OBUF_DR1 : OBUF
   generic map (
      DRIVE => 12,
      IOSTANDARD => "DEFAULT",
      SLEW => "SLOW")
   port map (
      O => DR1,			-- Buffer output (connect directly to top-level port)
      I => DR1sig		-- Buffer input 
   );	

OBUF_PT0 : OBUF
   generic map (
      DRIVE => 12,
      IOSTANDARD => "DEFAULT",
      SLEW => "SLOW")
   port map (
      O => PT0,			-- Buffer output (connect directly to top-level port)
      I => PT0sig		-- Buffer input 
   );	
	
OBUF_PT1 : OBUF
   generic map (
      DRIVE => 12,
      IOSTANDARD => "DEFAULT",
      SLEW => "SLOW")
   port map (
      O => PT1,			-- Buffer output (connect directly to top-level port)
      I => PT1sig		-- Buffer input 
   );	

OBUF_uD_OEn_B_for:
	for i in 0 to 3 generate
		OBUF_uD_OEn_B : OBUF
			generic map (
				DRIVE => 12,
				IOSTANDARD => "DEFAULT",
				SLEW => "SLOW")
			port map (
				O => uD_OEn_B(i),			-- Buffer output (connect directly to top-level port)
				I => uD_OEn_Bsig(i)   	-- Buffer input 
			);	
	end generate;	

OBUF_uDw_for:
	for i in 0 to 7 generate
		OBUF_uDw : OBUF
			generic map (
				DRIVE => 12,
				IOSTANDARD => "DEFAULT",
				SLEW => "SLOW")
			port map (
				O => uDw(i),		-- Buffer output (connect directly to top-level port)
				I => uDwsig(i)   	-- Buffer input 
			);	
	end generate;	
	
IBUF_uDr_for:
	for i in 0 to 7 generate
		OBUF_uDr : IBUF
			generic map (
				IOSTANDARD => "DEFAULT"  --LVTTL
				)
			port map (
				O => uDrsig(i),		-- Buffer output (connect directly to top-level port)
				I => uDr(i)   			-- Buffer input 
			);	
	end generate;	
	

OBUF_DAC_LOADn : OBUF
   generic map (
      DRIVE => 12,
      IOSTANDARD => "DEFAULT",
      SLEW => "SLOW")
   port map (
      O => DAC_LOADn,			-- Buffer output (connect directly to top-level port)
      I => DAC_LOADnsig		-- Buffer input 
   );	

OBUF_DAC_DIN : OBUF
   generic map (
      DRIVE => 12,
      IOSTANDARD => "DEFAULT",
      SLEW => "SLOW")
   port map (
      O => DAC_DIN,			-- Buffer output (connect directly to top-level port)
      I => DAC_DINsig		-- Buffer input 
   );	

OBUF_DAC_SCLK : OBUF
   generic map (
      DRIVE => 12,
      IOSTANDARD => "DEFAULT",
      SLEW => "SLOW")
   port map (
      O => DAC_SCLK,			-- Buffer output (connect directly to top-level port)
      I => DAC_SCLKsig		-- Buffer input 
   );	

OBUF_DAC_CSn_B_for:
	for i in 0 to 3 generate
		OBUF_DAC_CSn_B : OBUF
			generic map (
				DRIVE => 12,
				IOSTANDARD => "DEFAULT",
				SLEW => "SLOW")
			port map (
				O => DAC_CSn_B(i),		-- Buffer output (connect directly to top-level port)
				I => DAC_CSn_Bsig(i)   -- Buffer input 
			);	
	end generate;	
	
	
chip_comp : chip 
    Port Map ( 	
						RST 			=> RST,
						CLK 			=> CLK_40MHZsig,
						CLK_OK		=> CLK_40MHZ_OKsig,
						CTRL			=> CTRLsig,
						CTRL_OK		=> CTRL_OKsig,
						LOCKED		=> LOCKEDsig,
						DATA			=> DATAsig,
						DATA_TS		=> DATA_TSsig,
						SYNCn			=> SYNCnsig,
						HFn_B			=> HFn_Bsig,
						FFn_B			=> FFn_Bsig,
						RST_TIMERn	=> RST_TIMERnsig,
						DAC_LOADn	=> DAC_LOADnsig,
						DAC_DIN		=> DAC_DINsig,
						DAC_SCLK		=> DAC_SCLKsig,
						DAC_CSn_B	=> DAC_CSn_Bsig,
						RST4n_B		=> RST4n_Bsig,
						RCLK4_B		=> RCLK4_Bsig,
						D_OEn_B		=> D_OEn_Bsig,
						ACQENnB0		=> ACQENnB0sig,
						ACQENnB1		=> ACQENnB1sig,
						ACQENnB2		=> ACQENnB2sig,
						ACQENnB3		=> ACQENnB3sig,
						RESETn		=> RESETnsig,
						SYSCLK		=> SYSCLKsig,
						ENABLEn_B	=> ENABLEn_Bsig,
						TCLK			=> TCLKsig,
						ACLK			=> ACLKsig,
						RCLK3			=> RCLK3sig,
						ADCRST		=> ADCRSTsig,
						TMODE			=> TMODEsig,
						DR0			=> DR0sig,
						DR1			=> DR1sig,
						PT0			=> PT0sig,
						PT1			=> PT1sig,
						uD_OEn_B		=> uD_OEn_Bsig,
						uDw			=> uDwsig,
						uDr			=> uDrsig
				 );


end Behavioral;