cpldfit: version I.31 Xilinx Inc. Fitter Report Design Name: top Date: 3- 8-2007, 5:05PM Device Used: XC95288XL-7-TQ144 Fitting Status: Successful ************************* Mapped Resource Summary ************************** Macrocells Product Terms Function Block Registers Pins Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot 234/288 ( 81%) 653 /1440 ( 45%) 405/864 ( 47%) 192/288 ( 67%) 89 /117 ( 76%) ** Function Block Resources ** Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot FB1 18/18* 30/54 61/90 8/ 8* FB2 11/18 23/54 14/90 8/10 FB3 17/18 31/54 38/90 2/ 5 FB4 15/18 31/54 29/90 0/ 6 FB5 12/18 31/54 63/90 7/ 8 FB6 18/18* 16/54 21/90 0/ 8 FB7 8/18 31/54 78/90 4/ 4* FB8 18/18* 27/54 38/90 5/ 5* FB9 14/18 31/54 88/90 9/ 9* FB10 18/18* 11/54 10/90 8/10 FB11 10/18 32/54 51/90 7/ 7* FB12 12/18 12/54 12/90 0/ 6 FB13 9/18 32/54 55/90 6/ 6* FB14 18/18* 28/54 36/90 3/ 8 FB15 18/18* 22/54 23/90 8/ 9 FB16 18/18* 17/54 36/90 5/ 8 ----- ----- ----- ----- 234/288 405/864 653/1440 80/117 * - Resource is exhausted ** Global Control Resources ** Signal 'CLK_40MHZ' mapped onto global clock net GCK1. Global output enable net(s) unused. Signal 'POR' mapped onto global set/reset net GSR. ** Pin Resources ** Signal Type Required Mapped | Pin Type Used Total ------------------------------------|------------------------------------ Input : 7 7 | I/O : 84 109 Output : 80 80 | GCK/IO : 1 3 Bidirectional : 0 0 | GTS/IO : 3 4 GCK : 1 1 | GSR/IO : 1 1 GTS : 0 0 | GSR : 1 1 | ---- ---- Total 89 89 ** Power Data ** There are 234 macrocells in high performance mode (MCHP). There are 0 macrocells in low power mode (MCLP). End of Mapped Resource Summary ************************** Errors and Warnings *************************** WARNING:Cpld:1258 - Invalid constraint 'PULLUP' found in netlist. The constraint is not supported for targeted device and is ignored. WARNING:Cpld:1258 - Invalid constraint 'PULLUP' found in netlist. The constraint is not supported for targeted device and is ignored. WARNING:Cpld:1258 - Invalid constraint 'PULLUP' found in netlist. The constraint is not supported for targeted device and is ignored. WARNING:Cpld:1258 - Invalid constraint 'PULLUP' found in netlist. The constraint is not supported for targeted device and is ignored. WARNING:Cpld:1258 - Invalid constraint 'PULLUP' found in netlist. The constraint is not supported for targeted device and is ignored. WARNING:Cpld:1258 - Invalid constraint 'PULLUP' found in netlist. The constraint is not supported for targeted device and is ignored. WARNING:Cpld:1258 - Invalid constraint 'PULLUP' found in netlist. The constraint is not supported for targeted device and is ignored. WARNING:Cpld:1258 - Invalid constraint 'PULLUP' found in netlist. The constraint is not supported for targeted device and is ignored. WARNING:Cpld:1007 - Removing unused input(s) 'CLK_40MHZ_OK'. The input(s) are unused after optimization. Please verify functionality via simulation. WARNING:Cpld:1007 - Removing unused input(s) 'FFn_B<0>'. The input(s) are unused after optimization. Please verify functionality via simulation. WARNING:Cpld:1007 - Removing unused input(s) 'FFn_B<1>'. The input(s) are unused after optimization. Please verify functionality via simulation. WARNING:Cpld:1007 - Removing unused input(s) 'FFn_B<2>'. The input(s) are unused after optimization. Please verify functionality via simulation. WARNING:Cpld:1007 - Removing unused input(s) 'FFn_B<3>'. The input(s) are unused after optimization. Please verify functionality via simulation. WARNING:Cpld:1007 - Removing unused input(s) 'uDr<0>'. The input(s) are unused after optimization. Please verify functionality via simulation. WARNING:Cpld:1007 - Removing unused input(s) 'uDr<1>'. The input(s) are unused after optimization. Please verify functionality via simulation. WARNING:Cpld:1007 - Removing unused input(s) 'uDr<2>'. The input(s) are unused after optimization. Please verify functionality via simulation. WARNING:Cpld:1007 - Removing unused input(s) 'uDr<3>'. The input(s) are unused after optimization. Please verify functionality via simulation. WARNING:Cpld:1007 - Removing unused input(s) 'uDr<4>'. The input(s) are unused after optimization. Please verify functionality via simulation. WARNING:Cpld:1007 - Removing unused input(s) 'uDr<5>'. The input(s) are unused after optimization. Please verify functionality via simulation. WARNING:Cpld:1007 - Removing unused input(s) 'uDr<6>'. The input(s) are unused after optimization. Please verify functionality via simulation. WARNING:Cpld:1007 - Removing unused input(s) 'uDr<7>'. The input(s) are unused after optimization. Please verify functionality via simulation. ************************* Summary of Mapped Logic ************************ ** 80 Outputs ** Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init Name Pts Inps No. Type Use Mode Rate State ACQENnB0<1> 1 2 FB1_5 20 I/O O STD SLOW SET ACQENnB1<1> 1 2 FB1_6 21 I/O O STD SLOW SET ACQENnB2<1> 1 2 FB1_8 22 I/O O STD SLOW SET ACQENnB3<1> 1 2 FB1_10 23 I/O O STD SLOW SET ACQENnB0<0> 1 2 FB1_12 24 I/O O STD SLOW SET SYSCLK 1 1 FB1_14 25 I/O O STD SLOW TCLK 1 11 FB1_15 26 I/O O STD SLOW RESET ACLK 1 9 FB1_17 27 I/O O STD SLOW RESET ACQENnB0<3> 1 2 FB2_5 11 I/O O STD SLOW SET ACQENnB1<3> 1 2 FB2_6 12 I/O O STD SLOW SET ACQENnB2<3> 1 2 FB2_8 13 I/O O STD SLOW SET ACQENnB3<3> 1 2 FB2_10 14 I/O O STD SLOW SET ACQENnB0<2> 1 2 FB2_12 15 I/O O STD SLOW SET ACQENnB1<2> 1 2 FB2_14 16 I/O O STD SLOW SET ACQENnB2<2> 1 2 FB2_15 17 I/O O STD SLOW SET ACQENnB3<2> 1 2 FB2_17 19 I/O O STD SLOW SET RCLK3 1 1 FB3_2 28 I/O O STD SLOW ACQENnB1<0> 1 2 FB3_15 33 I/O O STD SLOW SET ACQENnB2<0> 1 2 FB5_2 34 I/O O STD SLOW SET ACQENnB3<0> 1 2 FB5_5 35 I/O O STD SLOW SET DATA<15> 6 7 FB5_10 39 I/O O STD SLOW DATA<14> 6 7 FB5_12 40 I/O O STD SLOW DATA<13> 6 7 FB5_14 41 I/O O STD SLOW DATA<12> 6 7 FB5_15 43 I/O O STD SLOW DATA<11> 6 7 FB5_17 44 I/O O STD SLOW DATA<10> 6 7 FB7_3 45 I/O O STD SLOW DATA<9> 6 7 FB7_5 46 I/O O STD SLOW DATA<8> 6 7 FB7_12 48 I/O O STD SLOW DATA<7> 6 7 FB7_15 49 I/O O STD SLOW uDw<3> 0 0 FB8_2 130 I/O O STD SLOW uDw<2> 0 0 FB8_3 131 I/O O STD SLOW uDw<1> 0 0 FB8_5 132 I/O O STD SLOW uDw<0> 0 0 FB8_8 133 I/O O STD SLOW SYNCn 1 1 FB8_10 134 I/O O STD SLOW RESET DATA<6> 6 7 FB9_2 50 I/O O STD SLOW DATA<5> 6 7 FB9_3 51 I/O O STD SLOW DATA<4> 6 7 FB9_5 52 I/O O STD SLOW DATA<3> 6 7 FB9_6 53 I/O O STD SLOW DATA<2> 6 7 FB9_8 54 I/O O STD SLOW DATA<1> 6 7 FB9_11 56 I/O O STD SLOW Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init Name Pts Inps No. Type Use Mode Rate State DATA<0> 6 7 FB9_12 57 I/O O STD SLOW RST4n_B<0> 1 5 FB9_14 58 I/O O STD SLOW RESET D_OEn_B<0> 1 4 FB9_17 59 I/O O STD SLOW SET uD_OEn_B<0> 0 0 FB10_5 119 I/O O STD SLOW uD_OEn_B<1> 0 0 FB10_6 120 I/O O STD SLOW uD_OEn_B<2> 0 0 FB10_8 121 I/O O STD SLOW uD_OEn_B<3> 0 0 FB10_10 124 I/O O STD SLOW uDw<7> 0 0 FB10_11 125 I/O O STD SLOW uDw<6> 0 0 FB10_12 126 I/O O STD SLOW uDw<5> 0 0 FB10_14 128 I/O O STD SLOW uDw<4> 0 0 FB10_17 129 I/O O STD SLOW RCLK4_B<0> 1 3 FB11_3 60 I/O O STD SLOW RST4n_B<1> 1 5 FB11_5 61 I/O O STD SLOW RESET D_OEn_B<1> 1 4 FB11_10 64 I/O O STD SLOW SET RCLK4_B<1> 1 3 FB11_11 66 I/O O STD SLOW RST4n_B<2> 1 5 FB11_12 68 I/O O STD SLOW RESET D_OEn_B<2> 1 4 FB11_14 69 I/O O STD SLOW SET RCLK4_B<2> 1 3 FB11_17 70 I/O O STD SLOW RST4n_B<3> 1 5 FB13_2 71 I/O O STD SLOW RESET D_OEn_B<3> 1 4 FB13_8 74 I/O O STD SLOW SET RCLK4_B<3> 1 3 FB13_11 75 I/O O STD SLOW DAC_LOADn 1 0 FB13_14 76 I/O O STD SLOW DAC_DIN 0 0 FB13_15 77 I/O O STD SLOW DAC_SCLK 1 0 FB13_17 78 I/O O STD SLOW ADCRST 2 4 FB14_3 100 I/O O STD SLOW RESET RESETn 1 1 FB14_11 105 I/O O STD SLOW RST_TIMERn 2 4 FB14_14 106 I/O O STD SLOW SET DAC_CSn_B<0> 0 0 FB15_2 79 I/O O STD SLOW DAC_CSn_B<1> 0 0 FB15_3 80 I/O O STD SLOW DAC_CSn_B<2> 0 0 FB15_8 81 I/O O STD SLOW DAC_CSn_B<3> 0 0 FB15_10 82 I/O O STD SLOW ENABLEn_B<3> 1 2 FB15_12 85 I/O O STD SLOW SET ENABLEn_B<2> 1 2 FB15_14 86 I/O O STD SLOW SET ENABLEn_B<1> 1 2 FB15_15 87 I/O O STD SLOW SET ENABLEn_B<0> 1 2 FB15_17 88 I/O O STD SLOW SET PT0 2 10 FB16_6 94 I/O O STD SLOW RESET PT1 2 10 FB16_8 95 I/O O STD SLOW RESET DR0 2 10 FB16_10 96 I/O O STD SLOW RESET DR1 2 10 FB16_11 97 I/O O STD SLOW RESET TMODE 2 10 FB16_12 98 I/O O STD SLOW RESET ** 154 Buried Nodes ** Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State chip_comp/TCLKCounter<0> 2 14 FB1_1 STD RESET chip_comp/TCLKCounter<1> 3 14 FB1_2 STD RESET chip_comp/TCLKCounter<9> 4 14 FB1_3 STD RESET chip_comp/TCLKCounter<8> 5 14 FB1_4 STD RESET chip_comp/TCLKCounter<2> 5 14 FB1_7 STD RESET chip_comp/TCLKCounter<3> 6 14 FB1_9 STD RESET chip_comp/TCLKCounter<7> 7 14 FB1_11 STD RESET chip_comp/TCLKCounter<6> 7 14 FB1_13 STD RESET chip_comp/TCLKCounter<5> 7 14 FB1_16 STD RESET chip_comp/TCLKCounter<4> 7 14 FB1_18 STD RESET chip_comp/ACQENnB2Reg<3> 2 15 FB2_13 STD RESET chip_comp/ACQENnB1Reg<3> 2 15 FB2_16 STD RESET chip_comp/ACQENnB0Reg<3> 2 15 FB2_18 STD RESET chip_comp/TXMAINSTATE_FFd1 1 5 FB3_3 STD RESET chip_comp/TCLKsig_1 1 1 FB3_4 STD RESET chip_comp/SimulData<9> 1 1 FB3_5 STD RESET chip_comp/ADCRestCMD 1 3 FB3_6 STD SET chip_comp/ACLKCounter<2> 1 2 FB3_7 STD RESET chip_comp/ACLKCounter<1> 1 1 FB3_8 STD RESET chip_comp/TimerInterval<1> 2 10 FB3_9 STD RESET chip_comp/StatusDataSel<1> 2 10 FB3_10 STD RESET chip_comp/SamplingClock<1> 2 10 FB3_11 STD RESET chip_comp/ACLKCounter<8> 2 11 FB3_12 STD RESET chip_comp/ACLKCounter<7> 3 11 FB3_13 STD RESET chip_comp/ACLKCounter<6> 4 11 FB3_14 STD RESET chip_comp/ACLKCounter<3> 4 11 FB3_16 STD RESET chip_comp/ACLKCounter<4> 5 10 FB3_17 STD RESET chip_comp/ACLKCounter<5> 6 11 FB3_18 STD RESET chip_comp/CommandAvailable 1 4 FB4_4 STD RESET chip_comp/TCLKCounter<10> 2 14 FB4_5 STD RESET chip_comp/CommandReceived<6> 2 5 FB4_6 STD RESET chip_comp/CommandReceived<5> 2 5 FB4_7 STD RESET chip_comp/CommandReceived<4> 2 5 FB4_8 STD RESET chip_comp/CommandReceived<3> 2 5 FB4_9 STD RESET chip_comp/CommandReceived<2> 2 5 FB4_10 STD RESET chip_comp/CommandReceived<1> 2 5 FB4_11 STD RESET chip_comp/CommandReceived<15> 2 5 FB4_12 STD RESET chip_comp/CommandReceived<14> 2 5 FB4_13 STD RESET chip_comp/CommandReceived<13> 2 5 FB4_14 STD RESET chip_comp/CommandReceived<12> 2 5 FB4_15 STD RESET Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State chip_comp/CommandReceived<11> 2 5 FB4_16 STD RESET chip_comp/CommandReceived<10> 2 5 FB4_17 STD RESET chip_comp/CommandReceived<0> 2 5 FB4_18 STD RESET chip_comp/Datasig<9> 15 17 FB5_1 STD RESET DATA_TSsig 4 4 FB5_9 STD SET chip_comp/Datasig<14> 6 12 FB5_11 STD RESET chip_comp/ACLKCounter<0> 0 0 FB5_13 STD RESET chip_comp/Datasig<12> 6 12 FB5_16 STD RESET chip_comp/ReceiveCommandComp/sr<3> 1 2 FB6_1 STD RESET chip_comp/ReceiveCommandComp/sr<2> 1 2 FB6_2 STD RESET chip_comp/ReceiveCommandComp/sr<1> 1 2 FB6_3 STD RESET chip_comp/ReceiveCommandComp/sr<19> 1 2 FB6_4 STD RESET chip_comp/ReceiveCommandComp/sr<18> 1 2 FB6_5 STD RESET chip_comp/ReceiveCommandComp/sr<17> 1 2 FB6_6 STD RESET chip_comp/ReceiveCommandComp/sr<16> 1 2 FB6_7 STD RESET chip_comp/ReceiveCommandComp/sr<15> 1 2 FB6_8 STD RESET chip_comp/ReceiveCommandComp/sr<14> 1 2 FB6_9 STD RESET chip_comp/ReceiveCommandComp/sr<13> 1 2 FB6_10 STD RESET chip_comp/ReceiveCommandComp/sr<12> 1 2 FB6_11 STD RESET chip_comp/ReceiveCommandComp/sr<11> 1 2 FB6_12 STD RESET chip_comp/ReceiveCommandComp/sr<10> 1 2 FB6_13 STD RESET chip_comp/ReceiveCommandComp/sr<0> 1 2 FB6_14 STD RESET chip_comp/ReceiveCommandComp/clr_sr 1 4 FB6_15 STD RESET chip_comp/CommandReceived<9> 2 5 FB6_16 STD RESET chip_comp/CommandReceived<8> 2 5 FB6_17 STD RESET chip_comp/CommandReceived<7> 2 5 FB6_18 STD RESET chip_comp/Datasig<10> 6 12 FB7_2 STD RESET chip_comp/Datasig<5> 16 18 FB7_7 STD RESET chip_comp/Datasig<7> 16 18 FB7_11 STD RESET chip_comp/Datasig<8> 16 18 FB7_17 STD RESET chip_comp/SimulData<7> 1 1 FB8_1 STD RESET chip_comp/SimulData<14> 1 1 FB8_4 STD RESET chip_comp/TXMAINSTATE_FFd2 2 3 FB8_6 STD RESET chip_comp/LinkStablished 2 3 FB8_7 STD RESET chip_comp/GenDataCounter<6> 2 8 FB8_9 STD RESET chip_comp/GenDataCounter<5> 2 7 FB8_11 STD RESET chip_comp/GenDataCounter<4> 2 6 FB8_12 STD RESET chip_comp/GenDataCounter<3> 2 5 FB8_13 STD RESET chip_comp/GenDataCounter<2> 2 4 FB8_14 STD RESET chip_comp/GenDataCounter<1> 2 3 FB8_15 STD RESET Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State chip_comp/TXREADOUTSTATE_FFd1 3 6 FB8_16 STD RESET chip_comp/TXREADOUTSTATE_FFd3 6 9 FB8_17 STD RESET chip_comp/Datasig<13> 10 12 FB8_18 STD RESET chip_comp/TXREADOUTSTATE_FFd4 12 12 FB9_1 STD RESET chip_comp/GenDatasig 5 8 FB9_7 STD RESET chip_comp/Datasig<15> 10 11 FB9_10 STD RESET chip_comp/TXREADOUTSTATE_FFd2 7 12 FB9_13 STD RESET chip_comp/Datasig<11> 10 12 FB9_16 STD RESET chip_comp/SimulData<0> 1 1 FB10_1 STD RESET chip_comp/ReceiveCommandComp/sr<9> 1 2 FB10_2 STD RESET chip_comp/ReceiveCommandComp/sr<8> 1 2 FB10_3 STD RESET chip_comp/ReceiveCommandComp/sr<7> 1 2 FB10_4 STD RESET chip_comp/ReceiveCommandComp/sr<6> 1 2 FB10_7 STD RESET chip_comp/ReceiveCommandComp/sr<5> 1 2 FB10_9 STD RESET chip_comp/ReceiveCommandComp/sr<4> 1 2 FB10_13 STD RESET chip_comp/ReceiveCommandComp/sr<20> 1 2 FB10_15 STD RESET chip_comp/GenDataCounter<0> 1 2 FB10_16 STD RESET chip_comp/ACLKsig_1 1 1 FB10_18 STD RESET chip_comp/Datasig<0> 18 21 FB11_1 STD RESET chip_comp/Datasig<4> 8 17 FB11_4 STD RESET chip_comp/Datasig<2> 18 21 FB11_15 STD RESET chip_comp/SimulData<8> 1 1 FB12_7 STD RESET chip_comp/SimulData<6> 1 1 FB12_8 STD RESET chip_comp/SimulData<5> 1 1 FB12_9 STD RESET chip_comp/SimulData<4> 1 1 FB12_10 STD RESET chip_comp/SimulData<3> 1 1 FB12_11 STD RESET chip_comp/SimulData<2> 1 1 FB12_12 STD RESET chip_comp/SimulData<1> 1 1 FB12_13 STD RESET chip_comp/SimulData<15> 1 1 FB12_14 STD RESET chip_comp/SimulData<13> 1 1 FB12_15 STD RESET chip_comp/SimulData<12> 1 1 FB12_16 STD RESET chip_comp/SimulData<11> 1 1 FB12_17 STD RESET chip_comp/SimulData<10> 1 1 FB12_18 STD RESET chip_comp/Datasig<6> 16 18 FB13_4 STD RESET chip_comp/Datasig<3> 17 21 FB13_13 STD RESET chip_comp/Datasig<1> 17 21 FB13_18 STD RESET chip_comp/TimerRestCMD 2 11 FB14_1 STD SET chip_comp/TimerInterval<2> 2 10 FB14_2 STD RESET chip_comp/TimerInterval<0> 2 10 FB14_4 STD RESET chip_comp/StatusDataSel<4> 2 10 FB14_5 STD RESET Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State chip_comp/StatusDataSel<3> 2 10 FB14_6 STD RESET chip_comp/StatusDataSel<2> 2 10 FB14_7 STD RESET chip_comp/StatusDataSel<0> 2 10 FB14_8 STD RESET chip_comp/SamplingClock<0> 2 10 FB14_9 STD RESET chip_comp/GenDataCMD 2 11 FB14_10 STD RESET chip_comp/ENABLEn_BReg<3> 2 15 FB14_12 STD RESET chip_comp/ENABLEn_BReg<2> 2 15 FB14_13 STD RESET chip_comp/DataPackageTXEn 2 10 FB14_15 STD RESET chip_comp/ACQENnB3Reg<3> 2 15 FB14_16 STD RESET chip_comp/ACQENnB3Reg<2> 2 15 FB14_17 STD RESET chip_comp/RunningFlag 3 10 FB14_18 STD RESET chip_comp/GenDataDonesig 1 16 FB15_1 STD RESET chip_comp/GenDataCounter<9> 2 11 FB15_4 STD RESET chip_comp/GenDataCounter<8> 2 10 FB15_5 STD RESET chip_comp/GenDataCounter<7> 2 9 FB15_6 STD RESET chip_comp/GenDataCounter<15> 2 17 FB15_7 STD RESET chip_comp/GenDataCounter<14> 2 16 FB15_9 STD RESET chip_comp/GenDataCounter<13> 2 15 FB15_11 STD RESET chip_comp/GenDataCounter<12> 2 14 FB15_13 STD RESET chip_comp/GenDataCounter<11> 2 13 FB15_16 STD RESET chip_comp/GenDataCounter<10> 2 12 FB15_18 STD RESET chip_comp/ENABLEn_BReg<1> 2 15 FB16_1 STD RESET chip_comp/ENABLEn_BReg<0> 2 15 FB16_2 STD RESET chip_comp/ACQENnB3Reg<1> 2 15 FB16_3 STD RESET chip_comp/ACQENnB3Reg<0> 2 15 FB16_4 STD RESET chip_comp/ACQENnB2Reg<2> 2 15 FB16_5 STD RESET chip_comp/ACQENnB2Reg<1> 2 15 FB16_7 STD RESET chip_comp/ACQENnB2Reg<0> 2 15 FB16_9 STD RESET chip_comp/ACQENnB1Reg<2> 2 15 FB16_13 STD RESET chip_comp/ACQENnB1Reg<1> 2 15 FB16_14 STD RESET chip_comp/ACQENnB1Reg<0> 2 15 FB16_15 STD RESET chip_comp/ACQENnB0Reg<2> 2 15 FB16_16 STD RESET chip_comp/ACQENnB0Reg<1> 2 15 FB16_17 STD RESET chip_comp/ACQENnB0Reg<0> 2 15 FB16_18 STD RESET ** 9 Inputs ** Signal Loc Pin Pin Pin Name No. Type Use CLK_40MHZ FB3_10 30 GCK/I/O GCK/I CTRL FB3_12 31 I/O I HFn_B<0> FB4_2 2 GTS/I/O I HFn_B<1> FB4_5 3 GTS/I/O I HFn_B<2> FB4_6 4 I/O I HFn_B<3> FB4_8 5 GTS/I/O I POR FB6_15 143 GSR/I/O GSR/I CTRL_OK FB16_2 91 I/O I LOCKED FB16_5 93 I/O I Legend: Pin No. - ~ - User Assigned ************************** Function Block Details ************************ Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X - Signal used as input to the macrocell logic. Pin No. - ~ - User Assigned *********************************** FB1 *********************************** Number of function block inputs used/remaining: 30/24 Number of signals used by logic mapping into function block: 30 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use chip_comp/TCLKCounter<0> 2 0 /\2 1 FB1_1 (b) (b) chip_comp/TCLKCounter<1> 3 0 0 2 FB1_2 (b) (b) chip_comp/TCLKCounter<9> 4 0 0 1 FB1_3 (b) (b) chip_comp/TCLKCounter<8> 5 0 0 0 FB1_4 (b) (b) ACQENnB0<1> 1 0 0 4 FB1_5 20 I/O O ACQENnB1<1> 1 0 0 4 FB1_6 21 I/O O chip_comp/TCLKCounter<2> 5 0 0 0 FB1_7 (b) (b) ACQENnB2<1> 1 0 \/1 3 FB1_8 22 I/O O chip_comp/TCLKCounter<3> 6 1<- 0 0 FB1_9 (b) (b) ACQENnB3<1> 1 0 \/1 3 FB1_10 23 I/O O chip_comp/TCLKCounter<7> 7 2<- 0 0 FB1_11 (b) (b) ACQENnB0<0> 1 0 /\1 3 FB1_12 24 I/O O chip_comp/TCLKCounter<6> 7 2<- 0 0 FB1_13 (b) (b) SYSCLK 1 0 /\2 2 FB1_14 25 I/O O TCLK 1 0 \/1 3 FB1_15 26 I/O O chip_comp/TCLKCounter<5> 7 2<- 0 0 FB1_16 (b) (b) ACLK 1 0 /\1 3 FB1_17 27 I/O O chip_comp/TCLKCounter<4> 7 2<- 0 0 FB1_18 (b) (b) Signals Used by Logic in Function Block 1: CLK_40MHZ 11: chip_comp/ACQENnB0Reg<0> 21: chip_comp/TCLKCounter<3> 2: chip_comp/ACLKCounter<0> 12: chip_comp/ACQENnB0Reg<1> 22: chip_comp/TCLKCounter<4> 3: chip_comp/ACLKCounter<1> 13: chip_comp/ACQENnB1Reg<1> 23: chip_comp/TCLKCounter<5> 4: chip_comp/ACLKCounter<2> 14: chip_comp/ACQENnB2Reg<1> 24: chip_comp/TCLKCounter<6> 5: chip_comp/ACLKCounter<3> 15: chip_comp/ACQENnB3Reg<1> 25: chip_comp/TCLKCounter<7> 6: chip_comp/ACLKCounter<4> 16: chip_comp/RunningFlag 26: chip_comp/TCLKCounter<8> 7: chip_comp/ACLKCounter<5> 17: chip_comp/TCLKCounter<0> 27: chip_comp/TCLKCounter<9> 8: chip_comp/ACLKCounter<6> 18: chip_comp/TCLKCounter<10> 28: chip_comp/TimerInterval<0> 9: chip_comp/ACLKCounter<7> 19: chip_comp/TCLKCounter<1> 29: chip_comp/TimerInterval<1> 10: chip_comp/ACLKCounter<8> 20: chip_comp/TCLKCounter<2> 30: chip_comp/TimerInterval<2> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs chip_comp/TCLKCounter<0> ................XXXXXXXXXXXXXX.......... 14 chip_comp/TCLKCounter<1> ................XXXXXXXXXXXXXX.......... 14 chip_comp/TCLKCounter<9> ................XXXXXXXXXXXXXX.......... 14 chip_comp/TCLKCounter<8> ................XXXXXXXXXXXXXX.......... 14 ACQENnB0<1> ...........X...X........................ 2 ACQENnB1<1> ............X..X........................ 2 chip_comp/TCLKCounter<2> ................XXXXXXXXXXXXXX.......... 14 ACQENnB2<1> .............X.X........................ 2 chip_comp/TCLKCounter<3> ................XXXXXXXXXXXXXX.......... 14 ACQENnB3<1> ..............XX........................ 2 chip_comp/TCLKCounter<7> ................XXXXXXXXXXXXXX.......... 14 ACQENnB0<0> ..........X....X........................ 2 chip_comp/TCLKCounter<6> ................XXXXXXXXXXXXXX.......... 14 SYSCLK X....................................... 1 TCLK ................XXXXXXXXXXX............. 11 chip_comp/TCLKCounter<5> ................XXXXXXXXXXXXXX.......... 14 ACLK .XXXXXXXXX.............................. 9 chip_comp/TCLKCounter<4> ................XXXXXXXXXXXXXX.......... 14 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB2 *********************************** Number of function block inputs used/remaining: 23/31 Number of signals used by logic mapping into function block: 23 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB2_1 (b) (unused) 0 0 0 5 FB2_2 9 I/O (unused) 0 0 0 5 FB2_3 10 I/O (unused) 0 0 0 5 FB2_4 (b) ACQENnB0<3> 1 0 0 4 FB2_5 11 I/O O ACQENnB1<3> 1 0 0 4 FB2_6 12 I/O O (unused) 0 0 0 5 FB2_7 (b) ACQENnB2<3> 1 0 0 4 FB2_8 13 I/O O (unused) 0 0 0 5 FB2_9 (b) ACQENnB3<3> 1 0 0 4 FB2_10 14 I/O O (unused) 0 0 0 5 FB2_11 (b) ACQENnB0<2> 1 0 0 4 FB2_12 15 I/O O chip_comp/ACQENnB2Reg<3> 2 0 0 3 FB2_13 (b) (b) ACQENnB1<2> 1 0 0 4 FB2_14 16 I/O O ACQENnB2<2> 1 0 0 4 FB2_15 17 I/O O chip_comp/ACQENnB1Reg<3> 2 0 0 3 FB2_16 (b) (b) ACQENnB3<2> 1 0 0 4 FB2_17 19 I/O O chip_comp/ACQENnB0Reg<3> 2 0 0 3 FB2_18 (b) (b) Signals Used by Logic in Function Block 1: chip_comp/ACQENnB0Reg<2> 9: chip_comp/CommandReceived<10> 17: chip_comp/CommandReceived<5> 2: chip_comp/ACQENnB0Reg<3> 10: chip_comp/CommandReceived<11> 18: chip_comp/CommandReceived<6> 3: chip_comp/ACQENnB1Reg<2> 11: chip_comp/CommandReceived<12> 19: chip_comp/CommandReceived<7> 4: chip_comp/ACQENnB1Reg<3> 12: chip_comp/CommandReceived<13> 20: chip_comp/CommandReceived<8> 5: chip_comp/ACQENnB2Reg<2> 13: chip_comp/CommandReceived<14> 21: chip_comp/CommandReceived<9> 6: chip_comp/ACQENnB2Reg<3> 14: chip_comp/CommandReceived<15> 22: chip_comp/RunningFlag 7: chip_comp/ACQENnB3Reg<2> 15: chip_comp/CommandReceived<3> 23: chip_comp/TXMAINSTATE_FFd1 8: chip_comp/ACQENnB3Reg<3> 16: chip_comp/CommandReceived<4> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs ACQENnB0<3> .X...................X.................. 2 ACQENnB1<3> ...X.................X.................. 2 ACQENnB2<3> .....X...............X.................. 2 ACQENnB3<3> .......X.............X.................. 2 ACQENnB0<2> X....................X.................. 2 chip_comp/ACQENnB2Reg<3> ........XXXXXXXXXXXXXXX................. 15 ACQENnB1<2> ..X..................X.................. 2 ACQENnB2<2> ....X................X.................. 2 chip_comp/ACQENnB1Reg<3> ........XXXXXXXXXXXXXXX................. 15 ACQENnB3<2> ......X..............X.................. 2 chip_comp/ACQENnB0Reg<3> ........XXXXXXXXXXXXXXX................. 15 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB3 *********************************** Number of function block inputs used/remaining: 31/23 Number of signals used by logic mapping into function block: 31 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 /\1 4 FB3_1 (b) (b) RCLK3 1 0 0 4 FB3_2 28 I/O O chip_comp/TXMAINSTATE_FFd1 1 0 0 4 FB3_3 (b) (b) chip_comp/TCLKsig_1 1 0 0 4 FB3_4 (b) (b) chip_comp/SimulData<9> 1 0 0 4 FB3_5 (b) (b) chip_comp/ADCRestCMD 1 0 0 4 FB3_6 (b) (b) chip_comp/ACLKCounter<2> 1 0 0 4 FB3_7 (b) (b) chip_comp/ACLKCounter<1> 1 0 0 4 FB3_8 (b) (b) chip_comp/TimerInterval<1> 2 0 0 3 FB3_9 (b) (b) chip_comp/StatusDataSel<1> 2 0 0 3 FB3_10 30 GCK/I/O GCK/I chip_comp/SamplingClock<1> 2 0 0 3 FB3_11 (b) (b) chip_comp/ACLKCounter<8> 2 0 0 3 FB3_12 31 I/O I chip_comp/ACLKCounter<7> 3 0 0 2 FB3_13 (b) (b) chip_comp/ACLKCounter<6> 4 0 0 1 FB3_14 32 GCK/I/O (b) ACQENnB1<0> 1 0 0 4 FB3_15 33 I/O O chip_comp/ACLKCounter<3> 4 0 0 1 FB3_16 (b) (b) chip_comp/ACLKCounter<4> 5 0 0 0 FB3_17 (b) (b) chip_comp/ACLKCounter<5> 6 1<- 0 0 FB3_18 (b) (b) Signals Used by Logic in Function Block 1: CLK_40MHZ 12: chip_comp/ACLKCounter<7> 22: chip_comp/CommandReceived<15> 2: CTRL_OK 13: chip_comp/ACLKCounter<8> 23: chip_comp/CommandReceived<1> 3: LOCKED 14: chip_comp/ACQENnB1Reg<0> 24: chip_comp/CommandReceived<8> 4: TCLK 15: chip_comp/ADCRestCMD 25: chip_comp/CommandReceived<9> 5: chip_comp/ACLKCounter<0> 16: chip_comp/CommandAvailable 26: chip_comp/GenDataCounter<9> 6: chip_comp/ACLKCounter<1> 17: chip_comp/CommandReceived<10> 27: chip_comp/RunningFlag 7: chip_comp/ACLKCounter<2> 18: chip_comp/CommandReceived<11> 28: chip_comp/SamplingClock<0> 8: chip_comp/ACLKCounter<3> 19: chip_comp/CommandReceived<12> 29: chip_comp/SamplingClock<1> 9: chip_comp/ACLKCounter<4> 20: chip_comp/CommandReceived<13> 30: chip_comp/TXMAINSTATE_FFd1 10: chip_comp/ACLKCounter<5> 21: chip_comp/CommandReceived<14> 31: chip_comp/TXMAINSTATE_FFd2 11: chip_comp/ACLKCounter<6> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs RCLK3 X....................................... 1 chip_comp/TXMAINSTATE_FFd1 .XX............X.............XX......... 5 chip_comp/TCLKsig_1 ...X.................................... 1 chip_comp/SimulData<9> .........................X.............. 1 chip_comp/ADCRestCMD ..............X..............XX......... 3 chip_comp/ACLKCounter<2> ....XX.................................. 2 chip_comp/ACLKCounter<1> ....X................................... 1 chip_comp/TimerInterval<1> ................XXXXXXXXX....X.......... 10 chip_comp/StatusDataSel<1> ................XXXXXXXXX....X.......... 10 chip_comp/SamplingClock<1> ................XXXXXXXXX....X.......... 10 chip_comp/ACLKCounter<8> ....XXXXXXXXX..............XX........... 11 chip_comp/ACLKCounter<7> ....XXXXXXXXX..............XX........... 11 chip_comp/ACLKCounter<6> ....XXXXXXXXX..............XX........... 11 ACQENnB1<0> .............X............X............. 2 chip_comp/ACLKCounter<3> ....XXXXXXXXX..............XX........... 11 chip_comp/ACLKCounter<4> ....XXXXXXXXX...............X........... 10 chip_comp/ACLKCounter<5> ....XXXXXXXXX..............XX........... 11 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB4 *********************************** Number of function block inputs used/remaining: 31/23 Number of signals used by logic mapping into function block: 31 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB4_1 (b) (unused) 0 0 0 5 FB4_2 2 GTS/I/O I (unused) 0 0 0 5 FB4_3 (b) chip_comp/CommandAvailable 1 0 0 4 FB4_4 (b) (b) chip_comp/TCLKCounter<10> 2 0 0 3 FB4_5 3 GTS/I/O I chip_comp/CommandReceived<6> 2 0 0 3 FB4_6 4 I/O I chip_comp/CommandReceived<5> 2 0 0 3 FB4_7 (b) (b) chip_comp/CommandReceived<4> 2 0 0 3 FB4_8 5 GTS/I/O I chip_comp/CommandReceived<3> 2 0 0 3 FB4_9 (b) (b) chip_comp/CommandReceived<2> 2 0 0 3 FB4_10 (b) (b) chip_comp/CommandReceived<1> 2 0 0 3 FB4_11 (b) (b) chip_comp/CommandReceived<15> 2 0 0 3 FB4_12 6 GTS/I/O (b) chip_comp/CommandReceived<14> 2 0 0 3 FB4_13 (b) (b) chip_comp/CommandReceived<13> 2 0 0 3 FB4_14 7 I/O (b) chip_comp/CommandReceived<12> 2 0 0 3 FB4_15 (b) (b) chip_comp/CommandReceived<11> 2 0 0 3 FB4_16 (b) (b) chip_comp/CommandReceived<10> 2 0 0 3 FB4_17 (b) (b) chip_comp/CommandReceived<0> 2 0 0 3 FB4_18 (b) (b) Signals Used by Logic in Function Block 1: chip_comp/ReceiveCommandComp/sr<10> 12: chip_comp/ReceiveCommandComp/sr<4> 22: chip_comp/TCLKCounter<3> 2: chip_comp/ReceiveCommandComp/sr<11> 13: chip_comp/ReceiveCommandComp/sr<5> 23: chip_comp/TCLKCounter<4> 3: chip_comp/ReceiveCommandComp/sr<15> 14: chip_comp/ReceiveCommandComp/sr<6> 24: chip_comp/TCLKCounter<5> 4: chip_comp/ReceiveCommandComp/sr<16> 15: chip_comp/ReceiveCommandComp/sr<7> 25: chip_comp/TCLKCounter<6> 5: chip_comp/ReceiveCommandComp/sr<17> 16: chip_comp/ReceiveCommandComp/sr<8> 26: chip_comp/TCLKCounter<7> 6: chip_comp/ReceiveCommandComp/sr<18> 17: chip_comp/ReceiveCommandComp/sr<9> 27: chip_comp/TCLKCounter<8> 7: chip_comp/ReceiveCommandComp/sr<19> 18: chip_comp/TCLKCounter<0> 28: chip_comp/TCLKCounter<9> 8: chip_comp/ReceiveCommandComp/sr<1> 19: chip_comp/TCLKCounter<10> 29: chip_comp/TimerInterval<0> 9: chip_comp/ReceiveCommandComp/sr<20> 20: chip_comp/TCLKCounter<1> 30: chip_comp/TimerInterval<1> 10: chip_comp/ReceiveCommandComp/sr<2> 21: chip_comp/TCLKCounter<2> 31: chip_comp/TimerInterval<2> 11: chip_comp/ReceiveCommandComp/sr<3> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs chip_comp/CommandAvailable .......X.XXX............................ 4 chip_comp/TCLKCounter<10> .................XXXXXXXXXXXXXX......... 14 chip_comp/CommandReceived<6> .X.....X.XXX............................ 5 chip_comp/CommandReceived<5> X......X.XXX............................ 5 chip_comp/CommandReceived<4> .......X.XXX....X....................... 5 chip_comp/CommandReceived<3> .......X.XXX...X........................ 5 chip_comp/CommandReceived<2> .......X.XXX..X......................... 5 chip_comp/CommandReceived<1> .......X.XXX.X.......................... 5 chip_comp/CommandReceived<15> .......XXXXX............................ 5 chip_comp/CommandReceived<14> ......XX.XXX............................ 5 chip_comp/CommandReceived<13> .....X.X.XXX............................ 5 chip_comp/CommandReceived<12> ....X..X.XXX............................ 5 chip_comp/CommandReceived<11> ...X...X.XXX............................ 5 chip_comp/CommandReceived<10> ..X....X.XXX............................ 5 chip_comp/CommandReceived<0> .......X.XXXX........................... 5 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB5 *********************************** Number of function block inputs used/remaining: 31/23 Number of signals used by logic mapping into function block: 31 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use chip_comp/Datasig<9> 15 10<- 0 0 FB5_1 (b) (b) ACQENnB2<0> 1 1<- /\5 0 FB5_2 34 I/O O (unused) 0 0 /\1 4 FB5_3 (b) (b) (unused) 0 0 0 5 FB5_4 (b) ACQENnB3<0> 1 0 0 4 FB5_5 35 I/O O (unused) 0 0 0 5 FB5_6 (b) (unused) 0 0 0 5 FB5_7 (b) (unused) 0 0 \/2 3 FB5_8 38 GCK/I/O (b) DATA_TSsig 4 2<- \/3 0 FB5_9 (b) (b) DATA<15> 6 3<- \/2 0 FB5_10 39 I/O O chip_comp/Datasig<14> 6 2<- \/1 0 FB5_11 (b) (b) DATA<14> 6 1<- 0 0 FB5_12 40 I/O O chip_comp/ACLKCounter<0> 0 0 \/4 1 FB5_13 (b) (b) DATA<13> 6 4<- \/3 0 FB5_14 41 I/O O DATA<12> 6 3<- \/2 0 FB5_15 43 I/O O chip_comp/Datasig<12> 6 2<- \/1 0 FB5_16 (b) (b) DATA<11> 6 1<- 0 0 FB5_17 44 I/O O (unused) 0 0 \/5 0 FB5_18 (b) (b) Signals Used by Logic in Function Block 1: DATA_TSsig 12: chip_comp/Datasig<14> 22: chip_comp/SimulData<15> 2: HFn_B<0> 13: chip_comp/Datasig<15> 23: chip_comp/StatusDataSel<0> 3: HFn_B<1> 14: chip_comp/Datasig<9> 24: chip_comp/StatusDataSel<1> 4: HFn_B<2> 15: chip_comp/GenDataCMD 25: chip_comp/StatusDataSel<2> 5: HFn_B<3> 16: chip_comp/LinkStablished 26: chip_comp/StatusDataSel<3> 6: PT1 17: chip_comp/RunningFlag 27: chip_comp/StatusDataSel<4> 7: chip_comp/ACQENnB2Reg<0> 18: chip_comp/SimulData<11> 28: chip_comp/TXREADOUTSTATE_FFd1 8: chip_comp/ACQENnB3Reg<0> 19: chip_comp/SimulData<12> 29: chip_comp/TXREADOUTSTATE_FFd2 9: chip_comp/Datasig<11> 20: chip_comp/SimulData<13> 30: chip_comp/TXREADOUTSTATE_FFd3 10: chip_comp/Datasig<12> 21: chip_comp/SimulData<14> 31: chip_comp/TXREADOUTSTATE_FFd4 11: chip_comp/Datasig<13> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs chip_comp/Datasig<9> .XXXXX.......XXX......XXXXXXXXX......... 17 ACQENnB2<0> ......X.........X....................... 2 ACQENnB3<0> .......X........X....................... 2 DATA_TSsig ...........................XXXX......... 4 DATA<15> X...........X........X.....XXXX......... 7 chip_comp/Datasig<14> .XXXX......X..XX..........XXXXX......... 12 DATA<14> X..........X........X......XXXX......... 7 chip_comp/ACLKCounter<0> ........................................ 0 DATA<13> X.........X........X.......XXXX......... 7 DATA<12> X........X........X........XXXX......... 7 chip_comp/Datasig<12> .XXXX....X....XX........X..XXXX......... 12 DATA<11> X.......X........X.........XXXX......... 7 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB6 *********************************** Number of function block inputs used/remaining: 16/38 Number of signals used by logic mapping into function block: 16 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use chip_comp/ReceiveCommandComp/sr<3> 1 0 0 4 FB6_1 (b) (b) chip_comp/ReceiveCommandComp/sr<2> 1 0 0 4 FB6_2 135 I/O (b) chip_comp/ReceiveCommandComp/sr<1> 1 0 0 4 FB6_3 136 I/O (b) chip_comp/ReceiveCommandComp/sr<19> 1 0 0 4 FB6_4 (b) (b) chip_comp/ReceiveCommandComp/sr<18> 1 0 0 4 FB6_5 137 I/O (b) chip_comp/ReceiveCommandComp/sr<17> 1 0 0 4 FB6_6 138 I/O (b) chip_comp/ReceiveCommandComp/sr<16> 1 0 0 4 FB6_7 (b) (b) chip_comp/ReceiveCommandComp/sr<15> 1 0 0 4 FB6_8 139 I/O (b) chip_comp/ReceiveCommandComp/sr<14> 1 0 0 4 FB6_9 (b) (b) chip_comp/ReceiveCommandComp/sr<13> 1 0 0 4 FB6_10 140 I/O (b) chip_comp/ReceiveCommandComp/sr<12> 1 0 0 4 FB6_11 (b) (b) chip_comp/ReceiveCommandComp/sr<11> 1 0 0 4 FB6_12 (b) (b) chip_comp/ReceiveCommandComp/sr<10> 1 0 0 4 FB6_13 (b) (b) chip_comp/ReceiveCommandComp/sr<0> 1 0 0 4 FB6_14 142 I/O (b) chip_comp/ReceiveCommandComp/clr_sr 1 0 0 4 FB6_15 143 GSR/I/O GSR/I chip_comp/CommandReceived<9> 2 0 0 3 FB6_16 (b) (b) chip_comp/CommandReceived<8> 2 0 0 3 FB6_17 (b) (b) chip_comp/CommandReceived<7> 2 0 0 3 FB6_18 (b) (b) Signals Used by Logic in Function Block 1: chip_comp/ReceiveCommandComp/clr_sr 7: chip_comp/ReceiveCommandComp/sr<15> 12: chip_comp/ReceiveCommandComp/sr<1> 2: chip_comp/ReceiveCommandComp/sr<0> 8: chip_comp/ReceiveCommandComp/sr<16> 13: chip_comp/ReceiveCommandComp/sr<20> 3: chip_comp/ReceiveCommandComp/sr<11> 9: chip_comp/ReceiveCommandComp/sr<17> 14: chip_comp/ReceiveCommandComp/sr<2> 4: chip_comp/ReceiveCommandComp/sr<12> 10: chip_comp/ReceiveCommandComp/sr<18> 15: chip_comp/ReceiveCommandComp/sr<3> 5: chip_comp/ReceiveCommandComp/sr<13> 11: chip_comp/ReceiveCommandComp/sr<19> 16: chip_comp/ReceiveCommandComp/sr<4> 6: chip_comp/ReceiveCommandComp/sr<14> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs chip_comp/ReceiveCommandComp/sr<3> X..............X........................ 2 chip_comp/ReceiveCommandComp/sr<2> X.............X......................... 2 chip_comp/ReceiveCommandComp/sr<1> X............X.......................... 2 chip_comp/ReceiveCommandComp/sr<19> X...........X........................... 2 chip_comp/ReceiveCommandComp/sr<18> X.........X............................. 2 chip_comp/ReceiveCommandComp/sr<17> X........X.............................. 2 chip_comp/ReceiveCommandComp/sr<16> X.......X............................... 2 chip_comp/ReceiveCommandComp/sr<15> X......X................................ 2 chip_comp/ReceiveCommandComp/sr<14> X.....X................................. 2 chip_comp/ReceiveCommandComp/sr<13> X....X.................................. 2 chip_comp/ReceiveCommandComp/sr<12> X...X................................... 2 chip_comp/ReceiveCommandComp/sr<11> X..X.................................... 2 chip_comp/ReceiveCommandComp/sr<10> X.X..................................... 2 chip_comp/ReceiveCommandComp/sr<0> X..........X............................ 2 chip_comp/ReceiveCommandComp/clr_sr .X.........X.XX......................... 4 chip_comp/CommandReceived<9> .....X.....X.XXX........................ 5 chip_comp/CommandReceived<8> ....X......X.XXX........................ 5 chip_comp/CommandReceived<7> ...X.......X.XXX........................ 5 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB7 *********************************** Number of function block inputs used/remaining: 31/23 Number of signals used by logic mapping into function block: 31 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 \/2 3 FB7_1 (b) (b) chip_comp/Datasig<10> 6 2<- \/1 0 FB7_2 (b) (b) DATA<10> 6 1<- 0 0 FB7_3 45 I/O O (unused) 0 0 \/2 3 FB7_4 (b) (b) DATA<9> 6 2<- \/1 0 FB7_5 46 I/O O (unused) 0 0 \/5 0 FB7_6 (b) (b) chip_comp/Datasig<5> 16 11<- 0 0 FB7_7 (b) (b) (unused) 0 0 /\5 0 FB7_8 (b) (b) (unused) 0 0 \/3 2 FB7_9 (b) (b) (unused) 0 0 \/5 0 FB7_10 (b) (b) chip_comp/Datasig<7> 16 11<- 0 0 FB7_11 (b) (b) DATA<8> 6 4<- /\3 0 FB7_12 48 I/O O (unused) 0 0 /\4 1 FB7_13 (b) (b) (unused) 0 0 \/2 3 FB7_14 (b) (b) DATA<7> 6 2<- \/1 0 FB7_15 49 I/O O (unused) 0 0 \/5 0 FB7_16 (b) (b) chip_comp/Datasig<8> 16 11<- 0 0 FB7_17 (b) (b) (unused) 0 0 /\5 0 FB7_18 (b) (b) Signals Used by Logic in Function Block 1: DATA_TSsig 12: chip_comp/Datasig<8> 22: chip_comp/StatusDataSel<0> 2: DR0 13: chip_comp/Datasig<9> 23: chip_comp/StatusDataSel<1> 3: HFn_B<0> 14: chip_comp/GenDataCMD 24: chip_comp/StatusDataSel<2> 4: HFn_B<1> 15: chip_comp/LinkStablished 25: chip_comp/StatusDataSel<3> 5: HFn_B<2> 16: chip_comp/SamplingClock<0> 26: chip_comp/StatusDataSel<4> 6: HFn_B<3> 17: chip_comp/SamplingClock<1> 27: chip_comp/TXREADOUTSTATE_FFd1 7: PT0 18: chip_comp/SimulData<10> 28: chip_comp/TXREADOUTSTATE_FFd2 8: TMODE 19: chip_comp/SimulData<7> 29: chip_comp/TXREADOUTSTATE_FFd3 9: chip_comp/Datasig<10> 20: chip_comp/SimulData<8> 30: chip_comp/TXREADOUTSTATE_FFd4 10: chip_comp/Datasig<5> 21: chip_comp/SimulData<9> 31: chip_comp/TimerInterval<1> 11: chip_comp/Datasig<7> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs chip_comp/Datasig<10> ..XXXX..X....XX......X....XXXX.......... 12 DATA<10> X.......X........X........XXXX.......... 7 DATA<9> X...........X.......X.....XXXX.......... 7 chip_comp/Datasig<5> .XXXXX...X...XX......XXXXXXXXXX......... 18 chip_comp/Datasig<7> ..XXXX.X..X..XXX.....XXXXXXXXX.......... 18 DATA<8> X..........X.......X......XXXX.......... 7 DATA<7> X.........X.......X.......XXXX.......... 7 chip_comp/Datasig<8> ..XXXXX....X.XX.X....XXXXXXXXX.......... 18 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB8 *********************************** Number of function block inputs used/remaining: 27/27 Number of signals used by logic mapping into function block: 27 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use chip_comp/SimulData<7> 1 0 /\4 0 FB8_1 (b) (b) uDw<3> 0 0 0 5 FB8_2 130 I/O O uDw<2> 0 0 0 5 FB8_3 131 I/O O chip_comp/SimulData<14> 1 0 0 4 FB8_4 (b) (b) uDw<1> 0 0 0 5 FB8_5 132 I/O O chip_comp/TXMAINSTATE_FFd2 2 0 0 3 FB8_6 (b) (b) chip_comp/LinkStablished 2 0 0 3 FB8_7 (b) (b) uDw<0> 0 0 0 5 FB8_8 133 I/O O chip_comp/GenDataCounter<6> 2 0 0 3 FB8_9 (b) (b) SYNCn 1 0 0 4 FB8_10 134 I/O O chip_comp/GenDataCounter<5> 2 0 0 3 FB8_11 (b) (b) chip_comp/GenDataCounter<4> 2 0 0 3 FB8_12 (b) (b) chip_comp/GenDataCounter<3> 2 0 0 3 FB8_13 (b) (b) chip_comp/GenDataCounter<2> 2 0 0 3 FB8_14 (b) (b) chip_comp/GenDataCounter<1> 2 0 0 3 FB8_15 (b) (b) chip_comp/TXREADOUTSTATE_FFd1 3 0 \/2 0 FB8_16 (b) (b) chip_comp/TXREADOUTSTATE_FFd3 6 2<- \/1 0 FB8_17 (b) (b) chip_comp/Datasig<13> 10 5<- 0 0 FB8_18 (b) (b) Signals Used by Logic in Function Block 1: CTRL_OK 10: chip_comp/GenDataCounter<14> 19: chip_comp/GenDatasig 2: HFn_B<0> 11: chip_comp/GenDataCounter<1> 20: chip_comp/LinkStablished 3: HFn_B<1> 12: chip_comp/GenDataCounter<2> 21: chip_comp/StatusDataSel<3> 4: HFn_B<2> 13: chip_comp/GenDataCounter<3> 22: chip_comp/TXMAINSTATE_FFd1 5: HFn_B<3> 14: chip_comp/GenDataCounter<4> 23: chip_comp/TXMAINSTATE_FFd2 6: LOCKED 15: chip_comp/GenDataCounter<5> 24: chip_comp/TXREADOUTSTATE_FFd1 7: chip_comp/Datasig<13> 16: chip_comp/GenDataCounter<6> 25: chip_comp/TXREADOUTSTATE_FFd2 8: chip_comp/GenDataCMD 17: chip_comp/GenDataCounter<7> 26: chip_comp/TXREADOUTSTATE_FFd3 9: chip_comp/GenDataCounter<0> 18: chip_comp/GenDataDonesig 27: chip_comp/TXREADOUTSTATE_FFd4 Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs chip_comp/SimulData<7> ................X....................... 1 uDw<3> ........................................ 0 uDw<2> ........................................ 0 chip_comp/SimulData<14> .........X.............................. 1 uDw<1> ........................................ 0 chip_comp/TXMAINSTATE_FFd2 X....X...............X.................. 3 chip_comp/LinkStablished ...................X.XX................. 3 uDw<0> ........................................ 0 chip_comp/GenDataCounter<6> ........X.XXXXXX..X..................... 8 SYNCn ......................X................. 1 chip_comp/GenDataCounter<5> ........X.XXXXX...X..................... 7 chip_comp/GenDataCounter<4> ........X.XXXX....X..................... 6 chip_comp/GenDataCounter<3> ........X.XXX.....X..................... 5 chip_comp/GenDataCounter<2> ........X.XX......X..................... 4 chip_comp/GenDataCounter<1> ........X.X.......X..................... 3 chip_comp/TXREADOUTSTATE_FFd1 ....X............X.....XXXX............. 6 chip_comp/TXREADOUTSTATE_FFd3 .X..X..X.........X.X...XXXX............. 9 chip_comp/Datasig<13> .XXXX.XX...........XX..XXXX............. 12 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB9 *********************************** Number of function block inputs used/remaining: 31/23 Number of signals used by logic mapping into function block: 31 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use chip_comp/TXREADOUTSTATE_FFd4 12 9<- \/2 0 FB9_1 (b) (b) DATA<6> 6 2<- \/1 0 FB9_2 50 I/O O DATA<5> 6 1<- 0 0 FB9_3 51 I/O O (unused) 0 0 \/3 2 FB9_4 (b) (b) DATA<4> 6 3<- \/2 0 FB9_5 52 I/O O DATA<3> 6 2<- \/1 0 FB9_6 53 I/O O chip_comp/GenDatasig 5 1<- \/1 0 FB9_7 (b) (b) DATA<2> 6 1<- 0 0 FB9_8 54 I/O O (unused) 0 0 \/5 0 FB9_9 (b) (b) chip_comp/Datasig<15> 10 5<- 0 0 FB9_10 (b) (b) DATA<1> 6 1<- 0 0 FB9_11 56 I/O O DATA<0> 6 2<- /\1 0 FB9_12 57 I/O O chip_comp/TXREADOUTSTATE_FFd2 7 4<- /\2 0 FB9_13 (b) (b) RST4n_B<0> 1 0 /\4 0 FB9_14 58 I/O O (unused) 0 0 \/5 0 FB9_15 (b) (b) chip_comp/Datasig<11> 10 5<- 0 0 FB9_16 (b) (b) D_OEn_B<0> 1 0 \/4 0 FB9_17 59 I/O O (unused) 0 0 \/5 0 FB9_18 (b) (b) Signals Used by Logic in Function Block 1: DATA_TSsig 12: chip_comp/Datasig<2> 22: chip_comp/SimulData<2> 2: HFn_B<0> 13: chip_comp/Datasig<3> 23: chip_comp/SimulData<3> 3: HFn_B<1> 14: chip_comp/Datasig<4> 24: chip_comp/SimulData<4> 4: HFn_B<2> 15: chip_comp/Datasig<5> 25: chip_comp/SimulData<5> 5: HFn_B<3> 16: chip_comp/Datasig<6> 26: chip_comp/SimulData<6> 6: RST4n_B<0> 17: chip_comp/GenDataCMD 27: chip_comp/StatusDataSel<1> 7: chip_comp/DataPackageTXEn 18: chip_comp/GenDataDonesig 28: chip_comp/TXREADOUTSTATE_FFd1 8: chip_comp/Datasig<0> 19: chip_comp/LinkStablished 29: chip_comp/TXREADOUTSTATE_FFd2 9: chip_comp/Datasig<11> 20: chip_comp/SimulData<0> 30: chip_comp/TXREADOUTSTATE_FFd3 10: chip_comp/Datasig<15> 21: chip_comp/SimulData<1> 31: chip_comp/TXREADOUTSTATE_FFd4 11: chip_comp/Datasig<1> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs chip_comp/TXREADOUTSTATE_FFd4 .XXXX.X.........XXX........XXXX......... 12 DATA<6> X..............X.........X.XXXX......... 7 DATA<5> X.............X.........X..XXXX......... 7 DATA<4> X............X.........X...XXXX......... 7 DATA<3> X...........X.........X....XXXX......... 7 chip_comp/GenDatasig .XXXX......................XXXX......... 8 DATA<2> X..........X.........X.....XXXX......... 7 chip_comp/Datasig<15> .XXXX....X......X.X........XXXX......... 11 DATA<1> X.........X.........X......XXXX......... 7 DATA<0> X......X...........X.......XXXX......... 7 chip_comp/TXREADOUTSTATE_FFd2 .XXXX.X.........XXX........XXXX......... 12 RST4n_B<0> .....X.....................XXXX......... 5 chip_comp/Datasig<11> .XXXX...X.......X.X.......XXXXX......... 12 D_OEn_B<0> ...........................XXXX......... 4 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB10 *********************************** Number of function block inputs used/remaining: 11/43 Number of signals used by logic mapping into function block: 11 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use chip_comp/SimulData<0> 1 0 0 4 FB10_1 (b) (b) chip_comp/ReceiveCommandComp/sr<9> 1 0 0 4 FB10_2 117 I/O (b) chip_comp/ReceiveCommandComp/sr<8> 1 0 0 4 FB10_3 118 I/O (b) chip_comp/ReceiveCommandComp/sr<7> 1 0 0 4 FB10_4 (b) (b) uD_OEn_B<0> 0 0 0 5 FB10_5 119 I/O O uD_OEn_B<1> 0 0 0 5 FB10_6 120 I/O O chip_comp/ReceiveCommandComp/sr<6> 1 0 0 4 FB10_7 (b) (b) uD_OEn_B<2> 0 0 0 5 FB10_8 121 I/O O chip_comp/ReceiveCommandComp/sr<5> 1 0 0 4 FB10_9 (b) (b) uD_OEn_B<3> 0 0 0 5 FB10_10 124 I/O O uDw<7> 0 0 0 5 FB10_11 125 I/O O uDw<6> 0 0 0 5 FB10_12 126 I/O O chip_comp/ReceiveCommandComp/sr<4> 1 0 0 4 FB10_13 (b) (b) uDw<5> 0 0 0 5 FB10_14 128 I/O O chip_comp/ReceiveCommandComp/sr<20> 1 0 0 4 FB10_15 (b) (b) chip_comp/GenDataCounter<0> 1 0 0 4 FB10_16 (b) (b) uDw<4> 0 0 0 5 FB10_17 129 I/O O chip_comp/ACLKsig_1 1 0 0 4 FB10_18 (b) (b) Signals Used by Logic in Function Block 1: ACLK 5: chip_comp/ReceiveCommandComp/clr_sr 9: chip_comp/ReceiveCommandComp/sr<7> 2: CTRL 6: chip_comp/ReceiveCommandComp/sr<10> 10: chip_comp/ReceiveCommandComp/sr<8> 3: chip_comp/GenDataCounter<0> 7: chip_comp/ReceiveCommandComp/sr<5> 11: chip_comp/ReceiveCommandComp/sr<9> 4: chip_comp/GenDatasig 8: chip_comp/ReceiveCommandComp/sr<6> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs chip_comp/SimulData<0> ..X..................................... 1 chip_comp/ReceiveCommandComp/sr<9> ....XX.................................. 2 chip_comp/ReceiveCommandComp/sr<8> ....X.....X............................. 2 chip_comp/ReceiveCommandComp/sr<7> ....X....X.............................. 2 uD_OEn_B<0> ........................................ 0 uD_OEn_B<1> ........................................ 0 chip_comp/ReceiveCommandComp/sr<6> ....X...X............................... 2 uD_OEn_B<2> ........................................ 0 chip_comp/ReceiveCommandComp/sr<5> ....X..X................................ 2 uD_OEn_B<3> ........................................ 0 uDw<7> ........................................ 0 uDw<6> ........................................ 0 chip_comp/ReceiveCommandComp/sr<4> ....X.X................................. 2 uDw<5> ........................................ 0 chip_comp/ReceiveCommandComp/sr<20> .X..X................................... 2 chip_comp/GenDataCounter<0> ..XX.................................... 2 uDw<4> ........................................ 0 chip_comp/ACLKsig_1 X....................................... 1 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB11 *********************************** Number of function block inputs used/remaining: 32/22 Number of signals used by logic mapping into function block: 32 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use chip_comp/Datasig<0> 18 13<- 0 0 FB11_1 (b) (b) (unused) 0 0 /\5 0 FB11_2 (b) (b) RCLK4_B<0> 1 0 /\3 1 FB11_3 60 I/O O chip_comp/Datasig<4> 8 3<- 0 0 FB11_4 (b) (b) RST4n_B<1> 1 0 /\3 1 FB11_5 61 I/O O (unused) 0 0 0 5 FB11_6 (b) (unused) 0 0 0 5 FB11_7 (b) (unused) 0 0 0 5 FB11_8 (b) (unused) 0 0 0 5 FB11_9 (b) D_OEn_B<1> 1 0 0 4 FB11_10 64 I/O O RCLK4_B<1> 1 0 0 4 FB11_11 66 I/O O RST4n_B<2> 1 0 0 4 FB11_12 68 I/O O (unused) 0 0 \/1 4 FB11_13 (b) (b) D_OEn_B<2> 1 1<- \/5 0 FB11_14 69 I/O O chip_comp/Datasig<2> 18 13<- 0 0 FB11_15 (b) (b) (unused) 0 0 /\5 0 FB11_16 (b) (b) RCLK4_B<2> 1 0 /\3 1 FB11_17 70 I/O O (unused) 0 0 \/5 0 FB11_18 (b) (b) Signals Used by Logic in Function Block 1: CLK_40MHZ 12: chip_comp/ACQENnB2Reg<0> 23: chip_comp/StatusDataSel<0> 2: HFn_B<0> 13: chip_comp/ACQENnB2Reg<2> 24: chip_comp/StatusDataSel<1> 3: HFn_B<1> 14: chip_comp/ACQENnB3Reg<0> 25: chip_comp/StatusDataSel<2> 4: HFn_B<2> 15: chip_comp/ACQENnB3Reg<2> 26: chip_comp/StatusDataSel<3> 5: HFn_B<3> 16: chip_comp/Datasig<0> 27: chip_comp/StatusDataSel<4> 6: RST4n_B<1> 17: chip_comp/Datasig<2> 28: chip_comp/TXREADOUTSTATE_FFd1 7: RST4n_B<2> 18: chip_comp/Datasig<4> 29: chip_comp/TXREADOUTSTATE_FFd2 8: chip_comp/ACQENnB0Reg<0> 19: chip_comp/ENABLEn_BReg<0> 30: chip_comp/TXREADOUTSTATE_FFd3 9: chip_comp/ACQENnB0Reg<2> 20: chip_comp/ENABLEn_BReg<2> 31: chip_comp/TXREADOUTSTATE_FFd4 10: chip_comp/ACQENnB1Reg<0> 21: chip_comp/GenDataCMD 32: chip_comp/TimerInterval<0> 11: chip_comp/ACQENnB1Reg<2> 22: chip_comp/LinkStablished Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs chip_comp/Datasig<0> .XXXX..X.X.X.X.X..X.XXXXXXXXXXX......... 21 RCLK4_B<0> X..........................X.X.......... 3 chip_comp/Datasig<4> .XXXX............X..XXXXXXXXXXXX........ 17 RST4n_B<1> .....X.....................XXXX......... 5 D_OEn_B<1> ...........................XXXX......... 4 RCLK4_B<1> X..........................X.X.......... 3 RST4n_B<2> ......X....................XXXX......... 5 D_OEn_B<2> ...........................XXXX......... 4 chip_comp/Datasig<2> .XXXX...X.X.X.X.X..XXXXXXXXXXXX......... 21 RCLK4_B<2> X..........................X.X.......... 3 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB12 *********************************** Number of function block inputs used/remaining: 12/42 Number of signals used by logic mapping into function block: 12 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB12_1 (b) (unused) 0 0 0 5 FB12_2 110 I/O (unused) 0 0 0 5 FB12_3 111 I/O (unused) 0 0 0 5 FB12_4 (b) (unused) 0 0 0 5 FB12_5 112 I/O (unused) 0 0 0 5 FB12_6 (b) chip_comp/SimulData<8> 1 0 0 4 FB12_7 (b) (b) chip_comp/SimulData<6> 1 0 0 4 FB12_8 113 I/O (b) chip_comp/SimulData<5> 1 0 0 4 FB12_9 (b) (b) chip_comp/SimulData<4> 1 0 0 4 FB12_10 115 I/O (b) chip_comp/SimulData<3> 1 0 0 4 FB12_11 (b) (b) chip_comp/SimulData<2> 1 0 0 4 FB12_12 116 I/O (b) chip_comp/SimulData<1> 1 0 0 4 FB12_13 (b) (b) chip_comp/SimulData<15> 1 0 0 4 FB12_14 (b) (b) chip_comp/SimulData<13> 1 0 0 4 FB12_15 (b) (b) chip_comp/SimulData<12> 1 0 0 4 FB12_16 (b) (b) chip_comp/SimulData<11> 1 0 0 4 FB12_17 (b) (b) chip_comp/SimulData<10> 1 0 0 4 FB12_18 (b) (b) Signals Used by Logic in Function Block 1: chip_comp/GenDataCounter<10> 5: chip_comp/GenDataCounter<15> 9: chip_comp/GenDataCounter<4> 2: chip_comp/GenDataCounter<11> 6: chip_comp/GenDataCounter<1> 10: chip_comp/GenDataCounter<5> 3: chip_comp/GenDataCounter<12> 7: chip_comp/GenDataCounter<2> 11: chip_comp/GenDataCounter<6> 4: chip_comp/GenDataCounter<13> 8: chip_comp/GenDataCounter<3> 12: chip_comp/GenDataCounter<8> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs chip_comp/SimulData<8> ...........X............................ 1 chip_comp/SimulData<6> ..........X............................. 1 chip_comp/SimulData<5> .........X.............................. 1 chip_comp/SimulData<4> ........X............................... 1 chip_comp/SimulData<3> .......X................................ 1 chip_comp/SimulData<2> ......X................................. 1 chip_comp/SimulData<1> .....X.................................. 1 chip_comp/SimulData<15> ....X................................... 1 chip_comp/SimulData<13> ...X.................................... 1 chip_comp/SimulData<12> ..X..................................... 1 chip_comp/SimulData<11> .X...................................... 1 chip_comp/SimulData<10> X....................................... 1 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB13 *********************************** Number of function block inputs used/remaining: 32/22 Number of signals used by logic mapping into function block: 32 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 /\5 0 FB13_1 (b) (b) RST4n_B<3> 1 0 /\2 2 FB13_2 71 I/O O (unused) 0 0 \/5 0 FB13_3 (b) (b) chip_comp/Datasig<6> 16 11<- 0 0 FB13_4 (b) (b) (unused) 0 0 /\5 0 FB13_5 (b) (b) (unused) 0 0 /\1 4 FB13_6 (b) (b) (unused) 0 0 0 5 FB13_7 (b) D_OEn_B<3> 1 0 0 4 FB13_8 74 I/O O (unused) 0 0 0 5 FB13_9 (b) (unused) 0 0 0 5 FB13_10 (b) RCLK4_B<3> 1 0 \/2 2 FB13_11 75 I/O O (unused) 0 0 \/5 0 FB13_12 (b) (b) chip_comp/Datasig<3> 17 12<- 0 0 FB13_13 (b) (b) DAC_LOADn 1 1<- /\5 0 FB13_14 76 I/O O DAC_DIN 0 0 /\1 4 FB13_15 77 I/O O (unused) 0 0 0 5 FB13_16 (b) (b) DAC_SCLK 1 1<- \/5 0 FB13_17 78 I/O O chip_comp/Datasig<1> 17 12<- 0 0 FB13_18 (b) (b) Signals Used by Logic in Function Block 1: CLK_40MHZ 12: chip_comp/ACQENnB2Reg<1> 23: chip_comp/StatusDataSel<0> 2: DR1 13: chip_comp/ACQENnB2Reg<3> 24: chip_comp/StatusDataSel<1> 3: HFn_B<0> 14: chip_comp/ACQENnB3Reg<1> 25: chip_comp/StatusDataSel<2> 4: HFn_B<1> 15: chip_comp/ACQENnB3Reg<3> 26: chip_comp/StatusDataSel<3> 5: HFn_B<2> 16: chip_comp/Datasig<1> 27: chip_comp/StatusDataSel<4> 6: HFn_B<3> 17: chip_comp/Datasig<3> 28: chip_comp/TXREADOUTSTATE_FFd1 7: RST4n_B<3> 18: chip_comp/Datasig<6> 29: chip_comp/TXREADOUTSTATE_FFd2 8: chip_comp/ACQENnB0Reg<1> 19: chip_comp/ENABLEn_BReg<1> 30: chip_comp/TXREADOUTSTATE_FFd3 9: chip_comp/ACQENnB0Reg<3> 20: chip_comp/ENABLEn_BReg<3> 31: chip_comp/TXREADOUTSTATE_FFd4 10: chip_comp/ACQENnB1Reg<1> 21: chip_comp/GenDataCMD 32: chip_comp/TimerInterval<2> 11: chip_comp/ACQENnB1Reg<3> 22: chip_comp/LinkStablished Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs RST4n_B<3> ......X....................XXXX......... 5 chip_comp/Datasig<6> .XXXXX...........X..XXXXXXXXXXXX........ 18 D_OEn_B<3> ...........................XXXX......... 4 RCLK4_B<3> X..........................X.X.......... 3 chip_comp/Datasig<3> ..XXXX..X.X.X.X.X..XXXXXXXXXXXX......... 21 DAC_LOADn ........................................ 0 DAC_DIN ........................................ 0 DAC_SCLK ........................................ 0 chip_comp/Datasig<1> ..XXXX.X.X.X.X.X..X.XXXXXXXXXXX......... 21 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB14 *********************************** Number of function block inputs used/remaining: 28/26 Number of signals used by logic mapping into function block: 28 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use chip_comp/TimerRestCMD 2 0 0 3 FB14_1 (b) (b) chip_comp/TimerInterval<2> 2 0 0 3 FB14_2 (b) (b) ADCRST 2 0 0 3 FB14_3 100 I/O O chip_comp/TimerInterval<0> 2 0 0 3 FB14_4 (b) (b) chip_comp/StatusDataSel<4> 2 0 0 3 FB14_5 101 I/O (b) chip_comp/StatusDataSel<3> 2 0 0 3 FB14_6 102 I/O (b) chip_comp/StatusDataSel<2> 2 0 0 3 FB14_7 (b) (b) chip_comp/StatusDataSel<0> 2 0 0 3 FB14_8 103 I/O (b) chip_comp/SamplingClock<0> 2 0 0 3 FB14_9 (b) (b) chip_comp/GenDataCMD 2 0 0 3 FB14_10 104 I/O (b) RESETn 1 0 0 4 FB14_11 105 I/O O chip_comp/ENABLEn_BReg<3> 2 0 0 3 FB14_12 (b) (b) chip_comp/ENABLEn_BReg<2> 2 0 0 3 FB14_13 (b) (b) RST_TIMERn 2 0 0 3 FB14_14 106 I/O O chip_comp/DataPackageTXEn 2 0 0 3 FB14_15 107 I/O (b) chip_comp/ACQENnB3Reg<3> 2 0 0 3 FB14_16 (b) (b) chip_comp/ACQENnB3Reg<2> 2 0 0 3 FB14_17 (b) (b) chip_comp/RunningFlag 3 0 0 2 FB14_18 (b) (b) Signals Used by Logic in Function Block 1: ACLK 11: chip_comp/CommandReceived<12> 20: chip_comp/CommandReceived<7> 2: ADCRST 12: chip_comp/CommandReceived<13> 21: chip_comp/CommandReceived<8> 3: POR 13: chip_comp/CommandReceived<14> 22: chip_comp/CommandReceived<9> 4: RST_TIMERn 14: chip_comp/CommandReceived<15> 23: chip_comp/GenDataCMD 5: TCLK 15: chip_comp/CommandReceived<2> 24: chip_comp/RunningFlag 6: chip_comp/ACLKsig_1 16: chip_comp/CommandReceived<3> 25: chip_comp/TCLKsig_1 7: chip_comp/ADCRestCMD 17: chip_comp/CommandReceived<4> 26: chip_comp/TXMAINSTATE_FFd1 8: chip_comp/CommandReceived<0> 18: chip_comp/CommandReceived<5> 27: chip_comp/TXMAINSTATE_FFd2 9: chip_comp/CommandReceived<10> 19: chip_comp/CommandReceived<6> 28: chip_comp/TimerRestCMD 10: chip_comp/CommandReceived<11> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs chip_comp/TimerRestCMD ........XXXXXX......XX...XXX............ 11 chip_comp/TimerInterval<2> ........XXXXXXX.....XX...X.............. 10 ADCRST XX...XX................................. 4 chip_comp/TimerInterval<0> .......XXXXXXX......XX...X.............. 10 chip_comp/StatusDataSel<4> ........XXXXXX..X...XX...X.............. 10 chip_comp/StatusDataSel<3> ........XXXXXX.X....XX...X.............. 10 chip_comp/StatusDataSel<2> ........XXXXXXX.....XX...X.............. 10 chip_comp/StatusDataSel<0> .......XXXXXXX......XX...X.............. 10 chip_comp/SamplingClock<0> .......XXXXXXX......XX...X.............. 10 chip_comp/GenDataCMD ........XXXXXX......XXX..XX............. 11 RESETn ..X..................................... 1 chip_comp/ENABLEn_BReg<3> ........XXXXXX.XXXXXXX.X.X.............. 15 chip_comp/ENABLEn_BReg<2> ........XXXXXXX.XXXXXX.X.X.............. 15 RST_TIMERn ...XX...................X..X............ 4 chip_comp/DataPackageTXEn .......XXXXXXX......XX...X.............. 10 chip_comp/ACQENnB3Reg<3> ........XXXXXX.XXXXXXX.X.X.............. 15 chip_comp/ACQENnB3Reg<2> ........XXXXXXX.XXXXXX.X.X.............. 15 chip_comp/RunningFlag ........XXXXXX......XX.X.X.............. 10 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB15 *********************************** Number of function block inputs used/remaining: 22/32 Number of signals used by logic mapping into function block: 22 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use chip_comp/GenDataDonesig 1 0 0 4 FB15_1 (b) (b) DAC_CSn_B<0> 0 0 0 5 FB15_2 79 I/O O DAC_CSn_B<1> 0 0 0 5 FB15_3 80 I/O O chip_comp/GenDataCounter<9> 2 0 0 3 FB15_4 (b) (b) chip_comp/GenDataCounter<8> 2 0 0 3 FB15_5 (b) (b) chip_comp/GenDataCounter<7> 2 0 0 3 FB15_6 (b) (b) chip_comp/GenDataCounter<15> 2 0 0 3 FB15_7 (b) (b) DAC_CSn_B<2> 0 0 0 5 FB15_8 81 I/O O chip_comp/GenDataCounter<14> 2 0 0 3 FB15_9 (b) (b) DAC_CSn_B<3> 0 0 0 5 FB15_10 82 I/O O chip_comp/GenDataCounter<13> 2 0 0 3 FB15_11 83 I/O (b) ENABLEn_B<3> 1 0 0 4 FB15_12 85 I/O O chip_comp/GenDataCounter<12> 2 0 0 3 FB15_13 (b) (b) ENABLEn_B<2> 1 0 0 4 FB15_14 86 I/O O ENABLEn_B<1> 1 0 0 4 FB15_15 87 I/O O chip_comp/GenDataCounter<11> 2 0 0 3 FB15_16 (b) (b) ENABLEn_B<0> 1 0 0 4 FB15_17 88 I/O O chip_comp/GenDataCounter<10> 2 0 0 3 FB15_18 (b) (b) Signals Used by Logic in Function Block 1: chip_comp/ENABLEn_BReg<0> 9: chip_comp/GenDataCounter<13> 16: chip_comp/GenDataCounter<5> 2: chip_comp/ENABLEn_BReg<1> 10: chip_comp/GenDataCounter<14> 17: chip_comp/GenDataCounter<6> 3: chip_comp/ENABLEn_BReg<2> 11: chip_comp/GenDataCounter<15> 18: chip_comp/GenDataCounter<7> 4: chip_comp/ENABLEn_BReg<3> 12: chip_comp/GenDataCounter<1> 19: chip_comp/GenDataCounter<8> 5: chip_comp/GenDataCounter<0> 13: chip_comp/GenDataCounter<2> 20: chip_comp/GenDataCounter<9> 6: chip_comp/GenDataCounter<10> 14: chip_comp/GenDataCounter<3> 21: chip_comp/GenDatasig 7: chip_comp/GenDataCounter<11> 15: chip_comp/GenDataCounter<4> 22: chip_comp/RunningFlag 8: chip_comp/GenDataCounter<12> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs chip_comp/GenDataDonesig ....XXXXXXXXXXXXXXXX.................... 16 DAC_CSn_B<0> ........................................ 0 DAC_CSn_B<1> ........................................ 0 chip_comp/GenDataCounter<9> ....X......XXXXXXXXXX................... 11 chip_comp/GenDataCounter<8> ....X......XXXXXXXX.X................... 10 chip_comp/GenDataCounter<7> ....X......XXXXXXX..X................... 9 chip_comp/GenDataCounter<15> ....XXXXXXXXXXXXXXXXX................... 17 DAC_CSn_B<2> ........................................ 0 chip_comp/GenDataCounter<14> ....XXXXXX.XXXXXXXXXX................... 16 DAC_CSn_B<3> ........................................ 0 chip_comp/GenDataCounter<13> ....XXXXX..XXXXXXXXXX................... 15 ENABLEn_B<3> ...X.................X.................. 2 chip_comp/GenDataCounter<12> ....XXXX...XXXXXXXXXX................... 14 ENABLEn_B<2> ..X..................X.................. 2 ENABLEn_B<1> .X...................X.................. 2 chip_comp/GenDataCounter<11> ....XXX....XXXXXXXXXX................... 13 ENABLEn_B<0> X....................X.................. 2 chip_comp/GenDataCounter<10> ....XX.....XXXXXXXXXX................... 12 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB16 *********************************** Number of function block inputs used/remaining: 17/37 Number of signals used by logic mapping into function block: 17 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use chip_comp/ENABLEn_BReg<1> 2 0 0 3 FB16_1 (b) (b) chip_comp/ENABLEn_BReg<0> 2 0 0 3 FB16_2 91 I/O I chip_comp/ACQENnB3Reg<1> 2 0 0 3 FB16_3 92 I/O (b) chip_comp/ACQENnB3Reg<0> 2 0 0 3 FB16_4 (b) (b) chip_comp/ACQENnB2Reg<2> 2 0 0 3 FB16_5 93 I/O I PT0 2 0 0 3 FB16_6 94 I/O O chip_comp/ACQENnB2Reg<1> 2 0 0 3 FB16_7 (b) (b) PT1 2 0 0 3 FB16_8 95 I/O O chip_comp/ACQENnB2Reg<0> 2 0 0 3 FB16_9 (b) (b) DR0 2 0 0 3 FB16_10 96 I/O O DR1 2 0 0 3 FB16_11 97 I/O O TMODE 2 0 0 3 FB16_12 98 I/O O chip_comp/ACQENnB1Reg<2> 2 0 0 3 FB16_13 (b) (b) chip_comp/ACQENnB1Reg<1> 2 0 0 3 FB16_14 (b) (b) chip_comp/ACQENnB1Reg<0> 2 0 0 3 FB16_15 (b) (b) chip_comp/ACQENnB0Reg<2> 2 0 0 3 FB16_16 (b) (b) chip_comp/ACQENnB0Reg<1> 2 0 0 3 FB16_17 (b) (b) chip_comp/ACQENnB0Reg<0> 2 0 0 3 FB16_18 (b) (b) Signals Used by Logic in Function Block 1: chip_comp/CommandReceived<0> 7: chip_comp/CommandReceived<15> 13: chip_comp/CommandReceived<7> 2: chip_comp/CommandReceived<10> 8: chip_comp/CommandReceived<1> 14: chip_comp/CommandReceived<8> 3: chip_comp/CommandReceived<11> 9: chip_comp/CommandReceived<2> 15: chip_comp/CommandReceived<9> 4: chip_comp/CommandReceived<12> 10: chip_comp/CommandReceived<4> 16: chip_comp/RunningFlag 5: chip_comp/CommandReceived<13> 11: chip_comp/CommandReceived<5> 17: chip_comp/TXMAINSTATE_FFd1 6: chip_comp/CommandReceived<14> 12: chip_comp/CommandReceived<6> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs chip_comp/ENABLEn_BReg<1> .XXXXXXX.XXXXXXXX....................... 15 chip_comp/ENABLEn_BReg<0> XXXXXXX..XXXXXXXX....................... 15 chip_comp/ACQENnB3Reg<1> .XXXXXXX.XXXXXXXX....................... 15 chip_comp/ACQENnB3Reg<0> XXXXXXX..XXXXXXXX....................... 15 chip_comp/ACQENnB2Reg<2> .XXXXXX.XXXXXXXXX....................... 15 PT0 XXXXXXX......XX.X....................... 10 chip_comp/ACQENnB2Reg<1> .XXXXXXX.XXXXXXXX....................... 15 PT1 .XXXXXXX.....XX.X....................... 10 chip_comp/ACQENnB2Reg<0> XXXXXXX..XXXXXXXX....................... 15 DR0 XXXXXXX......XX.X....................... 10 DR1 .XXXXXXX.....XX.X....................... 10 TMODE XXXXXXX......XX.X....................... 10 chip_comp/ACQENnB1Reg<2> .XXXXXX.XXXXXXXXX....................... 15 chip_comp/ACQENnB1Reg<1> .XXXXXXX.XXXXXXXX....................... 15 chip_comp/ACQENnB1Reg<0> XXXXXXX..XXXXXXXX....................... 15 chip_comp/ACQENnB0Reg<2> .XXXXXX.XXXXXXXXX....................... 15 chip_comp/ACQENnB0Reg<1> .XXXXXXX.XXXXXXXX....................... 15 chip_comp/ACQENnB0Reg<0> XXXXXXX..XXXXXXXX....................... 15 0----+----1----+----2----+----3----+----4 0 0 0 0 ******************************* Equations ******************************** ********** Mapped Logic ********** FTCPE_ACLK: FTCPE port map (ACLK,'1',CLK_40MHZ,POR,'0',ACLK_CE); ACLK_CE <= (NOT chip_comp/ACLKCounter(0) AND NOT chip_comp/ACLKCounter(1) AND NOT chip_comp/ACLKCounter(2) AND NOT chip_comp/ACLKCounter(3) AND NOT chip_comp/ACLKCounter(4) AND NOT chip_comp/ACLKCounter(5) AND NOT chip_comp/ACLKCounter(6) AND NOT chip_comp/ACLKCounter(7) AND NOT chip_comp/ACLKCounter(8)); FDCPE_ACQENnB00: FDCPE port map (ACQENnB0(0),ACQENnB0_D(0),CLK_40MHZ,'0',POR); ACQENnB0_D(0) <= (chip_comp/RunningFlag AND chip_comp/ACQENnB0Reg(0)); FDCPE_ACQENnB01: FDCPE port map (ACQENnB0(1),ACQENnB0_D(1),CLK_40MHZ,'0',POR); ACQENnB0_D(1) <= (chip_comp/RunningFlag AND chip_comp/ACQENnB0Reg(1)); FDCPE_ACQENnB02: FDCPE port map (ACQENnB0(2),ACQENnB0_D(2),CLK_40MHZ,'0',POR); ACQENnB0_D(2) <= (chip_comp/RunningFlag AND chip_comp/ACQENnB0Reg(2)); FDCPE_ACQENnB03: FDCPE port map (ACQENnB0(3),ACQENnB0_D(3),CLK_40MHZ,'0',POR); ACQENnB0_D(3) <= (chip_comp/RunningFlag AND chip_comp/ACQENnB0Reg(3)); FDCPE_ACQENnB10: FDCPE port map (ACQENnB1(0),ACQENnB1_D(0),CLK_40MHZ,'0',POR); ACQENnB1_D(0) <= (chip_comp/RunningFlag AND chip_comp/ACQENnB1Reg(0)); FDCPE_ACQENnB11: FDCPE port map (ACQENnB1(1),ACQENnB1_D(1),CLK_40MHZ,'0',POR); ACQENnB1_D(1) <= (chip_comp/RunningFlag AND chip_comp/ACQENnB1Reg(1)); FDCPE_ACQENnB12: FDCPE port map (ACQENnB1(2),ACQENnB1_D(2),CLK_40MHZ,'0',POR); ACQENnB1_D(2) <= (chip_comp/RunningFlag AND chip_comp/ACQENnB1Reg(2)); FDCPE_ACQENnB13: FDCPE port map (ACQENnB1(3),ACQENnB1_D(3),CLK_40MHZ,'0',POR); ACQENnB1_D(3) <= (chip_comp/RunningFlag AND chip_comp/ACQENnB1Reg(3)); FDCPE_ACQENnB20: FDCPE port map (ACQENnB2(0),EXP19_.EXP,CLK_40MHZ,'0',POR); FDCPE_ACQENnB21: FDCPE port map (ACQENnB2(1),ACQENnB2_D(1),CLK_40MHZ,'0',POR); ACQENnB2_D(1) <= (chip_comp/RunningFlag AND chip_comp/ACQENnB2Reg(1)); FDCPE_ACQENnB22: FDCPE port map (ACQENnB2(2),ACQENnB2_D(2),CLK_40MHZ,'0',POR); ACQENnB2_D(2) <= (chip_comp/RunningFlag AND chip_comp/ACQENnB2Reg(2)); FDCPE_ACQENnB23: FDCPE port map (ACQENnB2(3),ACQENnB2_D(3),CLK_40MHZ,'0',POR); ACQENnB2_D(3) <= (chip_comp/RunningFlag AND chip_comp/ACQENnB2Reg(3)); FDCPE_ACQENnB30: FDCPE port map (ACQENnB3(0),ACQENnB3_D(0),CLK_40MHZ,'0',POR); ACQENnB3_D(0) <= (chip_comp/RunningFlag AND chip_comp/ACQENnB3Reg(0)); FDCPE_ACQENnB31: FDCPE port map (ACQENnB3(1),ACQENnB3_D(1),CLK_40MHZ,'0',POR); ACQENnB3_D(1) <= (chip_comp/RunningFlag AND chip_comp/ACQENnB3Reg(1)); FDCPE_ACQENnB32: FDCPE port map (ACQENnB3(2),ACQENnB3_D(2),CLK_40MHZ,'0',POR); ACQENnB3_D(2) <= (chip_comp/RunningFlag AND chip_comp/ACQENnB3Reg(2)); FDCPE_ACQENnB33: FDCPE port map (ACQENnB3(3),ACQENnB3_D(3),CLK_40MHZ,'0',POR); ACQENnB3_D(3) <= (chip_comp/RunningFlag AND chip_comp/ACQENnB3Reg(3)); FDCPE_ADCRST: FDCPE port map (ADCRST,ADCRST_D,CLK_40MHZ,'0',POR); ADCRST_D <= ((NOT ADCRST AND NOT chip_comp/ADCRestCMD) OR (ACLK AND NOT chip_comp/ADCRestCMD AND NOT chip_comp/ACLKsig_1)); DAC_CSn_B(0) <= '1'; DAC_CSn_B(1) <= '1'; DAC_CSn_B(2) <= '1'; DAC_CSn_B(3) <= '1'; DAC_DIN <= '0'; DAC_LOADn <= DAC_DINsig$BUF9.EXP; DAC_SCLK <= EXP45_.EXP; DATA_I(0) <= ((chip_comp/TXREADOUTSTATE_FFd2.EXP) OR (chip_comp/TXREADOUTSTATE_FFd3 AND chip_comp/Datasig(0)) OR (NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/Datasig(0)) OR (chip_comp/TXREADOUTSTATE_FFd2 AND chip_comp/Datasig(0))); DATA(0) <= DATA_I(0) when DATA_OE(0) = '1' else 'Z'; DATA_OE(0) <= NOT DATA_TSsig; DATA_I(1) <= ((Datasig(0).EXP) OR (chip_comp/TXREADOUTSTATE_FFd3 AND chip_comp/Datasig(1)) OR (NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/Datasig(1)) OR (chip_comp/TXREADOUTSTATE_FFd2 AND chip_comp/Datasig(1)) OR (chip_comp/TXREADOUTSTATE_FFd1 AND chip_comp/Datasig(1))); DATA(1) <= DATA_I(1) when DATA_OE(1) = '1' else 'Z'; DATA_OE(1) <= NOT DATA_TSsig; DATA_I(2) <= ((chip_comp/GenDatasig.EXP) OR (chip_comp/TXREADOUTSTATE_FFd3 AND chip_comp/Datasig(2)) OR (NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/Datasig(2)) OR (chip_comp/TXREADOUTSTATE_FFd2 AND chip_comp/Datasig(2)) OR (chip_comp/TXREADOUTSTATE_FFd1 AND chip_comp/Datasig(2))); DATA(2) <= DATA_I(2) when DATA_OE(2) = '1' else 'Z'; DATA_OE(2) <= NOT DATA_TSsig; DATA_I(3) <= ((Datasig(4).EXP) OR (chip_comp/TXREADOUTSTATE_FFd3 AND chip_comp/Datasig(3)) OR (NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/Datasig(3)) OR (chip_comp/TXREADOUTSTATE_FFd2 AND chip_comp/Datasig(3))); DATA(3) <= DATA_I(3) when DATA_OE(3) = '1' else 'Z'; DATA_OE(3) <= NOT DATA_TSsig; DATA_I(4) <= ((EXP32_.EXP) OR (chip_comp/TXREADOUTSTATE_FFd3 AND chip_comp/Datasig(4)) OR (NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/Datasig(4))); DATA(4) <= DATA_I(4) when DATA_OE(4) = '1' else 'Z'; DATA_OE(4) <= NOT DATA_TSsig; DATA_I(5) <= ((Datasig(6).EXP) OR (chip_comp/TXREADOUTSTATE_FFd3 AND chip_comp/Datasig(5)) OR (NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/Datasig(5)) OR (chip_comp/TXREADOUTSTATE_FFd2 AND chip_comp/Datasig(5)) OR (chip_comp/TXREADOUTSTATE_FFd1 AND chip_comp/Datasig(5))); DATA(5) <= DATA_I(5) when DATA_OE(5) = '1' else 'Z'; DATA_OE(5) <= NOT DATA_TSsig; DATA_I(6) <= ((chip_comp/TXREADOUTSTATE_FFd4.EXP) OR (chip_comp/TXREADOUTSTATE_FFd3 AND chip_comp/Datasig(6)) OR (NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/Datasig(6)) OR (chip_comp/TXREADOUTSTATE_FFd2 AND chip_comp/Datasig(6))); DATA(6) <= DATA_I(6) when DATA_OE(6) = '1' else 'Z'; DATA_OE(6) <= NOT DATA_TSsig; DATA_I(7) <= ((EXP29_.EXP) OR (chip_comp/TXREADOUTSTATE_FFd3 AND chip_comp/Datasig(7)) OR (NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/Datasig(7)) OR (chip_comp/TXREADOUTSTATE_FFd2 AND chip_comp/Datasig(7))); DATA(7) <= DATA_I(7) when DATA_OE(7) = '1' else 'Z'; DATA_OE(7) <= NOT DATA_TSsig; DATA_I(8) <= ((EXP28_.EXP) OR (chip_comp/TXREADOUTSTATE_FFd3 AND chip_comp/Datasig(8))); DATA(8) <= DATA_I(8) when DATA_OE(8) = '1' else 'Z'; DATA_OE(8) <= NOT DATA_TSsig; DATA_I(9) <= ((EXP23_.EXP) OR (chip_comp/TXREADOUTSTATE_FFd3 AND chip_comp/Datasig(9)) OR (NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/Datasig(9)) OR (chip_comp/TXREADOUTSTATE_FFd2 AND chip_comp/Datasig(9))); DATA(9) <= DATA_I(9) when DATA_OE(9) = '1' else 'Z'; DATA_OE(9) <= NOT DATA_TSsig; DATA_I(10) <= ((chip_comp/Datasig(10).EXP) OR (chip_comp/TXREADOUTSTATE_FFd3 AND chip_comp/Datasig(10)) OR (NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/Datasig(10)) OR (chip_comp/TXREADOUTSTATE_FFd2 AND chip_comp/Datasig(10)) OR (chip_comp/TXREADOUTSTATE_FFd1 AND chip_comp/Datasig(10))); DATA(10) <= DATA_I(10) when DATA_OE(10) = '1' else 'Z'; DATA_OE(10) <= NOT DATA_TSsig; DATA_I(11) <= ((chip_comp/Datasig(12).EXP) OR (chip_comp/TXREADOUTSTATE_FFd3 AND chip_comp/Datasig(11)) OR (NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/Datasig(11)) OR (chip_comp/TXREADOUTSTATE_FFd2 AND chip_comp/Datasig(11)) OR (chip_comp/TXREADOUTSTATE_FFd1 AND chip_comp/Datasig(11))); DATA(11) <= DATA_I(11) when DATA_OE(11) = '1' else 'Z'; DATA_OE(11) <= NOT DATA_TSsig; DATA_I(12) <= ((Datasig(13).EXP) OR (chip_comp/TXREADOUTSTATE_FFd3 AND chip_comp/Datasig(12)) OR (NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/Datasig(12))); DATA(12) <= DATA_I(12) when DATA_OE(12) = '1' else 'Z'; DATA_OE(12) <= NOT DATA_TSsig; DATA_I(13) <= ((chip_comp/ACLKCounter(0).EXP) OR (chip_comp/TXREADOUTSTATE_FFd3 AND chip_comp/Datasig(13))); DATA(13) <= DATA_I(13) when DATA_OE(13) = '1' else 'Z'; DATA_OE(13) <= NOT DATA_TSsig; DATA_I(14) <= ((chip_comp/Datasig(14).EXP) OR (chip_comp/TXREADOUTSTATE_FFd3 AND chip_comp/Datasig(14)) OR (NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/Datasig(14)) OR (chip_comp/TXREADOUTSTATE_FFd2 AND chip_comp/Datasig(14)) OR (chip_comp/TXREADOUTSTATE_FFd1 AND chip_comp/Datasig(14))); DATA(14) <= DATA_I(14) when DATA_OE(14) = '1' else 'Z'; DATA_OE(14) <= NOT DATA_TSsig; DATA_I(15) <= ((DATA_TSsig.EXP) OR (chip_comp/TXREADOUTSTATE_FFd3 AND chip_comp/Datasig(15)) OR (NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/Datasig(15))); DATA(15) <= DATA_I(15) when DATA_OE(15) = '1' else 'Z'; DATA_OE(15) <= NOT DATA_TSsig; FDCPE_DATA_TSsig: FDCPE port map (DATA_TSsig,DATA_TSsig_D,CLK_40MHZ,'0',POR); DATA_TSsig_D <= ((EXP20_.EXP) OR (NOT chip_comp/TXREADOUTSTATE_FFd2 AND NOT chip_comp/TXREADOUTSTATE_FFd1) OR (NOT chip_comp/TXREADOUTSTATE_FFd3 AND chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd1)); FDCPE_DR0: FDCPE port map (DR0,chip_comp/CommandReceived(0),CLK_40MHZ,POR,'0',DR0_CE); DR0_CE <= (NOT chip_comp/CommandReceived(10) AND NOT chip_comp/CommandReceived(13) AND NOT chip_comp/CommandReceived(14) AND chip_comp/CommandReceived(9) AND chip_comp/CommandReceived(11) AND NOT chip_comp/CommandReceived(12) AND NOT chip_comp/CommandReceived(15) AND NOT chip_comp/CommandReceived(8) AND chip_comp/TXMAINSTATE_FFd1); FDCPE_DR1: FDCPE port map (DR1,chip_comp/CommandReceived(1),CLK_40MHZ,POR,'0',DR1_CE); DR1_CE <= (NOT chip_comp/CommandReceived(10) AND NOT chip_comp/CommandReceived(13) AND NOT chip_comp/CommandReceived(14) AND chip_comp/CommandReceived(9) AND chip_comp/CommandReceived(11) AND NOT chip_comp/CommandReceived(12) AND NOT chip_comp/CommandReceived(15) AND NOT chip_comp/CommandReceived(8) AND chip_comp/TXMAINSTATE_FFd1); FDCPE_D_OEn_B0: FDCPE port map (D_OEn_B(0),D_OEn_B_D(0),CLK_40MHZ,'0',POR); D_OEn_B_D(0) <= (NOT chip_comp/TXREADOUTSTATE_FFd3 AND NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND NOT chip_comp/TXREADOUTSTATE_FFd1); FDCPE_D_OEn_B1: FDCPE port map (D_OEn_B(1),D_OEn_B_D(1),CLK_40MHZ,'0',POR); D_OEn_B_D(1) <= (chip_comp/TXREADOUTSTATE_FFd3 AND chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND NOT chip_comp/TXREADOUTSTATE_FFd1); FDCPE_D_OEn_B2: FDCPE port map (D_OEn_B(2),EXP37_.EXP,CLK_40MHZ,'0',POR); FDCPE_D_OEn_B3: FDCPE port map (D_OEn_B(3),D_OEn_B_D(3),CLK_40MHZ,'0',POR); D_OEn_B_D(3) <= (chip_comp/TXREADOUTSTATE_FFd3 AND NOT chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND chip_comp/TXREADOUTSTATE_FFd1); FDCPE_ENABLEn_B0: FDCPE port map (ENABLEn_B(0),ENABLEn_B_D(0),CLK_40MHZ,'0',POR); ENABLEn_B_D(0) <= (chip_comp/RunningFlag AND chip_comp/ENABLEn_BReg(0)); FDCPE_ENABLEn_B1: FDCPE port map (ENABLEn_B(1),ENABLEn_B_D(1),CLK_40MHZ,'0',POR); ENABLEn_B_D(1) <= (chip_comp/RunningFlag AND chip_comp/ENABLEn_BReg(1)); FDCPE_ENABLEn_B2: FDCPE port map (ENABLEn_B(2),ENABLEn_B_D(2),CLK_40MHZ,'0',POR); ENABLEn_B_D(2) <= (chip_comp/RunningFlag AND chip_comp/ENABLEn_BReg(2)); FDCPE_ENABLEn_B3: FDCPE port map (ENABLEn_B(3),ENABLEn_B_D(3),CLK_40MHZ,'0',POR); ENABLEn_B_D(3) <= (chip_comp/RunningFlag AND chip_comp/ENABLEn_BReg(3)); FDCPE_PT0: FDCPE port map (PT0,chip_comp/CommandReceived(0),CLK_40MHZ,POR,'0',PT0_CE); PT0_CE <= (NOT chip_comp/CommandReceived(10) AND NOT chip_comp/CommandReceived(13) AND NOT chip_comp/CommandReceived(14) AND chip_comp/CommandReceived(9) AND chip_comp/CommandReceived(11) AND NOT chip_comp/CommandReceived(12) AND NOT chip_comp/CommandReceived(15) AND chip_comp/CommandReceived(8) AND chip_comp/TXMAINSTATE_FFd1); FDCPE_PT1: FDCPE port map (PT1,chip_comp/CommandReceived(1),CLK_40MHZ,POR,'0',PT1_CE); PT1_CE <= (NOT chip_comp/CommandReceived(10) AND NOT chip_comp/CommandReceived(13) AND NOT chip_comp/CommandReceived(14) AND chip_comp/CommandReceived(9) AND chip_comp/CommandReceived(11) AND NOT chip_comp/CommandReceived(12) AND NOT chip_comp/CommandReceived(15) AND chip_comp/CommandReceived(8) AND chip_comp/TXMAINSTATE_FFd1); RCLK3 <= CLK_40MHZ; RCLK4_B(0) <= NOT ((NOT CLK_40MHZ AND chip_comp/TXREADOUTSTATE_FFd3 AND chip_comp/TXREADOUTSTATE_FFd1)); RCLK4_B(1) <= NOT ((NOT CLK_40MHZ AND chip_comp/TXREADOUTSTATE_FFd3 AND chip_comp/TXREADOUTSTATE_FFd1)); RCLK4_B(2) <= NOT ((NOT CLK_40MHZ AND chip_comp/TXREADOUTSTATE_FFd3 AND chip_comp/TXREADOUTSTATE_FFd1)); RCLK4_B(3) <= NOT ((NOT CLK_40MHZ AND chip_comp/TXREADOUTSTATE_FFd3 AND chip_comp/TXREADOUTSTATE_FFd1)); RESETn <= NOT POR; FTCPE_RST4n_B0: FTCPE port map (RST4n_B(0),RST4n_B_T(0),CLK_40MHZ,POR,'0'); RST4n_B_T(0) <= (NOT RST4n_B(0) AND NOT chip_comp/TXREADOUTSTATE_FFd3 AND NOT chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND NOT chip_comp/TXREADOUTSTATE_FFd1); FTCPE_RST4n_B1: FTCPE port map (RST4n_B(1),RST4n_B_T(1),CLK_40MHZ,POR,'0'); RST4n_B_T(1) <= (NOT RST4n_B(1) AND NOT chip_comp/TXREADOUTSTATE_FFd3 AND NOT chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND NOT chip_comp/TXREADOUTSTATE_FFd1); FTCPE_RST4n_B2: FTCPE port map (RST4n_B(2),RST4n_B_T(2),CLK_40MHZ,POR,'0'); RST4n_B_T(2) <= (NOT RST4n_B(2) AND NOT chip_comp/TXREADOUTSTATE_FFd3 AND NOT chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND NOT chip_comp/TXREADOUTSTATE_FFd1); FTCPE_RST4n_B3: FTCPE port map (RST4n_B(3),RST4n_B_T(3),CLK_40MHZ,POR,'0'); RST4n_B_T(3) <= (NOT RST4n_B(3) AND NOT chip_comp/TXREADOUTSTATE_FFd3 AND NOT chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND NOT chip_comp/TXREADOUTSTATE_FFd1); FDCPE_RST_TIMERn: FDCPE port map (RST_TIMERn,RST_TIMERn_D,CLK_40MHZ,POR,'0'); RST_TIMERn_D <= ((NOT chip_comp/TimerRestCMD AND RST_TIMERn) OR (TCLK AND NOT chip_comp/TimerRestCMD AND NOT chip_comp/TCLKsig_1)); FDCPE_SYNCn: FDCPE port map (SYNCn,NOT chip_comp/TXMAINSTATE_FFd2,CLK_40MHZ,POR,'0'); SYSCLK <= CLK_40MHZ; FTCPE_TCLK: FTCPE port map (TCLK,'1',CLK_40MHZ,POR,'0',TCLK_CE); TCLK_CE <= (NOT chip_comp/TCLKCounter(0) AND NOT chip_comp/TCLKCounter(1) AND NOT chip_comp/TCLKCounter(2) AND NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND NOT chip_comp/TCLKCounter(5) AND NOT chip_comp/TCLKCounter(6) AND NOT chip_comp/TCLKCounter(7) AND NOT chip_comp/TCLKCounter(8) AND NOT chip_comp/TCLKCounter(9) AND NOT chip_comp/TCLKCounter(10)); FDCPE_TMODE: FDCPE port map (TMODE,chip_comp/CommandReceived(0),CLK_40MHZ,POR,'0',TMODE_CE); TMODE_CE <= (chip_comp/CommandReceived(10) AND NOT chip_comp/CommandReceived(13) AND NOT chip_comp/CommandReceived(14) AND NOT chip_comp/CommandReceived(9) AND chip_comp/CommandReceived(11) AND NOT chip_comp/CommandReceived(12) AND NOT chip_comp/CommandReceived(15) AND chip_comp/CommandReceived(8) AND chip_comp/TXMAINSTATE_FFd1); FTCPE_chip_comp/ACLKCounter0: FTCPE port map (chip_comp/ACLKCounter(0),'1',CLK_40MHZ,POR,'0'); FTCPE_chip_comp/ACLKCounter1: FTCPE port map (chip_comp/ACLKCounter(1),chip_comp/ACLKCounter(0),CLK_40MHZ,POR,'0'); FTCPE_chip_comp/ACLKCounter2: FTCPE port map (chip_comp/ACLKCounter(2),chip_comp/ACLKCounter_T(2),CLK_40MHZ,POR,'0'); chip_comp/ACLKCounter_T(2) <= (NOT chip_comp/ACLKCounter(0) AND NOT chip_comp/ACLKCounter(1)); FTCPE_chip_comp/ACLKCounter3: FTCPE port map (chip_comp/ACLKCounter(3),chip_comp/ACLKCounter_T(3),CLK_40MHZ,POR,'0'); chip_comp/ACLKCounter_T(3) <= ((chip_comp/ACLKCounter(0)) OR (chip_comp/ACLKCounter(1)) OR (chip_comp/ACLKCounter(2)) OR (NOT chip_comp/SamplingClock(1) AND NOT chip_comp/SamplingClock(0) AND NOT chip_comp/ACLKCounter(3) AND NOT chip_comp/ACLKCounter(4) AND NOT chip_comp/ACLKCounter(5) AND NOT chip_comp/ACLKCounter(6) AND NOT chip_comp/ACLKCounter(7) AND NOT chip_comp/ACLKCounter(8))); FTCPE_chip_comp/ACLKCounter4: FTCPE port map (chip_comp/ACLKCounter(4),chip_comp/ACLKCounter_T(4),CLK_40MHZ,POR,'0'); chip_comp/ACLKCounter_T(4) <= ((chip_comp/ACLKCounter(0)) OR (chip_comp/ACLKCounter(1)) OR (chip_comp/ACLKCounter(2)) OR (chip_comp/ACLKCounter(3)) OR (NOT chip_comp/SamplingClock(1) AND NOT chip_comp/ACLKCounter(4) AND NOT chip_comp/ACLKCounter(5) AND NOT chip_comp/ACLKCounter(6) AND NOT chip_comp/ACLKCounter(7) AND NOT chip_comp/ACLKCounter(8))); FTCPE_chip_comp/ACLKCounter5: FTCPE port map (chip_comp/ACLKCounter(5),chip_comp/ACLKCounter_T(5),CLK_40MHZ,POR,'0'); chip_comp/ACLKCounter_T(5) <= ((EXP18_.EXP) OR (NOT chip_comp/ACLKCounter(0) AND NOT chip_comp/ACLKCounter(1) AND NOT chip_comp/ACLKCounter(2) AND NOT chip_comp/ACLKCounter(3) AND NOT chip_comp/ACLKCounter(4) AND chip_comp/ACLKCounter(5)) OR (NOT chip_comp/ACLKCounter(0) AND NOT chip_comp/ACLKCounter(1) AND NOT chip_comp/ACLKCounter(2) AND NOT chip_comp/ACLKCounter(3) AND NOT chip_comp/ACLKCounter(4) AND chip_comp/ACLKCounter(6)) OR (NOT chip_comp/ACLKCounter(0) AND NOT chip_comp/ACLKCounter(1) AND NOT chip_comp/ACLKCounter(2) AND NOT chip_comp/ACLKCounter(3) AND NOT chip_comp/ACLKCounter(4) AND chip_comp/ACLKCounter(7)) OR (NOT chip_comp/ACLKCounter(0) AND NOT chip_comp/ACLKCounter(1) AND NOT chip_comp/ACLKCounter(2) AND NOT chip_comp/ACLKCounter(3) AND NOT chip_comp/ACLKCounter(4) AND chip_comp/ACLKCounter(8)) OR (chip_comp/SamplingClock(1) AND chip_comp/SamplingClock(0) AND NOT chip_comp/ACLKCounter(0) AND NOT chip_comp/ACLKCounter(1) AND NOT chip_comp/ACLKCounter(2) AND NOT chip_comp/ACLKCounter(3) AND NOT chip_comp/ACLKCounter(4))); FTCPE_chip_comp/ACLKCounter6: FTCPE port map (chip_comp/ACLKCounter(6),chip_comp/ACLKCounter_T(6),CLK_40MHZ,POR,'0'); chip_comp/ACLKCounter_T(6) <= ((NOT chip_comp/ACLKCounter(0) AND NOT chip_comp/ACLKCounter(1) AND NOT chip_comp/ACLKCounter(2) AND NOT chip_comp/ACLKCounter(3) AND NOT chip_comp/ACLKCounter(4) AND NOT chip_comp/ACLKCounter(5) AND chip_comp/ACLKCounter(6)) OR (NOT chip_comp/ACLKCounter(0) AND NOT chip_comp/ACLKCounter(1) AND NOT chip_comp/ACLKCounter(2) AND NOT chip_comp/ACLKCounter(3) AND NOT chip_comp/ACLKCounter(4) AND NOT chip_comp/ACLKCounter(5) AND chip_comp/ACLKCounter(7)) OR (NOT chip_comp/ACLKCounter(0) AND NOT chip_comp/ACLKCounter(1) AND NOT chip_comp/ACLKCounter(2) AND NOT chip_comp/ACLKCounter(3) AND NOT chip_comp/ACLKCounter(4) AND NOT chip_comp/ACLKCounter(5) AND chip_comp/ACLKCounter(8)) OR (NOT chip_comp/SamplingClock(1) AND chip_comp/SamplingClock(0) AND NOT chip_comp/ACLKCounter(0) AND NOT chip_comp/ACLKCounter(1) AND NOT chip_comp/ACLKCounter(2) AND NOT chip_comp/ACLKCounter(3) AND NOT chip_comp/ACLKCounter(4) AND NOT chip_comp/ACLKCounter(5))); FTCPE_chip_comp/ACLKCounter7: FTCPE port map (chip_comp/ACLKCounter(7),chip_comp/ACLKCounter_T(7),CLK_40MHZ,POR,'0'); chip_comp/ACLKCounter_T(7) <= ((NOT chip_comp/ACLKCounter(0) AND NOT chip_comp/ACLKCounter(1) AND NOT chip_comp/ACLKCounter(2) AND NOT chip_comp/ACLKCounter(3) AND NOT chip_comp/ACLKCounter(4) AND NOT chip_comp/ACLKCounter(5) AND NOT chip_comp/ACLKCounter(6) AND chip_comp/ACLKCounter(7)) OR (NOT chip_comp/ACLKCounter(0) AND NOT chip_comp/ACLKCounter(1) AND NOT chip_comp/ACLKCounter(2) AND NOT chip_comp/ACLKCounter(3) AND NOT chip_comp/ACLKCounter(4) AND NOT chip_comp/ACLKCounter(5) AND NOT chip_comp/ACLKCounter(6) AND chip_comp/ACLKCounter(8)) OR (chip_comp/SamplingClock(1) AND NOT chip_comp/SamplingClock(0) AND NOT chip_comp/ACLKCounter(0) AND NOT chip_comp/ACLKCounter(1) AND NOT chip_comp/ACLKCounter(2) AND NOT chip_comp/ACLKCounter(3) AND NOT chip_comp/ACLKCounter(4) AND NOT chip_comp/ACLKCounter(5) AND NOT chip_comp/ACLKCounter(6))); FTCPE_chip_comp/ACLKCounter8: FTCPE port map (chip_comp/ACLKCounter(8),chip_comp/ACLKCounter_T(8),CLK_40MHZ,POR,'0'); chip_comp/ACLKCounter_T(8) <= ((NOT chip_comp/ACLKCounter(0) AND NOT chip_comp/ACLKCounter(1) AND NOT chip_comp/ACLKCounter(2) AND NOT chip_comp/ACLKCounter(3) AND NOT chip_comp/ACLKCounter(4) AND NOT chip_comp/ACLKCounter(5) AND NOT chip_comp/ACLKCounter(6) AND NOT chip_comp/ACLKCounter(7) AND chip_comp/ACLKCounter(8)) OR (chip_comp/SamplingClock(1) AND chip_comp/SamplingClock(0) AND NOT chip_comp/ACLKCounter(0) AND NOT chip_comp/ACLKCounter(1) AND NOT chip_comp/ACLKCounter(2) AND NOT chip_comp/ACLKCounter(3) AND NOT chip_comp/ACLKCounter(4) AND NOT chip_comp/ACLKCounter(5) AND NOT chip_comp/ACLKCounter(6) AND NOT chip_comp/ACLKCounter(7))); FDCPE_chip_comp/ACLKsig_1: FDCPE port map (chip_comp/ACLKsig_1,ACLK,CLK_40MHZ,POR,'0'); FDCPE_chip_comp/ACQENnB0Reg0: FDCPE port map (chip_comp/ACQENnB0Reg(0),chip_comp/CommandReceived(0),CLK_40MHZ,POR,'0',chip_comp/ACQENnB0Reg_CE(0)); chip_comp/ACQENnB0Reg_CE(0) <= (NOT chip_comp/RunningFlag AND NOT chip_comp/CommandReceived(10) AND NOT chip_comp/CommandReceived(13) AND NOT chip_comp/CommandReceived(14) AND NOT chip_comp/CommandReceived(9) AND NOT chip_comp/CommandReceived(11) AND NOT chip_comp/CommandReceived(12) AND NOT chip_comp/CommandReceived(15) AND chip_comp/CommandReceived(8) AND NOT chip_comp/CommandReceived(4) AND NOT chip_comp/CommandReceived(5) AND NOT chip_comp/CommandReceived(6) AND NOT chip_comp/CommandReceived(7) AND chip_comp/TXMAINSTATE_FFd1); FDCPE_chip_comp/ACQENnB0Reg1: FDCPE port map (chip_comp/ACQENnB0Reg(1),chip_comp/CommandReceived(1),CLK_40MHZ,POR,'0',chip_comp/ACQENnB0Reg_CE(1)); chip_comp/ACQENnB0Reg_CE(1) <= (NOT chip_comp/RunningFlag AND NOT chip_comp/CommandReceived(10) AND NOT chip_comp/CommandReceived(13) AND NOT chip_comp/CommandReceived(14) AND NOT chip_comp/CommandReceived(9) AND NOT chip_comp/CommandReceived(11) AND NOT chip_comp/CommandReceived(12) AND NOT chip_comp/CommandReceived(15) AND chip_comp/CommandReceived(8) AND NOT chip_comp/CommandReceived(4) AND NOT chip_comp/CommandReceived(5) AND NOT chip_comp/CommandReceived(6) AND NOT chip_comp/CommandReceived(7) AND chip_comp/TXMAINSTATE_FFd1); FDCPE_chip_comp/ACQENnB0Reg2: FDCPE port map (chip_comp/ACQENnB0Reg(2),chip_comp/CommandReceived(2),CLK_40MHZ,POR,'0',chip_comp/ACQENnB0Reg_CE(2)); chip_comp/ACQENnB0Reg_CE(2) <= (NOT chip_comp/RunningFlag AND NOT chip_comp/CommandReceived(10) AND NOT chip_comp/CommandReceived(13) AND NOT chip_comp/CommandReceived(14) AND NOT chip_comp/CommandReceived(9) AND NOT chip_comp/CommandReceived(11) AND NOT chip_comp/CommandReceived(12) AND NOT chip_comp/CommandReceived(15) AND chip_comp/CommandReceived(8) AND NOT chip_comp/CommandReceived(4) AND NOT chip_comp/CommandReceived(5) AND NOT chip_comp/CommandReceived(6) AND NOT chip_comp/CommandReceived(7) AND chip_comp/TXMAINSTATE_FFd1); FDCPE_chip_comp/ACQENnB0Reg3: FDCPE port map (chip_comp/ACQENnB0Reg(3),chip_comp/CommandReceived(3),CLK_40MHZ,POR,'0',chip_comp/ACQENnB0Reg_CE(3)); chip_comp/ACQENnB0Reg_CE(3) <= (NOT chip_comp/RunningFlag AND NOT chip_comp/CommandReceived(10) AND NOT chip_comp/CommandReceived(13) AND NOT chip_comp/CommandReceived(14) AND NOT chip_comp/CommandReceived(9) AND NOT chip_comp/CommandReceived(11) AND NOT chip_comp/CommandReceived(12) AND NOT chip_comp/CommandReceived(15) AND chip_comp/CommandReceived(8) AND NOT chip_comp/CommandReceived(4) AND NOT chip_comp/CommandReceived(5) AND NOT chip_comp/CommandReceived(6) AND NOT chip_comp/CommandReceived(7) AND chip_comp/TXMAINSTATE_FFd1); FDCPE_chip_comp/ACQENnB1Reg0: FDCPE port map (chip_comp/ACQENnB1Reg(0),chip_comp/CommandReceived(0),CLK_40MHZ,POR,'0',chip_comp/ACQENnB1Reg_CE(0)); chip_comp/ACQENnB1Reg_CE(0) <= (NOT chip_comp/RunningFlag AND NOT chip_comp/CommandReceived(10) AND NOT chip_comp/CommandReceived(13) AND NOT chip_comp/CommandReceived(14) AND NOT chip_comp/CommandReceived(9) AND NOT chip_comp/CommandReceived(11) AND NOT chip_comp/CommandReceived(12) AND NOT chip_comp/CommandReceived(15) AND chip_comp/CommandReceived(8) AND chip_comp/CommandReceived(4) AND NOT chip_comp/CommandReceived(5) AND NOT chip_comp/CommandReceived(6) AND NOT chip_comp/CommandReceived(7) AND chip_comp/TXMAINSTATE_FFd1); FDCPE_chip_comp/ACQENnB1Reg1: FDCPE port map (chip_comp/ACQENnB1Reg(1),chip_comp/CommandReceived(1),CLK_40MHZ,POR,'0',chip_comp/ACQENnB1Reg_CE(1)); chip_comp/ACQENnB1Reg_CE(1) <= (NOT chip_comp/RunningFlag AND NOT chip_comp/CommandReceived(10) AND NOT chip_comp/CommandReceived(13) AND NOT chip_comp/CommandReceived(14) AND NOT chip_comp/CommandReceived(9) AND NOT chip_comp/CommandReceived(11) AND NOT chip_comp/CommandReceived(12) AND NOT chip_comp/CommandReceived(15) AND chip_comp/CommandReceived(8) AND chip_comp/CommandReceived(4) AND NOT chip_comp/CommandReceived(5) AND NOT chip_comp/CommandReceived(6) AND NOT chip_comp/CommandReceived(7) AND chip_comp/TXMAINSTATE_FFd1); FDCPE_chip_comp/ACQENnB1Reg2: FDCPE port map (chip_comp/ACQENnB1Reg(2),chip_comp/CommandReceived(2),CLK_40MHZ,POR,'0',chip_comp/ACQENnB1Reg_CE(2)); chip_comp/ACQENnB1Reg_CE(2) <= (NOT chip_comp/RunningFlag AND NOT chip_comp/CommandReceived(10) AND NOT chip_comp/CommandReceived(13) AND NOT chip_comp/CommandReceived(14) AND NOT chip_comp/CommandReceived(9) AND NOT chip_comp/CommandReceived(11) AND NOT chip_comp/CommandReceived(12) AND NOT chip_comp/CommandReceived(15) AND chip_comp/CommandReceived(8) AND chip_comp/CommandReceived(4) AND NOT chip_comp/CommandReceived(5) AND NOT chip_comp/CommandReceived(6) AND NOT chip_comp/CommandReceived(7) AND chip_comp/TXMAINSTATE_FFd1); FDCPE_chip_comp/ACQENnB1Reg3: FDCPE port map (chip_comp/ACQENnB1Reg(3),chip_comp/CommandReceived(3),CLK_40MHZ,POR,'0',chip_comp/ACQENnB1Reg_CE(3)); chip_comp/ACQENnB1Reg_CE(3) <= (NOT chip_comp/RunningFlag AND NOT chip_comp/CommandReceived(10) AND NOT chip_comp/CommandReceived(13) AND NOT chip_comp/CommandReceived(14) AND NOT chip_comp/CommandReceived(9) AND NOT chip_comp/CommandReceived(11) AND NOT chip_comp/CommandReceived(12) AND NOT chip_comp/CommandReceived(15) AND chip_comp/CommandReceived(8) AND chip_comp/CommandReceived(4) AND NOT chip_comp/CommandReceived(5) AND NOT chip_comp/CommandReceived(6) AND NOT chip_comp/CommandReceived(7) AND chip_comp/TXMAINSTATE_FFd1); FDCPE_chip_comp/ACQENnB2Reg0: FDCPE port map (chip_comp/ACQENnB2Reg(0),chip_comp/CommandReceived(0),CLK_40MHZ,POR,'0',chip_comp/ACQENnB2Reg_CE(0)); chip_comp/ACQENnB2Reg_CE(0) <= (NOT chip_comp/RunningFlag AND NOT chip_comp/CommandReceived(10) AND NOT chip_comp/CommandReceived(13) AND NOT chip_comp/CommandReceived(14) AND NOT chip_comp/CommandReceived(9) AND NOT chip_comp/CommandReceived(11) AND NOT chip_comp/CommandReceived(12) AND NOT chip_comp/CommandReceived(15) AND chip_comp/CommandReceived(8) AND NOT chip_comp/CommandReceived(4) AND chip_comp/CommandReceived(5) AND NOT chip_comp/CommandReceived(6) AND NOT chip_comp/CommandReceived(7) AND chip_comp/TXMAINSTATE_FFd1); FDCPE_chip_comp/ACQENnB2Reg1: FDCPE port map (chip_comp/ACQENnB2Reg(1),chip_comp/CommandReceived(1),CLK_40MHZ,POR,'0',chip_comp/ACQENnB2Reg_CE(1)); chip_comp/ACQENnB2Reg_CE(1) <= (NOT chip_comp/RunningFlag AND NOT chip_comp/CommandReceived(10) AND NOT chip_comp/CommandReceived(13) AND NOT chip_comp/CommandReceived(14) AND NOT chip_comp/CommandReceived(9) AND NOT chip_comp/CommandReceived(11) AND NOT chip_comp/CommandReceived(12) AND NOT chip_comp/CommandReceived(15) AND chip_comp/CommandReceived(8) AND NOT chip_comp/CommandReceived(4) AND chip_comp/CommandReceived(5) AND NOT chip_comp/CommandReceived(6) AND NOT chip_comp/CommandReceived(7) AND chip_comp/TXMAINSTATE_FFd1); FDCPE_chip_comp/ACQENnB2Reg2: FDCPE port map (chip_comp/ACQENnB2Reg(2),chip_comp/CommandReceived(2),CLK_40MHZ,POR,'0',chip_comp/ACQENnB2Reg_CE(2)); chip_comp/ACQENnB2Reg_CE(2) <= (NOT chip_comp/RunningFlag AND NOT chip_comp/CommandReceived(10) AND NOT chip_comp/CommandReceived(13) AND NOT chip_comp/CommandReceived(14) AND NOT chip_comp/CommandReceived(9) AND NOT chip_comp/CommandReceived(11) AND NOT chip_comp/CommandReceived(12) AND NOT chip_comp/CommandReceived(15) AND chip_comp/CommandReceived(8) AND NOT chip_comp/CommandReceived(4) AND chip_comp/CommandReceived(5) AND NOT chip_comp/CommandReceived(6) AND NOT chip_comp/CommandReceived(7) AND chip_comp/TXMAINSTATE_FFd1); FDCPE_chip_comp/ACQENnB2Reg3: FDCPE port map (chip_comp/ACQENnB2Reg(3),chip_comp/CommandReceived(3),CLK_40MHZ,POR,'0',chip_comp/ACQENnB2Reg_CE(3)); chip_comp/ACQENnB2Reg_CE(3) <= (NOT chip_comp/RunningFlag AND NOT chip_comp/CommandReceived(10) AND NOT chip_comp/CommandReceived(13) AND NOT chip_comp/CommandReceived(14) AND NOT chip_comp/CommandReceived(9) AND NOT chip_comp/CommandReceived(11) AND NOT chip_comp/CommandReceived(12) AND NOT chip_comp/CommandReceived(15) AND chip_comp/CommandReceived(8) AND NOT chip_comp/CommandReceived(4) AND chip_comp/CommandReceived(5) AND NOT chip_comp/CommandReceived(6) AND NOT chip_comp/CommandReceived(7) AND chip_comp/TXMAINSTATE_FFd1); FDCPE_chip_comp/ACQENnB3Reg0: FDCPE port map (chip_comp/ACQENnB3Reg(0),chip_comp/CommandReceived(0),CLK_40MHZ,POR,'0',chip_comp/ACQENnB3Reg_CE(0)); chip_comp/ACQENnB3Reg_CE(0) <= (NOT chip_comp/RunningFlag AND NOT chip_comp/CommandReceived(10) AND NOT chip_comp/CommandReceived(13) AND NOT chip_comp/CommandReceived(14) AND NOT chip_comp/CommandReceived(9) AND NOT chip_comp/CommandReceived(11) AND NOT chip_comp/CommandReceived(12) AND NOT chip_comp/CommandReceived(15) AND chip_comp/CommandReceived(8) AND chip_comp/CommandReceived(4) AND chip_comp/CommandReceived(5) AND NOT chip_comp/CommandReceived(6) AND NOT chip_comp/CommandReceived(7) AND chip_comp/TXMAINSTATE_FFd1); FDCPE_chip_comp/ACQENnB3Reg1: FDCPE port map (chip_comp/ACQENnB3Reg(1),chip_comp/CommandReceived(1),CLK_40MHZ,POR,'0',chip_comp/ACQENnB3Reg_CE(1)); chip_comp/ACQENnB3Reg_CE(1) <= (NOT chip_comp/RunningFlag AND NOT chip_comp/CommandReceived(10) AND NOT chip_comp/CommandReceived(13) AND NOT chip_comp/CommandReceived(14) AND NOT chip_comp/CommandReceived(9) AND NOT chip_comp/CommandReceived(11) AND NOT chip_comp/CommandReceived(12) AND NOT chip_comp/CommandReceived(15) AND chip_comp/CommandReceived(8) AND chip_comp/CommandReceived(4) AND chip_comp/CommandReceived(5) AND NOT chip_comp/CommandReceived(6) AND NOT chip_comp/CommandReceived(7) AND chip_comp/TXMAINSTATE_FFd1); FDCPE_chip_comp/ACQENnB3Reg2: FDCPE port map (chip_comp/ACQENnB3Reg(2),chip_comp/CommandReceived(2),CLK_40MHZ,POR,'0',chip_comp/ACQENnB3Reg_CE(2)); chip_comp/ACQENnB3Reg_CE(2) <= (NOT chip_comp/RunningFlag AND NOT chip_comp/CommandReceived(10) AND NOT chip_comp/CommandReceived(13) AND NOT chip_comp/CommandReceived(14) AND NOT chip_comp/CommandReceived(9) AND NOT chip_comp/CommandReceived(11) AND NOT chip_comp/CommandReceived(12) AND NOT chip_comp/CommandReceived(15) AND chip_comp/CommandReceived(8) AND chip_comp/CommandReceived(4) AND chip_comp/CommandReceived(5) AND NOT chip_comp/CommandReceived(6) AND NOT chip_comp/CommandReceived(7) AND chip_comp/TXMAINSTATE_FFd1); FDCPE_chip_comp/ACQENnB3Reg3: FDCPE port map (chip_comp/ACQENnB3Reg(3),chip_comp/CommandReceived(3),CLK_40MHZ,POR,'0',chip_comp/ACQENnB3Reg_CE(3)); chip_comp/ACQENnB3Reg_CE(3) <= (NOT chip_comp/RunningFlag AND NOT chip_comp/CommandReceived(10) AND NOT chip_comp/CommandReceived(13) AND NOT chip_comp/CommandReceived(14) AND NOT chip_comp/CommandReceived(9) AND NOT chip_comp/CommandReceived(11) AND NOT chip_comp/CommandReceived(12) AND NOT chip_comp/CommandReceived(15) AND chip_comp/CommandReceived(8) AND chip_comp/CommandReceived(4) AND chip_comp/CommandReceived(5) AND NOT chip_comp/CommandReceived(6) AND NOT chip_comp/CommandReceived(7) AND chip_comp/TXMAINSTATE_FFd1); FTCPE_chip_comp/ADCRestCMD: FTCPE port map (chip_comp/ADCRestCMD,chip_comp/ADCRestCMD_T,CLK_40MHZ,'0',POR); chip_comp/ADCRestCMD_T <= (NOT chip_comp/TXMAINSTATE_FFd1 AND NOT chip_comp/TXMAINSTATE_FFd2 AND chip_comp/ADCRestCMD); FDCPE_chip_comp/CommandAvailable: FDCPE port map (chip_comp/CommandAvailable,chip_comp/CommandAvailable_D,CLK_40MHZ,POR,'0'); chip_comp/CommandAvailable_D <= (chip_comp/ReceiveCommandComp/sr(1) AND chip_comp/ReceiveCommandComp/sr(2) AND NOT chip_comp/ReceiveCommandComp/sr(3) AND chip_comp/ReceiveCommandComp/sr(4)); FDCPE_chip_comp/CommandReceived0: FDCPE port map (chip_comp/CommandReceived(0),chip_comp/ReceiveCommandComp/sr(5),CLK_40MHZ,POR,'0',chip_comp/CommandReceived_CE(0)); chip_comp/CommandReceived_CE(0) <= (chip_comp/ReceiveCommandComp/sr(1) AND chip_comp/ReceiveCommandComp/sr(2) AND NOT chip_comp/ReceiveCommandComp/sr(3) AND chip_comp/ReceiveCommandComp/sr(4)); FDCPE_chip_comp/CommandReceived1: FDCPE port map (chip_comp/CommandReceived(1),chip_comp/ReceiveCommandComp/sr(6),CLK_40MHZ,POR,'0',chip_comp/CommandReceived_CE(1)); chip_comp/CommandReceived_CE(1) <= (chip_comp/ReceiveCommandComp/sr(1) AND chip_comp/ReceiveCommandComp/sr(2) AND NOT chip_comp/ReceiveCommandComp/sr(3) AND chip_comp/ReceiveCommandComp/sr(4)); FDCPE_chip_comp/CommandReceived2: FDCPE port map (chip_comp/CommandReceived(2),chip_comp/ReceiveCommandComp/sr(7),CLK_40MHZ,POR,'0',chip_comp/CommandReceived_CE(2)); chip_comp/CommandReceived_CE(2) <= (chip_comp/ReceiveCommandComp/sr(1) AND chip_comp/ReceiveCommandComp/sr(2) AND NOT chip_comp/ReceiveCommandComp/sr(3) AND chip_comp/ReceiveCommandComp/sr(4)); FDCPE_chip_comp/CommandReceived3: FDCPE port map (chip_comp/CommandReceived(3),chip_comp/ReceiveCommandComp/sr(8),CLK_40MHZ,POR,'0',chip_comp/CommandReceived_CE(3)); chip_comp/CommandReceived_CE(3) <= (chip_comp/ReceiveCommandComp/sr(1) AND chip_comp/ReceiveCommandComp/sr(2) AND NOT chip_comp/ReceiveCommandComp/sr(3) AND chip_comp/ReceiveCommandComp/sr(4)); FDCPE_chip_comp/CommandReceived4: FDCPE port map (chip_comp/CommandReceived(4),chip_comp/ReceiveCommandComp/sr(9),CLK_40MHZ,POR,'0',chip_comp/CommandReceived_CE(4)); chip_comp/CommandReceived_CE(4) <= (chip_comp/ReceiveCommandComp/sr(1) AND chip_comp/ReceiveCommandComp/sr(2) AND NOT chip_comp/ReceiveCommandComp/sr(3) AND chip_comp/ReceiveCommandComp/sr(4)); FDCPE_chip_comp/CommandReceived5: FDCPE port map (chip_comp/CommandReceived(5),chip_comp/ReceiveCommandComp/sr(10),CLK_40MHZ,POR,'0',chip_comp/CommandReceived_CE(5)); chip_comp/CommandReceived_CE(5) <= (chip_comp/ReceiveCommandComp/sr(1) AND chip_comp/ReceiveCommandComp/sr(2) AND NOT chip_comp/ReceiveCommandComp/sr(3) AND chip_comp/ReceiveCommandComp/sr(4)); FDCPE_chip_comp/CommandReceived6: FDCPE port map (chip_comp/CommandReceived(6),chip_comp/ReceiveCommandComp/sr(11),CLK_40MHZ,POR,'0',chip_comp/CommandReceived_CE(6)); chip_comp/CommandReceived_CE(6) <= (chip_comp/ReceiveCommandComp/sr(1) AND chip_comp/ReceiveCommandComp/sr(2) AND NOT chip_comp/ReceiveCommandComp/sr(3) AND chip_comp/ReceiveCommandComp/sr(4)); FDCPE_chip_comp/CommandReceived7: FDCPE port map (chip_comp/CommandReceived(7),chip_comp/ReceiveCommandComp/sr(12),CLK_40MHZ,POR,'0',chip_comp/CommandReceived_CE(7)); chip_comp/CommandReceived_CE(7) <= (chip_comp/ReceiveCommandComp/sr(1) AND chip_comp/ReceiveCommandComp/sr(2) AND NOT chip_comp/ReceiveCommandComp/sr(3) AND chip_comp/ReceiveCommandComp/sr(4)); FDCPE_chip_comp/CommandReceived8: FDCPE port map (chip_comp/CommandReceived(8),chip_comp/ReceiveCommandComp/sr(13),CLK_40MHZ,POR,'0',chip_comp/CommandReceived_CE(8)); chip_comp/CommandReceived_CE(8) <= (chip_comp/ReceiveCommandComp/sr(1) AND chip_comp/ReceiveCommandComp/sr(2) AND NOT chip_comp/ReceiveCommandComp/sr(3) AND chip_comp/ReceiveCommandComp/sr(4)); FDCPE_chip_comp/CommandReceived9: FDCPE port map (chip_comp/CommandReceived(9),chip_comp/ReceiveCommandComp/sr(14),CLK_40MHZ,POR,'0',chip_comp/CommandReceived_CE(9)); chip_comp/CommandReceived_CE(9) <= (chip_comp/ReceiveCommandComp/sr(1) AND chip_comp/ReceiveCommandComp/sr(2) AND NOT chip_comp/ReceiveCommandComp/sr(3) AND chip_comp/ReceiveCommandComp/sr(4)); FDCPE_chip_comp/CommandReceived10: FDCPE port map (chip_comp/CommandReceived(10),chip_comp/ReceiveCommandComp/sr(15),CLK_40MHZ,POR,'0',chip_comp/CommandReceived_CE(10)); chip_comp/CommandReceived_CE(10) <= (chip_comp/ReceiveCommandComp/sr(1) AND chip_comp/ReceiveCommandComp/sr(2) AND NOT chip_comp/ReceiveCommandComp/sr(3) AND chip_comp/ReceiveCommandComp/sr(4)); FDCPE_chip_comp/CommandReceived11: FDCPE port map (chip_comp/CommandReceived(11),chip_comp/ReceiveCommandComp/sr(16),CLK_40MHZ,POR,'0',chip_comp/CommandReceived_CE(11)); chip_comp/CommandReceived_CE(11) <= (chip_comp/ReceiveCommandComp/sr(1) AND chip_comp/ReceiveCommandComp/sr(2) AND NOT chip_comp/ReceiveCommandComp/sr(3) AND chip_comp/ReceiveCommandComp/sr(4)); FDCPE_chip_comp/CommandReceived12: FDCPE port map (chip_comp/CommandReceived(12),chip_comp/ReceiveCommandComp/sr(17),CLK_40MHZ,POR,'0',chip_comp/CommandReceived_CE(12)); chip_comp/CommandReceived_CE(12) <= (chip_comp/ReceiveCommandComp/sr(1) AND chip_comp/ReceiveCommandComp/sr(2) AND NOT chip_comp/ReceiveCommandComp/sr(3) AND chip_comp/ReceiveCommandComp/sr(4)); FDCPE_chip_comp/CommandReceived13: FDCPE port map (chip_comp/CommandReceived(13),chip_comp/ReceiveCommandComp/sr(18),CLK_40MHZ,POR,'0',chip_comp/CommandReceived_CE(13)); chip_comp/CommandReceived_CE(13) <= (chip_comp/ReceiveCommandComp/sr(1) AND chip_comp/ReceiveCommandComp/sr(2) AND NOT chip_comp/ReceiveCommandComp/sr(3) AND chip_comp/ReceiveCommandComp/sr(4)); FDCPE_chip_comp/CommandReceived14: FDCPE port map (chip_comp/CommandReceived(14),chip_comp/ReceiveCommandComp/sr(19),CLK_40MHZ,POR,'0',chip_comp/CommandReceived_CE(14)); chip_comp/CommandReceived_CE(14) <= (chip_comp/ReceiveCommandComp/sr(1) AND chip_comp/ReceiveCommandComp/sr(2) AND NOT chip_comp/ReceiveCommandComp/sr(3) AND chip_comp/ReceiveCommandComp/sr(4)); FDCPE_chip_comp/CommandReceived15: FDCPE port map (chip_comp/CommandReceived(15),chip_comp/ReceiveCommandComp/sr(20),CLK_40MHZ,POR,'0',chip_comp/CommandReceived_CE(15)); chip_comp/CommandReceived_CE(15) <= (chip_comp/ReceiveCommandComp/sr(1) AND chip_comp/ReceiveCommandComp/sr(2) AND NOT chip_comp/ReceiveCommandComp/sr(3) AND chip_comp/ReceiveCommandComp/sr(4)); FDCPE_chip_comp/DataPackageTXEn: FDCPE port map (chip_comp/DataPackageTXEn,chip_comp/CommandReceived(0),CLK_40MHZ,POR,'0',chip_comp/DataPackageTXEn_CE); chip_comp/DataPackageTXEn_CE <= (NOT chip_comp/CommandReceived(10) AND chip_comp/CommandReceived(13) AND chip_comp/CommandReceived(14) AND NOT chip_comp/CommandReceived(9) AND chip_comp/CommandReceived(11) AND NOT chip_comp/CommandReceived(12) AND NOT chip_comp/CommandReceived(15) AND chip_comp/CommandReceived(8) AND chip_comp/TXMAINSTATE_FFd1); FDCPE_chip_comp/Datasig0: FDCPE port map (chip_comp/Datasig(0),chip_comp/Datasig_D(0),CLK_40MHZ,POR,'0'); chip_comp/Datasig_D(0) <= ((EXP36_.EXP) OR (EXP39_.EXP) OR (HFn_B(3) AND NOT chip_comp/TXREADOUTSTATE_FFd3 AND NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd1 AND chip_comp/Datasig(0)) OR (HFn_B(2) AND chip_comp/TXREADOUTSTATE_FFd3 AND NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND chip_comp/Datasig(0)) OR (HFn_B(1) AND chip_comp/TXREADOUTSTATE_FFd3 AND chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND chip_comp/Datasig(0)) OR (HFn_B(0) AND NOT chip_comp/TXREADOUTSTATE_FFd3 AND chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND chip_comp/Datasig(0)) OR (chip_comp/StatusDataSel(2) AND chip_comp/ENABLEn_BReg(0) AND NOT chip_comp/TXREADOUTSTATE_FFd3 AND NOT chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND NOT chip_comp/TXREADOUTSTATE_FFd1 AND NOT chip_comp/GenDataCMD)); FDCPE_chip_comp/Datasig1: FDCPE port map (chip_comp/Datasig(1),chip_comp/Datasig_D(1),CLK_40MHZ,POR,'0'); chip_comp/Datasig_D(1) <= ((EXP40_.EXP) OR (DAC_DINsig$BUF7.EXP) OR (NOT HFn_B(2) AND chip_comp/TXREADOUTSTATE_FFd3 AND NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2) OR (chip_comp/TXREADOUTSTATE_FFd3 AND chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND chip_comp/Datasig(1)) OR (chip_comp/TXREADOUTSTATE_FFd3 AND NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND chip_comp/Datasig(1)) OR (chip_comp/TXREADOUTSTATE_FFd3 AND NOT chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND NOT chip_comp/TXREADOUTSTATE_FFd1) OR (NOT chip_comp/TXREADOUTSTATE_FFd3 AND chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND chip_comp/Datasig(1))); FDCPE_chip_comp/Datasig2: FDCPE port map (chip_comp/Datasig(2),chip_comp/Datasig_D(2),CLK_40MHZ,POR,'0'); chip_comp/Datasig_D(2) <= ((D_OEn_Bsig(2).EXP) OR (EXP38_.EXP) OR (HFn_B(3) AND NOT chip_comp/TXREADOUTSTATE_FFd3 AND NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd1 AND chip_comp/Datasig(2)) OR (HFn_B(2) AND chip_comp/TXREADOUTSTATE_FFd3 AND NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND chip_comp/Datasig(2)) OR (HFn_B(1) AND chip_comp/TXREADOUTSTATE_FFd3 AND chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND chip_comp/Datasig(2)) OR (HFn_B(0) AND NOT chip_comp/TXREADOUTSTATE_FFd3 AND chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND chip_comp/Datasig(2)) OR (chip_comp/StatusDataSel(2) AND chip_comp/ENABLEn_BReg(2) AND NOT chip_comp/TXREADOUTSTATE_FFd3 AND NOT chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND NOT chip_comp/TXREADOUTSTATE_FFd1 AND NOT chip_comp/GenDataCMD)); FDCPE_chip_comp/Datasig3: FDCPE port map (chip_comp/Datasig(3),chip_comp/Datasig_D(3),CLK_40MHZ,POR,'0'); chip_comp/Datasig_D(3) <= ((EXP44_.EXP) OR (DAC_DINsig$BUF8.EXP) OR (NOT HFn_B(3) AND NOT chip_comp/TXREADOUTSTATE_FFd3 AND NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd1) OR (chip_comp/TXREADOUTSTATE_FFd3 AND chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND chip_comp/Datasig(3)) OR (chip_comp/TXREADOUTSTATE_FFd3 AND NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND chip_comp/Datasig(3)) OR (chip_comp/TXREADOUTSTATE_FFd3 AND NOT chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND NOT chip_comp/TXREADOUTSTATE_FFd1) OR (NOT chip_comp/TXREADOUTSTATE_FFd3 AND chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND chip_comp/Datasig(3))); FDCPE_chip_comp/Datasig4: FDCPE port map (chip_comp/Datasig(4),chip_comp/Datasig_D(4),CLK_40MHZ,POR,'0'); chip_comp/Datasig_D(4) <= ((RST4n_Bsig(1).EXP) OR (HFn_B(3) AND NOT chip_comp/TXREADOUTSTATE_FFd3 AND NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd1 AND chip_comp/Datasig(4)) OR (HFn_B(2) AND chip_comp/TXREADOUTSTATE_FFd3 AND NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND chip_comp/Datasig(4)) OR (HFn_B(1) AND chip_comp/TXREADOUTSTATE_FFd3 AND chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND chip_comp/Datasig(4)) OR (HFn_B(0) AND NOT chip_comp/TXREADOUTSTATE_FFd3 AND chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND chip_comp/Datasig(4)) OR (NOT chip_comp/StatusDataSel(2) AND NOT chip_comp/StatusDataSel(3) AND NOT chip_comp/StatusDataSel(4) AND NOT chip_comp/TXREADOUTSTATE_FFd3 AND NOT chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND NOT chip_comp/TXREADOUTSTATE_FFd1 AND NOT chip_comp/GenDataCMD AND chip_comp/Datasig(4))); FDCPE_chip_comp/Datasig5: FDCPE port map (chip_comp/Datasig(5),chip_comp/Datasig_D(5),CLK_40MHZ,POR,'0'); chip_comp/Datasig_D(5) <= ((EXP24_.EXP) OR (EXP25_.EXP) OR (chip_comp/TXREADOUTSTATE_FFd3 AND chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND chip_comp/Datasig(5)) OR (chip_comp/TXREADOUTSTATE_FFd3 AND NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND chip_comp/Datasig(5)) OR (chip_comp/TXREADOUTSTATE_FFd3 AND NOT chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND NOT chip_comp/TXREADOUTSTATE_FFd1) OR (NOT chip_comp/TXREADOUTSTATE_FFd3 AND chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND chip_comp/Datasig(5)) OR (NOT chip_comp/TXREADOUTSTATE_FFd3 AND NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd1 AND chip_comp/Datasig(5))); FDCPE_chip_comp/Datasig6: FDCPE port map (chip_comp/Datasig(6),chip_comp/Datasig_D(6),CLK_40MHZ,POR,'0'); chip_comp/Datasig_D(6) <= ((EXP41_.EXP) OR (EXP42_.EXP) OR (HFn_B(3) AND NOT chip_comp/TXREADOUTSTATE_FFd3 AND NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd1 AND chip_comp/Datasig(6)) OR (HFn_B(2) AND chip_comp/TXREADOUTSTATE_FFd3 AND NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND chip_comp/Datasig(6)) OR (HFn_B(1) AND chip_comp/TXREADOUTSTATE_FFd3 AND chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND chip_comp/Datasig(6)) OR (HFn_B(0) AND NOT chip_comp/TXREADOUTSTATE_FFd3 AND chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND chip_comp/Datasig(6)) OR (DR1 AND chip_comp/StatusDataSel(3) AND NOT chip_comp/TXREADOUTSTATE_FFd3 AND NOT chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND NOT chip_comp/TXREADOUTSTATE_FFd1 AND NOT chip_comp/GenDataCMD)); FDCPE_chip_comp/Datasig7: FDCPE port map (chip_comp/Datasig(7),chip_comp/Datasig_D(7),CLK_40MHZ,POR,'0'); chip_comp/Datasig_D(7) <= ((EXP27_.EXP) OR (Datasig(8).EXP) OR (chip_comp/TXREADOUTSTATE_FFd3 AND chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND chip_comp/Datasig(7)) OR (chip_comp/TXREADOUTSTATE_FFd3 AND NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND chip_comp/Datasig(7)) OR (chip_comp/TXREADOUTSTATE_FFd3 AND NOT chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND NOT chip_comp/TXREADOUTSTATE_FFd1) OR (NOT chip_comp/TXREADOUTSTATE_FFd3 AND chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND chip_comp/Datasig(7)) OR (NOT chip_comp/TXREADOUTSTATE_FFd3 AND NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd1 AND chip_comp/Datasig(7))); FDCPE_chip_comp/Datasig8: FDCPE port map (chip_comp/Datasig(8),chip_comp/Datasig_D(8),CLK_40MHZ,POR,'0'); chip_comp/Datasig_D(8) <= ((EXP30_.EXP) OR (EXP31_.EXP) OR (HFn_B(3) AND NOT chip_comp/TXREADOUTSTATE_FFd3 AND NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd1 AND chip_comp/Datasig(8)) OR (HFn_B(2) AND chip_comp/TXREADOUTSTATE_FFd3 AND NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND chip_comp/Datasig(8)) OR (HFn_B(1) AND chip_comp/TXREADOUTSTATE_FFd3 AND chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND chip_comp/Datasig(8)) OR (HFn_B(0) AND NOT chip_comp/TXREADOUTSTATE_FFd3 AND chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND chip_comp/Datasig(8)) OR (PT0 AND chip_comp/StatusDataSel(3) AND NOT chip_comp/TXREADOUTSTATE_FFd3 AND NOT chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND NOT chip_comp/TXREADOUTSTATE_FFd1 AND NOT chip_comp/GenDataCMD)); FDCPE_chip_comp/Datasig9: FDCPE port map (chip_comp/Datasig(9),chip_comp/Datasig_D(9),CLK_40MHZ,POR,'0'); chip_comp/Datasig_D(9) <= ((ACQENnB2sig(0).EXP) OR (EXP21_.EXP) OR (chip_comp/TXREADOUTSTATE_FFd3 AND chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND chip_comp/Datasig(9)) OR (chip_comp/TXREADOUTSTATE_FFd3 AND NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND chip_comp/Datasig(9)) OR (chip_comp/TXREADOUTSTATE_FFd3 AND NOT chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND NOT chip_comp/TXREADOUTSTATE_FFd1) OR (NOT chip_comp/TXREADOUTSTATE_FFd3 AND chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND chip_comp/Datasig(9)) OR (NOT chip_comp/TXREADOUTSTATE_FFd3 AND NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd1 AND chip_comp/Datasig(9))); FDCPE_chip_comp/Datasig10: FDCPE port map (chip_comp/Datasig(10),chip_comp/Datasig_D(10),CLK_40MHZ,POR,'0'); chip_comp/Datasig_D(10) <= ((EXP22_.EXP) OR (HFn_B(3) AND NOT chip_comp/TXREADOUTSTATE_FFd3 AND NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd1 AND chip_comp/Datasig(10)) OR (HFn_B(2) AND chip_comp/TXREADOUTSTATE_FFd3 AND NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND chip_comp/Datasig(10)) OR (HFn_B(1) AND chip_comp/TXREADOUTSTATE_FFd3 AND chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND chip_comp/Datasig(10)) OR (HFn_B(0) AND NOT chip_comp/TXREADOUTSTATE_FFd3 AND chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND chip_comp/Datasig(10))); FDCPE_chip_comp/Datasig11: FDCPE port map (chip_comp/Datasig(11),chip_comp/Datasig_D(11),CLK_40MHZ,POR,'0'); chip_comp/Datasig_D(11) <= ((EXP34_.EXP) OR (chip_comp/TXREADOUTSTATE_FFd3 AND chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2) OR (NOT chip_comp/TXREADOUTSTATE_FFd3 AND chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2) OR (HFn_B(2) AND chip_comp/TXREADOUTSTATE_FFd3 AND chip_comp/TXREADOUTSTATE_FFd2 AND NOT chip_comp/Datasig(11)) OR (chip_comp/TXREADOUTSTATE_FFd3 AND NOT chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND chip_comp/TXREADOUTSTATE_FFd1) OR (NOT chip_comp/TXREADOUTSTATE_FFd3 AND NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND NOT chip_comp/TXREADOUTSTATE_FFd1)); FDCPE_chip_comp/Datasig12: FDCPE port map (chip_comp/Datasig(12),chip_comp/Datasig_D(12),CLK_40MHZ,POR,'0'); chip_comp/Datasig_D(12) <= ((Datasig(12).EXP) OR (HFn_B(3) AND NOT chip_comp/TXREADOUTSTATE_FFd3 AND NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd1 AND chip_comp/Datasig(12)) OR (HFn_B(2) AND chip_comp/TXREADOUTSTATE_FFd3 AND NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND chip_comp/Datasig(12)) OR (HFn_B(1) AND chip_comp/TXREADOUTSTATE_FFd3 AND chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND chip_comp/Datasig(12)) OR (HFn_B(0) AND NOT chip_comp/TXREADOUTSTATE_FFd3 AND chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND chip_comp/Datasig(12))); FDCPE_chip_comp/Datasig13: FDCPE port map (chip_comp/Datasig(13),chip_comp/Datasig_D(13),CLK_40MHZ,POR,'0'); chip_comp/Datasig_D(13) <= ((chip_comp/SimulData(7).EXP) OR (chip_comp/TXREADOUTSTATE_FFd3.EXP) OR (chip_comp/TXREADOUTSTATE_FFd3 AND chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2) OR (NOT chip_comp/TXREADOUTSTATE_FFd3 AND chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2) OR (HFn_B(2) AND chip_comp/TXREADOUTSTATE_FFd3 AND chip_comp/TXREADOUTSTATE_FFd2 AND NOT chip_comp/Datasig(13)) OR (chip_comp/TXREADOUTSTATE_FFd3 AND NOT chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND chip_comp/TXREADOUTSTATE_FFd1) OR (NOT chip_comp/TXREADOUTSTATE_FFd3 AND NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND NOT chip_comp/TXREADOUTSTATE_FFd1)); FDCPE_chip_comp/Datasig14: FDCPE port map (chip_comp/Datasig(14),chip_comp/Datasig_D(14),CLK_40MHZ,POR,'0'); chip_comp/Datasig_D(14) <= ((Datasig(15).EXP) OR (HFn_B(3) AND NOT chip_comp/TXREADOUTSTATE_FFd3 AND NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd1 AND chip_comp/Datasig(14)) OR (HFn_B(2) AND chip_comp/TXREADOUTSTATE_FFd3 AND NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND chip_comp/Datasig(14)) OR (HFn_B(1) AND chip_comp/TXREADOUTSTATE_FFd3 AND chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND chip_comp/Datasig(14)) OR (HFn_B(0) AND NOT chip_comp/TXREADOUTSTATE_FFd3 AND chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND chip_comp/Datasig(14))); FDCPE_chip_comp/Datasig15: FDCPE port map (chip_comp/Datasig(15),chip_comp/Datasig_D(15),CLK_40MHZ,POR,'0'); chip_comp/Datasig_D(15) <= ((EXP33_.EXP) OR (NOT HFn_B(3) AND NOT chip_comp/TXREADOUTSTATE_FFd3 AND NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd1) OR (chip_comp/TXREADOUTSTATE_FFd3 AND chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND chip_comp/Datasig(15)) OR (chip_comp/TXREADOUTSTATE_FFd3 AND NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND chip_comp/Datasig(15)) OR (NOT chip_comp/TXREADOUTSTATE_FFd3 AND chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND chip_comp/Datasig(15)) OR (NOT chip_comp/TXREADOUTSTATE_FFd3 AND NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd1 AND chip_comp/Datasig(15))); FDCPE_chip_comp/ENABLEn_BReg0: FDCPE port map (chip_comp/ENABLEn_BReg(0),chip_comp/CommandReceived(0),CLK_40MHZ,POR,'0',chip_comp/ENABLEn_BReg_CE(0)); chip_comp/ENABLEn_BReg_CE(0) <= (NOT chip_comp/RunningFlag AND NOT chip_comp/CommandReceived(10) AND NOT chip_comp/CommandReceived(13) AND NOT chip_comp/CommandReceived(14) AND NOT chip_comp/CommandReceived(9) AND NOT chip_comp/CommandReceived(11) AND NOT chip_comp/CommandReceived(12) AND NOT chip_comp/CommandReceived(15) AND chip_comp/CommandReceived(8) AND NOT chip_comp/CommandReceived(4) AND NOT chip_comp/CommandReceived(5) AND chip_comp/CommandReceived(6) AND NOT chip_comp/CommandReceived(7) AND chip_comp/TXMAINSTATE_FFd1); FDCPE_chip_comp/ENABLEn_BReg1: FDCPE port map (chip_comp/ENABLEn_BReg(1),chip_comp/CommandReceived(1),CLK_40MHZ,POR,'0',chip_comp/ENABLEn_BReg_CE(1)); chip_comp/ENABLEn_BReg_CE(1) <= (NOT chip_comp/RunningFlag AND NOT chip_comp/CommandReceived(10) AND NOT chip_comp/CommandReceived(13) AND NOT chip_comp/CommandReceived(14) AND NOT chip_comp/CommandReceived(9) AND NOT chip_comp/CommandReceived(11) AND NOT chip_comp/CommandReceived(12) AND NOT chip_comp/CommandReceived(15) AND chip_comp/CommandReceived(8) AND NOT chip_comp/CommandReceived(4) AND NOT chip_comp/CommandReceived(5) AND chip_comp/CommandReceived(6) AND NOT chip_comp/CommandReceived(7) AND chip_comp/TXMAINSTATE_FFd1); FDCPE_chip_comp/ENABLEn_BReg2: FDCPE port map (chip_comp/ENABLEn_BReg(2),chip_comp/CommandReceived(2),CLK_40MHZ,POR,'0',chip_comp/ENABLEn_BReg_CE(2)); chip_comp/ENABLEn_BReg_CE(2) <= (NOT chip_comp/RunningFlag AND NOT chip_comp/CommandReceived(10) AND NOT chip_comp/CommandReceived(13) AND NOT chip_comp/CommandReceived(14) AND NOT chip_comp/CommandReceived(9) AND NOT chip_comp/CommandReceived(11) AND NOT chip_comp/CommandReceived(12) AND NOT chip_comp/CommandReceived(15) AND chip_comp/CommandReceived(8) AND NOT chip_comp/CommandReceived(4) AND NOT chip_comp/CommandReceived(5) AND chip_comp/CommandReceived(6) AND NOT chip_comp/CommandReceived(7) AND chip_comp/TXMAINSTATE_FFd1); FDCPE_chip_comp/ENABLEn_BReg3: FDCPE port map (chip_comp/ENABLEn_BReg(3),chip_comp/CommandReceived(3),CLK_40MHZ,POR,'0',chip_comp/ENABLEn_BReg_CE(3)); chip_comp/ENABLEn_BReg_CE(3) <= (NOT chip_comp/RunningFlag AND NOT chip_comp/CommandReceived(10) AND NOT chip_comp/CommandReceived(13) AND NOT chip_comp/CommandReceived(14) AND NOT chip_comp/CommandReceived(9) AND NOT chip_comp/CommandReceived(11) AND NOT chip_comp/CommandReceived(12) AND NOT chip_comp/CommandReceived(15) AND chip_comp/CommandReceived(8) AND NOT chip_comp/CommandReceived(4) AND NOT chip_comp/CommandReceived(5) AND chip_comp/CommandReceived(6) AND NOT chip_comp/CommandReceived(7) AND chip_comp/TXMAINSTATE_FFd1); FTCPE_chip_comp/GenDataCMD: FTCPE port map (chip_comp/GenDataCMD,chip_comp/GenDataCMD_T,CLK_40MHZ,POR,'0'); chip_comp/GenDataCMD_T <= ((chip_comp/GenDataCMD AND NOT chip_comp/TXMAINSTATE_FFd1 AND NOT chip_comp/TXMAINSTATE_FFd2) OR (chip_comp/CommandReceived(10) AND chip_comp/CommandReceived(13) AND chip_comp/CommandReceived(14) AND chip_comp/CommandReceived(9) AND NOT chip_comp/CommandReceived(11) AND NOT chip_comp/CommandReceived(12) AND NOT chip_comp/CommandReceived(15) AND chip_comp/CommandReceived(8) AND NOT chip_comp/GenDataCMD AND chip_comp/TXMAINSTATE_FFd1)); FDCPE_chip_comp/GenDataCounter0: FDCPE port map (chip_comp/GenDataCounter(0),chip_comp/GenDataCounter_D(0),CLK_40MHZ,POR,'0'); chip_comp/GenDataCounter_D(0) <= (chip_comp/GenDatasig AND NOT chip_comp/GenDataCounter(0)); FDCPE_chip_comp/GenDataCounter1: FDCPE port map (chip_comp/GenDataCounter(1),chip_comp/GenDataCounter_D(1),CLK_40MHZ,POR,'0'); chip_comp/GenDataCounter_D(1) <= ((chip_comp/GenDatasig AND chip_comp/GenDataCounter(0) AND NOT chip_comp/GenDataCounter(1)) OR (chip_comp/GenDatasig AND NOT chip_comp/GenDataCounter(0) AND chip_comp/GenDataCounter(1))); FTCPE_chip_comp/GenDataCounter2: FTCPE port map (chip_comp/GenDataCounter(2),chip_comp/GenDataCounter_T(2),CLK_40MHZ,POR,'0'); chip_comp/GenDataCounter_T(2) <= ((NOT chip_comp/GenDatasig AND chip_comp/GenDataCounter(2)) OR (chip_comp/GenDatasig AND chip_comp/GenDataCounter(0) AND chip_comp/GenDataCounter(1))); FTCPE_chip_comp/GenDataCounter3: FTCPE port map (chip_comp/GenDataCounter(3),chip_comp/GenDataCounter_T(3),CLK_40MHZ,POR,'0'); chip_comp/GenDataCounter_T(3) <= ((NOT chip_comp/GenDatasig AND chip_comp/GenDataCounter(3)) OR (chip_comp/GenDatasig AND chip_comp/GenDataCounter(0) AND chip_comp/GenDataCounter(1) AND chip_comp/GenDataCounter(2))); FTCPE_chip_comp/GenDataCounter4: FTCPE port map (chip_comp/GenDataCounter(4),chip_comp/GenDataCounter_T(4),CLK_40MHZ,POR,'0'); chip_comp/GenDataCounter_T(4) <= ((NOT chip_comp/GenDatasig AND chip_comp/GenDataCounter(4)) OR (chip_comp/GenDatasig AND chip_comp/GenDataCounter(0) AND chip_comp/GenDataCounter(1) AND chip_comp/GenDataCounter(2) AND chip_comp/GenDataCounter(3))); FTCPE_chip_comp/GenDataCounter5: FTCPE port map (chip_comp/GenDataCounter(5),chip_comp/GenDataCounter_T(5),CLK_40MHZ,POR,'0'); chip_comp/GenDataCounter_T(5) <= ((NOT chip_comp/GenDatasig AND chip_comp/GenDataCounter(5)) OR (chip_comp/GenDatasig AND chip_comp/GenDataCounter(0) AND chip_comp/GenDataCounter(1) AND chip_comp/GenDataCounter(2) AND chip_comp/GenDataCounter(3) AND chip_comp/GenDataCounter(4))); FTCPE_chip_comp/GenDataCounter6: FTCPE port map (chip_comp/GenDataCounter(6),chip_comp/GenDataCounter_T(6),CLK_40MHZ,POR,'0'); chip_comp/GenDataCounter_T(6) <= ((NOT chip_comp/GenDatasig AND chip_comp/GenDataCounter(6)) OR (chip_comp/GenDatasig AND chip_comp/GenDataCounter(0) AND chip_comp/GenDataCounter(1) AND chip_comp/GenDataCounter(2) AND chip_comp/GenDataCounter(3) AND chip_comp/GenDataCounter(4) AND chip_comp/GenDataCounter(5))); FTCPE_chip_comp/GenDataCounter7: FTCPE port map (chip_comp/GenDataCounter(7),chip_comp/GenDataCounter_T(7),CLK_40MHZ,POR,'0'); chip_comp/GenDataCounter_T(7) <= ((NOT chip_comp/GenDatasig AND chip_comp/GenDataCounter(7)) OR (chip_comp/GenDatasig AND chip_comp/GenDataCounter(0) AND chip_comp/GenDataCounter(1) AND chip_comp/GenDataCounter(2) AND chip_comp/GenDataCounter(3) AND chip_comp/GenDataCounter(4) AND chip_comp/GenDataCounter(5) AND chip_comp/GenDataCounter(6))); FTCPE_chip_comp/GenDataCounter8: FTCPE port map (chip_comp/GenDataCounter(8),chip_comp/GenDataCounter_T(8),CLK_40MHZ,POR,'0'); chip_comp/GenDataCounter_T(8) <= ((NOT chip_comp/GenDatasig AND chip_comp/GenDataCounter(8)) OR (chip_comp/GenDatasig AND chip_comp/GenDataCounter(0) AND chip_comp/GenDataCounter(1) AND chip_comp/GenDataCounter(2) AND chip_comp/GenDataCounter(3) AND chip_comp/GenDataCounter(4) AND chip_comp/GenDataCounter(5) AND chip_comp/GenDataCounter(6) AND chip_comp/GenDataCounter(7))); FTCPE_chip_comp/GenDataCounter9: FTCPE port map (chip_comp/GenDataCounter(9),chip_comp/GenDataCounter_T(9),CLK_40MHZ,POR,'0'); chip_comp/GenDataCounter_T(9) <= ((NOT chip_comp/GenDatasig AND chip_comp/GenDataCounter(9)) OR (chip_comp/GenDatasig AND chip_comp/GenDataCounter(0) AND chip_comp/GenDataCounter(1) AND chip_comp/GenDataCounter(2) AND chip_comp/GenDataCounter(3) AND chip_comp/GenDataCounter(4) AND chip_comp/GenDataCounter(5) AND chip_comp/GenDataCounter(6) AND chip_comp/GenDataCounter(7) AND chip_comp/GenDataCounter(8))); FTCPE_chip_comp/GenDataCounter10: FTCPE port map (chip_comp/GenDataCounter(10),chip_comp/GenDataCounter_T(10),CLK_40MHZ,POR,'0'); chip_comp/GenDataCounter_T(10) <= ((NOT chip_comp/GenDatasig AND chip_comp/GenDataCounter(10)) OR (chip_comp/GenDatasig AND chip_comp/GenDataCounter(0) AND chip_comp/GenDataCounter(1) AND chip_comp/GenDataCounter(2) AND chip_comp/GenDataCounter(3) AND chip_comp/GenDataCounter(4) AND chip_comp/GenDataCounter(5) AND chip_comp/GenDataCounter(6) AND chip_comp/GenDataCounter(7) AND chip_comp/GenDataCounter(8) AND chip_comp/GenDataCounter(9))); FTCPE_chip_comp/GenDataCounter11: FTCPE port map (chip_comp/GenDataCounter(11),chip_comp/GenDataCounter_T(11),CLK_40MHZ,POR,'0'); chip_comp/GenDataCounter_T(11) <= ((NOT chip_comp/GenDatasig AND chip_comp/GenDataCounter(11)) OR (chip_comp/GenDatasig AND chip_comp/GenDataCounter(0) AND chip_comp/GenDataCounter(10) AND chip_comp/GenDataCounter(1) AND chip_comp/GenDataCounter(2) AND chip_comp/GenDataCounter(3) AND chip_comp/GenDataCounter(4) AND chip_comp/GenDataCounter(5) AND chip_comp/GenDataCounter(6) AND chip_comp/GenDataCounter(7) AND chip_comp/GenDataCounter(8) AND chip_comp/GenDataCounter(9))); FTCPE_chip_comp/GenDataCounter12: FTCPE port map (chip_comp/GenDataCounter(12),chip_comp/GenDataCounter_T(12),CLK_40MHZ,POR,'0'); chip_comp/GenDataCounter_T(12) <= ((NOT chip_comp/GenDatasig AND chip_comp/GenDataCounter(12)) OR (chip_comp/GenDatasig AND chip_comp/GenDataCounter(0) AND chip_comp/GenDataCounter(10) AND chip_comp/GenDataCounter(11) AND chip_comp/GenDataCounter(1) AND chip_comp/GenDataCounter(2) AND chip_comp/GenDataCounter(3) AND chip_comp/GenDataCounter(4) AND chip_comp/GenDataCounter(5) AND chip_comp/GenDataCounter(6) AND chip_comp/GenDataCounter(7) AND chip_comp/GenDataCounter(8) AND chip_comp/GenDataCounter(9))); FTCPE_chip_comp/GenDataCounter13: FTCPE port map (chip_comp/GenDataCounter(13),chip_comp/GenDataCounter_T(13),CLK_40MHZ,POR,'0'); chip_comp/GenDataCounter_T(13) <= ((NOT chip_comp/GenDatasig AND chip_comp/GenDataCounter(13)) OR (chip_comp/GenDatasig AND chip_comp/GenDataCounter(0) AND chip_comp/GenDataCounter(10) AND chip_comp/GenDataCounter(11) AND chip_comp/GenDataCounter(12) AND chip_comp/GenDataCounter(1) AND chip_comp/GenDataCounter(2) AND chip_comp/GenDataCounter(3) AND chip_comp/GenDataCounter(4) AND chip_comp/GenDataCounter(5) AND chip_comp/GenDataCounter(6) AND chip_comp/GenDataCounter(7) AND chip_comp/GenDataCounter(8) AND chip_comp/GenDataCounter(9))); FTCPE_chip_comp/GenDataCounter14: FTCPE port map (chip_comp/GenDataCounter(14),chip_comp/GenDataCounter_T(14),CLK_40MHZ,POR,'0'); chip_comp/GenDataCounter_T(14) <= ((NOT chip_comp/GenDatasig AND chip_comp/GenDataCounter(14)) OR (chip_comp/GenDatasig AND chip_comp/GenDataCounter(0) AND chip_comp/GenDataCounter(10) AND chip_comp/GenDataCounter(11) AND chip_comp/GenDataCounter(12) AND chip_comp/GenDataCounter(13) AND chip_comp/GenDataCounter(1) AND chip_comp/GenDataCounter(2) AND chip_comp/GenDataCounter(3) AND chip_comp/GenDataCounter(4) AND chip_comp/GenDataCounter(5) AND chip_comp/GenDataCounter(6) AND chip_comp/GenDataCounter(7) AND chip_comp/GenDataCounter(8) AND chip_comp/GenDataCounter(9))); FTCPE_chip_comp/GenDataCounter15: FTCPE port map (chip_comp/GenDataCounter(15),chip_comp/GenDataCounter_T(15),CLK_40MHZ,POR,'0'); chip_comp/GenDataCounter_T(15) <= ((NOT chip_comp/GenDatasig AND chip_comp/GenDataCounter(15)) OR (chip_comp/GenDatasig AND chip_comp/GenDataCounter(0) AND chip_comp/GenDataCounter(10) AND chip_comp/GenDataCounter(11) AND chip_comp/GenDataCounter(12) AND chip_comp/GenDataCounter(13) AND chip_comp/GenDataCounter(14) AND chip_comp/GenDataCounter(1) AND chip_comp/GenDataCounter(2) AND chip_comp/GenDataCounter(3) AND chip_comp/GenDataCounter(4) AND chip_comp/GenDataCounter(5) AND chip_comp/GenDataCounter(6) AND chip_comp/GenDataCounter(7) AND chip_comp/GenDataCounter(8) AND chip_comp/GenDataCounter(9))); FDCPE_chip_comp/GenDataDonesig: FDCPE port map (chip_comp/GenDataDonesig,chip_comp/GenDataDonesig_D,CLK_40MHZ,POR,'0'); chip_comp/GenDataDonesig_D <= (NOT chip_comp/GenDataCounter(0) AND chip_comp/GenDataCounter(10) AND chip_comp/GenDataCounter(11) AND NOT chip_comp/GenDataCounter(12) AND NOT chip_comp/GenDataCounter(13) AND NOT chip_comp/GenDataCounter(14) AND chip_comp/GenDataCounter(1) AND chip_comp/GenDataCounter(2) AND chip_comp/GenDataCounter(3) AND chip_comp/GenDataCounter(4) AND chip_comp/GenDataCounter(5) AND chip_comp/GenDataCounter(6) AND chip_comp/GenDataCounter(7) AND chip_comp/GenDataCounter(8) AND chip_comp/GenDataCounter(9) AND NOT chip_comp/GenDataCounter(15)); FDCPE_chip_comp/GenDatasig: FDCPE port map (chip_comp/GenDatasig,chip_comp/GenDatasig_D,CLK_40MHZ,POR,'0'); chip_comp/GenDatasig_D <= ((Datasig(3).EXP) OR (HFn_B(3) AND NOT chip_comp/TXREADOUTSTATE_FFd3 AND NOT chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2) OR (NOT chip_comp/TXREADOUTSTATE_FFd3 AND NOT chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND NOT chip_comp/TXREADOUTSTATE_FFd1) OR (HFn_B(2) AND chip_comp/TXREADOUTSTATE_FFd3 AND NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND NOT chip_comp/TXREADOUTSTATE_FFd1) OR (HFn_B(1) AND chip_comp/TXREADOUTSTATE_FFd3 AND chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND NOT chip_comp/TXREADOUTSTATE_FFd1)); FDCPE_chip_comp/LinkStablished: FDCPE port map (chip_comp/LinkStablished,chip_comp/LinkStablished_D,CLK_40MHZ,POR,'0'); chip_comp/LinkStablished_D <= ((chip_comp/LinkStablished AND chip_comp/TXMAINSTATE_FFd1) OR (NOT chip_comp/TXMAINSTATE_FFd1 AND NOT chip_comp/TXMAINSTATE_FFd2)); FDCPE_chip_comp/ReceiveCommandComp/clr_sr: FDCPE port map (chip_comp/ReceiveCommandComp/clr_sr,chip_comp/ReceiveCommandComp/clr_sr_D,CLK_40MHZ,POR,'0'); chip_comp/ReceiveCommandComp/clr_sr_D <= (chip_comp/ReceiveCommandComp/sr(1) AND NOT chip_comp/ReceiveCommandComp/sr(2) AND chip_comp/ReceiveCommandComp/sr(3) AND chip_comp/ReceiveCommandComp/sr(0)); FDCPE_chip_comp/ReceiveCommandComp/sr0: FDCPE port map (chip_comp/ReceiveCommandComp/sr(0),chip_comp/ReceiveCommandComp/sr_D(0),NOT CLK_40MHZ,POR,'0'); chip_comp/ReceiveCommandComp/sr_D(0) <= (NOT chip_comp/ReceiveCommandComp/clr_sr AND chip_comp/ReceiveCommandComp/sr(1)); FDCPE_chip_comp/ReceiveCommandComp/sr1: FDCPE port map (chip_comp/ReceiveCommandComp/sr(1),chip_comp/ReceiveCommandComp/sr_D(1),NOT CLK_40MHZ,POR,'0'); chip_comp/ReceiveCommandComp/sr_D(1) <= (NOT chip_comp/ReceiveCommandComp/clr_sr AND chip_comp/ReceiveCommandComp/sr(2)); FDCPE_chip_comp/ReceiveCommandComp/sr2: FDCPE port map (chip_comp/ReceiveCommandComp/sr(2),chip_comp/ReceiveCommandComp/sr_D(2),NOT CLK_40MHZ,POR,'0'); chip_comp/ReceiveCommandComp/sr_D(2) <= (NOT chip_comp/ReceiveCommandComp/clr_sr AND chip_comp/ReceiveCommandComp/sr(3)); FDCPE_chip_comp/ReceiveCommandComp/sr3: FDCPE port map (chip_comp/ReceiveCommandComp/sr(3),chip_comp/ReceiveCommandComp/sr_D(3),NOT CLK_40MHZ,POR,'0'); chip_comp/ReceiveCommandComp/sr_D(3) <= (NOT chip_comp/ReceiveCommandComp/clr_sr AND chip_comp/ReceiveCommandComp/sr(4)); FDCPE_chip_comp/ReceiveCommandComp/sr4: FDCPE port map (chip_comp/ReceiveCommandComp/sr(4),chip_comp/ReceiveCommandComp/sr_D(4),NOT CLK_40MHZ,POR,'0'); chip_comp/ReceiveCommandComp/sr_D(4) <= (NOT chip_comp/ReceiveCommandComp/clr_sr AND chip_comp/ReceiveCommandComp/sr(5)); FDCPE_chip_comp/ReceiveCommandComp/sr5: FDCPE port map (chip_comp/ReceiveCommandComp/sr(5),chip_comp/ReceiveCommandComp/sr_D(5),NOT CLK_40MHZ,POR,'0'); chip_comp/ReceiveCommandComp/sr_D(5) <= (NOT chip_comp/ReceiveCommandComp/clr_sr AND chip_comp/ReceiveCommandComp/sr(6)); FDCPE_chip_comp/ReceiveCommandComp/sr6: FDCPE port map (chip_comp/ReceiveCommandComp/sr(6),chip_comp/ReceiveCommandComp/sr_D(6),NOT CLK_40MHZ,POR,'0'); chip_comp/ReceiveCommandComp/sr_D(6) <= (NOT chip_comp/ReceiveCommandComp/clr_sr AND chip_comp/ReceiveCommandComp/sr(7)); FDCPE_chip_comp/ReceiveCommandComp/sr7: FDCPE port map (chip_comp/ReceiveCommandComp/sr(7),chip_comp/ReceiveCommandComp/sr_D(7),NOT CLK_40MHZ,POR,'0'); chip_comp/ReceiveCommandComp/sr_D(7) <= (NOT chip_comp/ReceiveCommandComp/clr_sr AND chip_comp/ReceiveCommandComp/sr(8)); FDCPE_chip_comp/ReceiveCommandComp/sr8: FDCPE port map (chip_comp/ReceiveCommandComp/sr(8),chip_comp/ReceiveCommandComp/sr_D(8),NOT CLK_40MHZ,POR,'0'); chip_comp/ReceiveCommandComp/sr_D(8) <= (NOT chip_comp/ReceiveCommandComp/clr_sr AND chip_comp/ReceiveCommandComp/sr(9)); FDCPE_chip_comp/ReceiveCommandComp/sr9: FDCPE port map (chip_comp/ReceiveCommandComp/sr(9),chip_comp/ReceiveCommandComp/sr_D(9),NOT CLK_40MHZ,POR,'0'); chip_comp/ReceiveCommandComp/sr_D(9) <= (NOT chip_comp/ReceiveCommandComp/clr_sr AND chip_comp/ReceiveCommandComp/sr(10)); FDCPE_chip_comp/ReceiveCommandComp/sr10: FDCPE port map (chip_comp/ReceiveCommandComp/sr(10),chip_comp/ReceiveCommandComp/sr_D(10),NOT CLK_40MHZ,POR,'0'); chip_comp/ReceiveCommandComp/sr_D(10) <= (NOT chip_comp/ReceiveCommandComp/clr_sr AND chip_comp/ReceiveCommandComp/sr(11)); FDCPE_chip_comp/ReceiveCommandComp/sr11: FDCPE port map (chip_comp/ReceiveCommandComp/sr(11),chip_comp/ReceiveCommandComp/sr_D(11),NOT CLK_40MHZ,POR,'0'); chip_comp/ReceiveCommandComp/sr_D(11) <= (NOT chip_comp/ReceiveCommandComp/clr_sr AND chip_comp/ReceiveCommandComp/sr(12)); FDCPE_chip_comp/ReceiveCommandComp/sr12: FDCPE port map (chip_comp/ReceiveCommandComp/sr(12),chip_comp/ReceiveCommandComp/sr_D(12),NOT CLK_40MHZ,POR,'0'); chip_comp/ReceiveCommandComp/sr_D(12) <= (NOT chip_comp/ReceiveCommandComp/clr_sr AND chip_comp/ReceiveCommandComp/sr(13)); FDCPE_chip_comp/ReceiveCommandComp/sr13: FDCPE port map (chip_comp/ReceiveCommandComp/sr(13),chip_comp/ReceiveCommandComp/sr_D(13),NOT CLK_40MHZ,POR,'0'); chip_comp/ReceiveCommandComp/sr_D(13) <= (NOT chip_comp/ReceiveCommandComp/clr_sr AND chip_comp/ReceiveCommandComp/sr(14)); FDCPE_chip_comp/ReceiveCommandComp/sr14: FDCPE port map (chip_comp/ReceiveCommandComp/sr(14),chip_comp/ReceiveCommandComp/sr_D(14),NOT CLK_40MHZ,POR,'0'); chip_comp/ReceiveCommandComp/sr_D(14) <= (NOT chip_comp/ReceiveCommandComp/clr_sr AND chip_comp/ReceiveCommandComp/sr(15)); FDCPE_chip_comp/ReceiveCommandComp/sr15: FDCPE port map (chip_comp/ReceiveCommandComp/sr(15),chip_comp/ReceiveCommandComp/sr_D(15),NOT CLK_40MHZ,POR,'0'); chip_comp/ReceiveCommandComp/sr_D(15) <= (NOT chip_comp/ReceiveCommandComp/clr_sr AND chip_comp/ReceiveCommandComp/sr(16)); FDCPE_chip_comp/ReceiveCommandComp/sr16: FDCPE port map (chip_comp/ReceiveCommandComp/sr(16),chip_comp/ReceiveCommandComp/sr_D(16),NOT CLK_40MHZ,POR,'0'); chip_comp/ReceiveCommandComp/sr_D(16) <= (NOT chip_comp/ReceiveCommandComp/clr_sr AND chip_comp/ReceiveCommandComp/sr(17)); FDCPE_chip_comp/ReceiveCommandComp/sr17: FDCPE port map (chip_comp/ReceiveCommandComp/sr(17),chip_comp/ReceiveCommandComp/sr_D(17),NOT CLK_40MHZ,POR,'0'); chip_comp/ReceiveCommandComp/sr_D(17) <= (NOT chip_comp/ReceiveCommandComp/clr_sr AND chip_comp/ReceiveCommandComp/sr(18)); FDCPE_chip_comp/ReceiveCommandComp/sr18: FDCPE port map (chip_comp/ReceiveCommandComp/sr(18),chip_comp/ReceiveCommandComp/sr_D(18),NOT CLK_40MHZ,POR,'0'); chip_comp/ReceiveCommandComp/sr_D(18) <= (NOT chip_comp/ReceiveCommandComp/clr_sr AND chip_comp/ReceiveCommandComp/sr(19)); FDCPE_chip_comp/ReceiveCommandComp/sr19: FDCPE port map (chip_comp/ReceiveCommandComp/sr(19),chip_comp/ReceiveCommandComp/sr_D(19),NOT CLK_40MHZ,POR,'0'); chip_comp/ReceiveCommandComp/sr_D(19) <= (NOT chip_comp/ReceiveCommandComp/clr_sr AND chip_comp/ReceiveCommandComp/sr(20)); FDCPE_chip_comp/ReceiveCommandComp/sr20: FDCPE port map (chip_comp/ReceiveCommandComp/sr(20),chip_comp/ReceiveCommandComp/sr_D(20),NOT CLK_40MHZ,POR,'0'); chip_comp/ReceiveCommandComp/sr_D(20) <= (NOT chip_comp/ReceiveCommandComp/clr_sr AND CTRL); FTCPE_chip_comp/RunningFlag: FTCPE port map (chip_comp/RunningFlag,chip_comp/RunningFlag_T,CLK_40MHZ,POR,'0',chip_comp/TXMAINSTATE_FFd1); chip_comp/RunningFlag_T <= ((chip_comp/RunningFlag AND NOT chip_comp/CommandReceived(10) AND NOT chip_comp/CommandReceived(13) AND NOT chip_comp/CommandReceived(14) AND chip_comp/CommandReceived(9) AND NOT chip_comp/CommandReceived(11) AND NOT chip_comp/CommandReceived(12) AND NOT chip_comp/CommandReceived(15) AND chip_comp/CommandReceived(8)) OR (NOT chip_comp/RunningFlag AND NOT chip_comp/CommandReceived(10) AND NOT chip_comp/CommandReceived(13) AND NOT chip_comp/CommandReceived(14) AND chip_comp/CommandReceived(9) AND NOT chip_comp/CommandReceived(11) AND NOT chip_comp/CommandReceived(12) AND NOT chip_comp/CommandReceived(15) AND NOT chip_comp/CommandReceived(8))); FDCPE_chip_comp/SamplingClock0: FDCPE port map (chip_comp/SamplingClock(0),chip_comp/CommandReceived(0),CLK_40MHZ,POR,'0',chip_comp/SamplingClock_CE(0)); chip_comp/SamplingClock_CE(0) <= (NOT chip_comp/CommandReceived(10) AND NOT chip_comp/CommandReceived(13) AND NOT chip_comp/CommandReceived(14) AND NOT chip_comp/CommandReceived(9) AND chip_comp/CommandReceived(11) AND NOT chip_comp/CommandReceived(12) AND NOT chip_comp/CommandReceived(15) AND chip_comp/CommandReceived(8) AND chip_comp/TXMAINSTATE_FFd1); FDCPE_chip_comp/SamplingClock1: FDCPE port map (chip_comp/SamplingClock(1),chip_comp/CommandReceived(1),CLK_40MHZ,POR,'0',chip_comp/SamplingClock_CE(1)); chip_comp/SamplingClock_CE(1) <= (NOT chip_comp/CommandReceived(10) AND NOT chip_comp/CommandReceived(13) AND NOT chip_comp/CommandReceived(14) AND NOT chip_comp/CommandReceived(9) AND chip_comp/CommandReceived(11) AND NOT chip_comp/CommandReceived(12) AND NOT chip_comp/CommandReceived(15) AND chip_comp/CommandReceived(8) AND chip_comp/TXMAINSTATE_FFd1); FDCPE_chip_comp/SimulData0: FDCPE port map (chip_comp/SimulData(0),chip_comp/GenDataCounter(0),CLK_40MHZ,POR,'0'); FDCPE_chip_comp/SimulData1: FDCPE port map (chip_comp/SimulData(1),chip_comp/GenDataCounter(1),CLK_40MHZ,POR,'0'); FDCPE_chip_comp/SimulData2: FDCPE port map (chip_comp/SimulData(2),chip_comp/GenDataCounter(2),CLK_40MHZ,POR,'0'); FDCPE_chip_comp/SimulData3: FDCPE port map (chip_comp/SimulData(3),chip_comp/GenDataCounter(3),CLK_40MHZ,POR,'0'); FDCPE_chip_comp/SimulData4: FDCPE port map (chip_comp/SimulData(4),chip_comp/GenDataCounter(4),CLK_40MHZ,POR,'0'); FDCPE_chip_comp/SimulData5: FDCPE port map (chip_comp/SimulData(5),chip_comp/GenDataCounter(5),CLK_40MHZ,POR,'0'); FDCPE_chip_comp/SimulData6: FDCPE port map (chip_comp/SimulData(6),chip_comp/GenDataCounter(6),CLK_40MHZ,POR,'0'); FDCPE_chip_comp/SimulData7: FDCPE port map (chip_comp/SimulData(7),chip_comp/GenDataCounter(7),CLK_40MHZ,POR,'0'); FDCPE_chip_comp/SimulData8: FDCPE port map (chip_comp/SimulData(8),chip_comp/GenDataCounter(8),CLK_40MHZ,POR,'0'); FDCPE_chip_comp/SimulData9: FDCPE port map (chip_comp/SimulData(9),chip_comp/GenDataCounter(9),CLK_40MHZ,POR,'0'); FDCPE_chip_comp/SimulData10: FDCPE port map (chip_comp/SimulData(10),chip_comp/GenDataCounter(10),CLK_40MHZ,POR,'0'); FDCPE_chip_comp/SimulData11: FDCPE port map (chip_comp/SimulData(11),chip_comp/GenDataCounter(11),CLK_40MHZ,POR,'0'); FDCPE_chip_comp/SimulData12: FDCPE port map (chip_comp/SimulData(12),chip_comp/GenDataCounter(12),CLK_40MHZ,POR,'0'); FDCPE_chip_comp/SimulData13: FDCPE port map (chip_comp/SimulData(13),chip_comp/GenDataCounter(13),CLK_40MHZ,POR,'0'); FDCPE_chip_comp/SimulData14: FDCPE port map (chip_comp/SimulData(14),chip_comp/GenDataCounter(14),CLK_40MHZ,POR,'0'); FDCPE_chip_comp/SimulData15: FDCPE port map (chip_comp/SimulData(15),chip_comp/GenDataCounter(15),CLK_40MHZ,POR,'0'); FDCPE_chip_comp/StatusDataSel0: FDCPE port map (chip_comp/StatusDataSel(0),chip_comp/CommandReceived(0),CLK_40MHZ,POR,'0',chip_comp/StatusDataSel_CE(0)); chip_comp/StatusDataSel_CE(0) <= (chip_comp/CommandReceived(10) AND NOT chip_comp/CommandReceived(13) AND NOT chip_comp/CommandReceived(14) AND NOT chip_comp/CommandReceived(9) AND chip_comp/CommandReceived(11) AND NOT chip_comp/CommandReceived(12) AND NOT chip_comp/CommandReceived(15) AND NOT chip_comp/CommandReceived(8) AND chip_comp/TXMAINSTATE_FFd1); FDCPE_chip_comp/StatusDataSel1: FDCPE port map (chip_comp/StatusDataSel(1),chip_comp/CommandReceived(1),CLK_40MHZ,POR,'0',chip_comp/StatusDataSel_CE(1)); chip_comp/StatusDataSel_CE(1) <= (chip_comp/CommandReceived(10) AND NOT chip_comp/CommandReceived(13) AND NOT chip_comp/CommandReceived(14) AND NOT chip_comp/CommandReceived(9) AND chip_comp/CommandReceived(11) AND NOT chip_comp/CommandReceived(12) AND NOT chip_comp/CommandReceived(15) AND NOT chip_comp/CommandReceived(8) AND chip_comp/TXMAINSTATE_FFd1); FDCPE_chip_comp/StatusDataSel2: FDCPE port map (chip_comp/StatusDataSel(2),chip_comp/CommandReceived(2),CLK_40MHZ,POR,'0',chip_comp/StatusDataSel_CE(2)); chip_comp/StatusDataSel_CE(2) <= (chip_comp/CommandReceived(10) AND NOT chip_comp/CommandReceived(13) AND NOT chip_comp/CommandReceived(14) AND NOT chip_comp/CommandReceived(9) AND chip_comp/CommandReceived(11) AND NOT chip_comp/CommandReceived(12) AND NOT chip_comp/CommandReceived(15) AND NOT chip_comp/CommandReceived(8) AND chip_comp/TXMAINSTATE_FFd1); FDCPE_chip_comp/StatusDataSel3: FDCPE port map (chip_comp/StatusDataSel(3),chip_comp/CommandReceived(3),CLK_40MHZ,POR,'0',chip_comp/StatusDataSel_CE(3)); chip_comp/StatusDataSel_CE(3) <= (chip_comp/CommandReceived(10) AND NOT chip_comp/CommandReceived(13) AND NOT chip_comp/CommandReceived(14) AND NOT chip_comp/CommandReceived(9) AND chip_comp/CommandReceived(11) AND NOT chip_comp/CommandReceived(12) AND NOT chip_comp/CommandReceived(15) AND NOT chip_comp/CommandReceived(8) AND chip_comp/TXMAINSTATE_FFd1); FDCPE_chip_comp/StatusDataSel4: FDCPE port map (chip_comp/StatusDataSel(4),chip_comp/CommandReceived(4),CLK_40MHZ,POR,'0',chip_comp/StatusDataSel_CE(4)); chip_comp/StatusDataSel_CE(4) <= (chip_comp/CommandReceived(10) AND NOT chip_comp/CommandReceived(13) AND NOT chip_comp/CommandReceived(14) AND NOT chip_comp/CommandReceived(9) AND chip_comp/CommandReceived(11) AND NOT chip_comp/CommandReceived(12) AND NOT chip_comp/CommandReceived(15) AND NOT chip_comp/CommandReceived(8) AND chip_comp/TXMAINSTATE_FFd1); FTCPE_chip_comp/TCLKCounter0: FTCPE port map (chip_comp/TCLKCounter(0),chip_comp/TCLKCounter_T(0),CLK_40MHZ,POR,'0'); chip_comp/TCLKCounter_T(0) <= ((chip_comp/TimerInterval(2) AND chip_comp/TimerInterval(0) AND NOT chip_comp/TCLKCounter(0) AND NOT chip_comp/TCLKCounter(1) AND NOT chip_comp/TCLKCounter(2) AND NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND NOT chip_comp/TCLKCounter(5) AND NOT chip_comp/TCLKCounter(6) AND NOT chip_comp/TCLKCounter(7) AND NOT chip_comp/TCLKCounter(8) AND NOT chip_comp/TCLKCounter(9) AND NOT chip_comp/TCLKCounter(10)) OR (chip_comp/TimerInterval(2) AND chip_comp/TimerInterval(1) AND NOT chip_comp/TCLKCounter(0) AND NOT chip_comp/TCLKCounter(1) AND NOT chip_comp/TCLKCounter(2) AND NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND NOT chip_comp/TCLKCounter(5) AND NOT chip_comp/TCLKCounter(6) AND NOT chip_comp/TCLKCounter(7) AND NOT chip_comp/TCLKCounter(8) AND NOT chip_comp/TCLKCounter(9) AND NOT chip_comp/TCLKCounter(10))); FTCPE_chip_comp/TCLKCounter1: FTCPE port map (chip_comp/TCLKCounter(1),chip_comp/TCLKCounter_T(1),CLK_40MHZ,POR,'0'); chip_comp/TCLKCounter_T(1) <= ((chip_comp/TCLKCounter(0)) OR (chip_comp/TimerInterval(2) AND chip_comp/TimerInterval(0) AND NOT chip_comp/TCLKCounter(1) AND NOT chip_comp/TCLKCounter(2) AND NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND NOT chip_comp/TCLKCounter(5) AND NOT chip_comp/TCLKCounter(6) AND NOT chip_comp/TCLKCounter(7) AND NOT chip_comp/TCLKCounter(8) AND NOT chip_comp/TCLKCounter(9) AND NOT chip_comp/TCLKCounter(10)) OR (chip_comp/TimerInterval(2) AND chip_comp/TimerInterval(1) AND NOT chip_comp/TCLKCounter(1) AND NOT chip_comp/TCLKCounter(2) AND NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND NOT chip_comp/TCLKCounter(5) AND NOT chip_comp/TCLKCounter(6) AND NOT chip_comp/TCLKCounter(7) AND NOT chip_comp/TCLKCounter(8) AND NOT chip_comp/TCLKCounter(9) AND NOT chip_comp/TCLKCounter(10))); FTCPE_chip_comp/TCLKCounter2: FTCPE port map (chip_comp/TCLKCounter(2),chip_comp/TCLKCounter_T(2),CLK_40MHZ,POR,'0'); chip_comp/TCLKCounter_T(2) <= ((chip_comp/TCLKCounter(0)) OR (chip_comp/TCLKCounter(1)) OR (chip_comp/TimerInterval(2) AND chip_comp/TimerInterval(0) AND NOT chip_comp/TCLKCounter(2) AND NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND NOT chip_comp/TCLKCounter(5) AND NOT chip_comp/TCLKCounter(6) AND NOT chip_comp/TCLKCounter(7) AND NOT chip_comp/TCLKCounter(8) AND NOT chip_comp/TCLKCounter(9) AND NOT chip_comp/TCLKCounter(10)) OR (chip_comp/TimerInterval(2) AND chip_comp/TimerInterval(1) AND NOT chip_comp/TCLKCounter(2) AND NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND NOT chip_comp/TCLKCounter(5) AND NOT chip_comp/TCLKCounter(6) AND NOT chip_comp/TCLKCounter(7) AND NOT chip_comp/TCLKCounter(8) AND NOT chip_comp/TCLKCounter(9) AND NOT chip_comp/TCLKCounter(10)) OR (NOT chip_comp/TimerInterval(2) AND NOT chip_comp/TimerInterval(0) AND NOT chip_comp/TimerInterval(1) AND NOT chip_comp/TCLKCounter(2) AND NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND NOT chip_comp/TCLKCounter(5) AND NOT chip_comp/TCLKCounter(6) AND NOT chip_comp/TCLKCounter(7) AND NOT chip_comp/TCLKCounter(8) AND NOT chip_comp/TCLKCounter(9) AND NOT chip_comp/TCLKCounter(10))); FTCPE_chip_comp/TCLKCounter3: FTCPE port map (chip_comp/TCLKCounter(3),chip_comp/TCLKCounter_T(3),CLK_40MHZ,POR,'0'); chip_comp/TCLKCounter_T(3) <= ((chip_comp/TCLKCounter(0)) OR (chip_comp/TCLKCounter(1)) OR (chip_comp/TCLKCounter(2)) OR (ACQENnB2sig(1).EXP) OR (chip_comp/TimerInterval(0) AND NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND NOT chip_comp/TCLKCounter(5) AND NOT chip_comp/TCLKCounter(6) AND NOT chip_comp/TCLKCounter(7) AND NOT chip_comp/TCLKCounter(8) AND NOT chip_comp/TCLKCounter(9) AND NOT chip_comp/TCLKCounter(10)) OR (NOT chip_comp/TimerInterval(2) AND NOT chip_comp/TimerInterval(1) AND NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND NOT chip_comp/TCLKCounter(5) AND NOT chip_comp/TCLKCounter(6) AND NOT chip_comp/TCLKCounter(7) AND NOT chip_comp/TCLKCounter(8) AND NOT chip_comp/TCLKCounter(9) AND NOT chip_comp/TCLKCounter(10))); FTCPE_chip_comp/TCLKCounter4: FTCPE port map (chip_comp/TCLKCounter(4),chip_comp/TCLKCounter_T(4),CLK_40MHZ,POR,'0'); chip_comp/TCLKCounter_T(4) <= ((chip_comp/TCLKCounter(0)) OR (chip_comp/TCLKCounter(1)) OR (chip_comp/TCLKCounter(2)) OR (chip_comp/TCLKCounter(3)) OR (chip_comp/TCLKCounter(0).EXP) OR (chip_comp/TimerInterval(0) AND NOT chip_comp/TCLKCounter(4) AND NOT chip_comp/TCLKCounter(5) AND NOT chip_comp/TCLKCounter(6) AND NOT chip_comp/TCLKCounter(7) AND NOT chip_comp/TCLKCounter(8) AND NOT chip_comp/TCLKCounter(9) AND NOT chip_comp/TCLKCounter(10))); FTCPE_chip_comp/TCLKCounter5: FTCPE port map (chip_comp/TCLKCounter(5),chip_comp/TCLKCounter_T(5),CLK_40MHZ,POR,'0'); chip_comp/TCLKCounter_T(5) <= ((TCLKsig.EXP) OR (ACLKsig.EXP) OR (NOT chip_comp/TCLKCounter(0) AND NOT chip_comp/TCLKCounter(1) AND NOT chip_comp/TCLKCounter(2) AND NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND chip_comp/TCLKCounter(5)) OR (NOT chip_comp/TCLKCounter(0) AND NOT chip_comp/TCLKCounter(1) AND NOT chip_comp/TCLKCounter(2) AND NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND chip_comp/TCLKCounter(6)) OR (NOT chip_comp/TCLKCounter(0) AND NOT chip_comp/TCLKCounter(1) AND NOT chip_comp/TCLKCounter(2) AND NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND chip_comp/TCLKCounter(7)) OR (NOT chip_comp/TCLKCounter(0) AND NOT chip_comp/TCLKCounter(1) AND NOT chip_comp/TCLKCounter(2) AND NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND chip_comp/TCLKCounter(8)) OR (NOT chip_comp/TCLKCounter(0) AND NOT chip_comp/TCLKCounter(1) AND NOT chip_comp/TCLKCounter(2) AND NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND chip_comp/TCLKCounter(9))); FTCPE_chip_comp/TCLKCounter6: FTCPE port map (chip_comp/TCLKCounter(6),chip_comp/TCLKCounter_T(6),CLK_40MHZ,POR,'0'); chip_comp/TCLKCounter_T(6) <= ((CLK_40MHZsig$BUF0.EXP) OR (NOT chip_comp/TCLKCounter(0) AND NOT chip_comp/TCLKCounter(1) AND NOT chip_comp/TCLKCounter(2) AND NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND NOT chip_comp/TCLKCounter(5) AND chip_comp/TCLKCounter(6)) OR (NOT chip_comp/TCLKCounter(0) AND NOT chip_comp/TCLKCounter(1) AND NOT chip_comp/TCLKCounter(2) AND NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND NOT chip_comp/TCLKCounter(5) AND chip_comp/TCLKCounter(7)) OR (NOT chip_comp/TCLKCounter(0) AND NOT chip_comp/TCLKCounter(1) AND NOT chip_comp/TCLKCounter(2) AND NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND NOT chip_comp/TCLKCounter(5) AND chip_comp/TCLKCounter(8)) OR (NOT chip_comp/TCLKCounter(0) AND NOT chip_comp/TCLKCounter(1) AND NOT chip_comp/TCLKCounter(2) AND NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND NOT chip_comp/TCLKCounter(5) AND chip_comp/TCLKCounter(9)) OR (NOT chip_comp/TCLKCounter(0) AND NOT chip_comp/TCLKCounter(1) AND NOT chip_comp/TCLKCounter(2) AND NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND NOT chip_comp/TCLKCounter(5) AND chip_comp/TCLKCounter(10))); FTCPE_chip_comp/TCLKCounter7: FTCPE port map (chip_comp/TCLKCounter(7),chip_comp/TCLKCounter_T(7),CLK_40MHZ,POR,'0'); chip_comp/TCLKCounter_T(7) <= ((ACQENnB3sig(1).EXP) OR (ACQENnB0sig(0).EXP) OR (NOT chip_comp/TCLKCounter(0) AND NOT chip_comp/TCLKCounter(1) AND NOT chip_comp/TCLKCounter(2) AND NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND NOT chip_comp/TCLKCounter(5) AND NOT chip_comp/TCLKCounter(6) AND chip_comp/TCLKCounter(7)) OR (NOT chip_comp/TCLKCounter(0) AND NOT chip_comp/TCLKCounter(1) AND NOT chip_comp/TCLKCounter(2) AND NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND NOT chip_comp/TCLKCounter(5) AND NOT chip_comp/TCLKCounter(6) AND chip_comp/TCLKCounter(8)) OR (NOT chip_comp/TCLKCounter(0) AND NOT chip_comp/TCLKCounter(1) AND NOT chip_comp/TCLKCounter(2) AND NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND NOT chip_comp/TCLKCounter(5) AND NOT chip_comp/TCLKCounter(6) AND chip_comp/TCLKCounter(9)) OR (NOT chip_comp/TCLKCounter(0) AND NOT chip_comp/TCLKCounter(1) AND NOT chip_comp/TCLKCounter(2) AND NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND NOT chip_comp/TCLKCounter(5) AND NOT chip_comp/TCLKCounter(6) AND chip_comp/TCLKCounter(10)) OR (NOT chip_comp/TimerInterval(2) AND chip_comp/TimerInterval(0) AND NOT chip_comp/TCLKCounter(0) AND NOT chip_comp/TCLKCounter(1) AND NOT chip_comp/TCLKCounter(2) AND NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND NOT chip_comp/TCLKCounter(5) AND NOT chip_comp/TCLKCounter(6))); FTCPE_chip_comp/TCLKCounter8: FTCPE port map (chip_comp/TCLKCounter(8),chip_comp/TCLKCounter_T(8),CLK_40MHZ,POR,'0'); chip_comp/TCLKCounter_T(8) <= ((NOT chip_comp/TCLKCounter(0) AND NOT chip_comp/TCLKCounter(1) AND NOT chip_comp/TCLKCounter(2) AND NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND NOT chip_comp/TCLKCounter(5) AND NOT chip_comp/TCLKCounter(6) AND NOT chip_comp/TCLKCounter(7) AND chip_comp/TCLKCounter(8)) OR (NOT chip_comp/TCLKCounter(0) AND NOT chip_comp/TCLKCounter(1) AND NOT chip_comp/TCLKCounter(2) AND NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND NOT chip_comp/TCLKCounter(5) AND NOT chip_comp/TCLKCounter(6) AND NOT chip_comp/TCLKCounter(7) AND chip_comp/TCLKCounter(9)) OR (NOT chip_comp/TCLKCounter(0) AND NOT chip_comp/TCLKCounter(1) AND NOT chip_comp/TCLKCounter(2) AND NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND NOT chip_comp/TCLKCounter(5) AND NOT chip_comp/TCLKCounter(6) AND NOT chip_comp/TCLKCounter(7) AND chip_comp/TCLKCounter(10)) OR (NOT chip_comp/TimerInterval(2) AND chip_comp/TimerInterval(1) AND NOT chip_comp/TCLKCounter(0) AND NOT chip_comp/TCLKCounter(1) AND NOT chip_comp/TCLKCounter(2) AND NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND NOT chip_comp/TCLKCounter(5) AND NOT chip_comp/TCLKCounter(6) AND NOT chip_comp/TCLKCounter(7)) OR (chip_comp/TimerInterval(2) AND NOT chip_comp/TimerInterval(0) AND NOT chip_comp/TimerInterval(1) AND NOT chip_comp/TCLKCounter(0) AND NOT chip_comp/TCLKCounter(1) AND NOT chip_comp/TCLKCounter(2) AND NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND NOT chip_comp/TCLKCounter(5) AND NOT chip_comp/TCLKCounter(6) AND NOT chip_comp/TCLKCounter(7))); FTCPE_chip_comp/TCLKCounter9: FTCPE port map (chip_comp/TCLKCounter(9),chip_comp/TCLKCounter_T(9),CLK_40MHZ,POR,'0'); chip_comp/TCLKCounter_T(9) <= ((NOT chip_comp/TCLKCounter(0) AND NOT chip_comp/TCLKCounter(1) AND NOT chip_comp/TCLKCounter(2) AND NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND NOT chip_comp/TCLKCounter(5) AND NOT chip_comp/TCLKCounter(6) AND NOT chip_comp/TCLKCounter(7) AND NOT chip_comp/TCLKCounter(8) AND chip_comp/TCLKCounter(9)) OR (NOT chip_comp/TCLKCounter(0) AND NOT chip_comp/TCLKCounter(1) AND NOT chip_comp/TCLKCounter(2) AND NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND NOT chip_comp/TCLKCounter(5) AND NOT chip_comp/TCLKCounter(6) AND NOT chip_comp/TCLKCounter(7) AND NOT chip_comp/TCLKCounter(8) AND chip_comp/TCLKCounter(10)) OR (chip_comp/TimerInterval(2) AND NOT chip_comp/TimerInterval(0) AND NOT chip_comp/TimerInterval(1) AND NOT chip_comp/TCLKCounter(0) AND NOT chip_comp/TCLKCounter(1) AND NOT chip_comp/TCLKCounter(2) AND NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND NOT chip_comp/TCLKCounter(5) AND NOT chip_comp/TCLKCounter(6) AND NOT chip_comp/TCLKCounter(7) AND NOT chip_comp/TCLKCounter(8)) OR (NOT chip_comp/TimerInterval(2) AND chip_comp/TimerInterval(0) AND chip_comp/TimerInterval(1) AND NOT chip_comp/TCLKCounter(0) AND NOT chip_comp/TCLKCounter(1) AND NOT chip_comp/TCLKCounter(2) AND NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND NOT chip_comp/TCLKCounter(5) AND NOT chip_comp/TCLKCounter(6) AND NOT chip_comp/TCLKCounter(7) AND NOT chip_comp/TCLKCounter(8))); FTCPE_chip_comp/TCLKCounter10: FTCPE port map (chip_comp/TCLKCounter(10),chip_comp/TCLKCounter_T(10),CLK_40MHZ,POR,'0'); chip_comp/TCLKCounter_T(10) <= ((NOT chip_comp/TCLKCounter(0) AND NOT chip_comp/TCLKCounter(1) AND NOT chip_comp/TCLKCounter(2) AND NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND NOT chip_comp/TCLKCounter(5) AND NOT chip_comp/TCLKCounter(6) AND NOT chip_comp/TCLKCounter(7) AND NOT chip_comp/TCLKCounter(8) AND NOT chip_comp/TCLKCounter(9) AND chip_comp/TCLKCounter(10)) OR (chip_comp/TimerInterval(2) AND NOT chip_comp/TimerInterval(0) AND NOT chip_comp/TimerInterval(1) AND NOT chip_comp/TCLKCounter(0) AND NOT chip_comp/TCLKCounter(1) AND NOT chip_comp/TCLKCounter(2) AND NOT chip_comp/TCLKCounter(3) AND NOT chip_comp/TCLKCounter(4) AND NOT chip_comp/TCLKCounter(5) AND NOT chip_comp/TCLKCounter(6) AND NOT chip_comp/TCLKCounter(7) AND NOT chip_comp/TCLKCounter(8) AND NOT chip_comp/TCLKCounter(9))); FDCPE_chip_comp/TCLKsig_1: FDCPE port map (chip_comp/TCLKsig_1,TCLK,CLK_40MHZ,POR,'0'); FDCPE_chip_comp/TXMAINSTATE_FFd1: FDCPE port map (chip_comp/TXMAINSTATE_FFd1,chip_comp/TXMAINSTATE_FFd1_D,CLK_40MHZ,POR,'0'); chip_comp/TXMAINSTATE_FFd1_D <= (NOT chip_comp/TXMAINSTATE_FFd1 AND NOT chip_comp/TXMAINSTATE_FFd2 AND chip_comp/CommandAvailable AND LOCKED AND CTRL_OK); FDCPE_chip_comp/TXMAINSTATE_FFd2: FDCPE port map (chip_comp/TXMAINSTATE_FFd2,chip_comp/TXMAINSTATE_FFd2_D,CLK_40MHZ,'0',POR); chip_comp/TXMAINSTATE_FFd2_D <= ((NOT chip_comp/TXMAINSTATE_FFd1 AND NOT LOCKED) OR (NOT chip_comp/TXMAINSTATE_FFd1 AND NOT CTRL_OK)); FTCPE_chip_comp/TXREADOUTSTATE_FFd1: FTCPE port map (chip_comp/TXREADOUTSTATE_FFd1,chip_comp/TXREADOUTSTATE_FFd1_T,CLK_40MHZ,POR,'0'); chip_comp/TXREADOUTSTATE_FFd1_T <= ((HFn_B(3) AND NOT chip_comp/TXREADOUTSTATE_FFd3 AND NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd1) OR (chip_comp/TXREADOUTSTATE_FFd3 AND NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND NOT chip_comp/TXREADOUTSTATE_FFd1) OR (chip_comp/TXREADOUTSTATE_FFd3 AND NOT chip_comp/TXREADOUTSTATE_FFd4 AND NOT chip_comp/TXREADOUTSTATE_FFd2 AND chip_comp/TXREADOUTSTATE_FFd1 AND chip_comp/GenDataDonesig)); FDCPE_chip_comp/TXREADOUTSTATE_FFd2: FDCPE port map (chip_comp/TXREADOUTSTATE_FFd2,chip_comp/TXREADOUTSTATE_FFd2_D,CLK_40MHZ,POR,'0'); chip_comp/TXREADOUTSTATE_FFd2_D <= ((RST4n_Bsig(0).EXP) OR (chip_comp/TXREADOUTSTATE_FFd3 AND chip_comp/TXREADOUTSTATE_FFd4) OR (NOT HFn_B(0) AND chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2) OR (NOT chip_comp/TXREADOUTSTATE_FFd3 AND NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND NOT chip_comp/GenDataDonesig)); FDCPE_chip_comp/TXREADOUTSTATE_FFd3: FDCPE port map (chip_comp/TXREADOUTSTATE_FFd3,chip_comp/TXREADOUTSTATE_FFd3_D,CLK_40MHZ,POR,'0'); chip_comp/TXREADOUTSTATE_FFd3_D <= ((chip_comp/TXREADOUTSTATE_FFd1.EXP) OR (chip_comp/TXREADOUTSTATE_FFd3 AND chip_comp/TXREADOUTSTATE_FFd4) OR (HFn_B(0) AND chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2) OR (chip_comp/TXREADOUTSTATE_FFd3 AND chip_comp/TXREADOUTSTATE_FFd1 AND NOT chip_comp/GenDataDonesig) OR (NOT chip_comp/TXREADOUTSTATE_FFd3 AND NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2 AND chip_comp/GenDataDonesig)); FDCPE_chip_comp/TXREADOUTSTATE_FFd4: FDCPE port map (chip_comp/TXREADOUTSTATE_FFd4,chip_comp/TXREADOUTSTATE_FFd4_D,CLK_40MHZ,POR,'0'); chip_comp/TXREADOUTSTATE_FFd4_D <= ((EXP35_.EXP) OR (chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd1 AND NOT chip_comp/GenDataDonesig) OR (NOT HFn_B(2) AND chip_comp/TXREADOUTSTATE_FFd3 AND NOT chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2) OR (HFn_B(0) AND NOT chip_comp/TXREADOUTSTATE_FFd3 AND chip_comp/TXREADOUTSTATE_FFd4 AND chip_comp/TXREADOUTSTATE_FFd2)); FDCPE_chip_comp/TimerInterval0: FDCPE port map (chip_comp/TimerInterval(0),chip_comp/CommandReceived(0),CLK_40MHZ,'0',POR,chip_comp/TimerInterval_CE(0)); chip_comp/TimerInterval_CE(0) <= (chip_comp/CommandReceived(10) AND NOT chip_comp/CommandReceived(13) AND NOT chip_comp/CommandReceived(14) AND chip_comp/CommandReceived(9) AND NOT chip_comp/CommandReceived(11) AND NOT chip_comp/CommandReceived(12) AND NOT chip_comp/CommandReceived(15) AND chip_comp/CommandReceived(8) AND chip_comp/TXMAINSTATE_FFd1); FDCPE_chip_comp/TimerInterval1: FDCPE port map (chip_comp/TimerInterval(1),chip_comp/CommandReceived(1),CLK_40MHZ,POR,'0',chip_comp/TimerInterval_CE(1)); chip_comp/TimerInterval_CE(1) <= (chip_comp/CommandReceived(10) AND NOT chip_comp/CommandReceived(13) AND NOT chip_comp/CommandReceived(14) AND chip_comp/CommandReceived(9) AND NOT chip_comp/CommandReceived(11) AND NOT chip_comp/CommandReceived(12) AND NOT chip_comp/CommandReceived(15) AND chip_comp/CommandReceived(8) AND chip_comp/TXMAINSTATE_FFd1); FDCPE_chip_comp/TimerInterval2: FDCPE port map (chip_comp/TimerInterval(2),chip_comp/CommandReceived(2),CLK_40MHZ,POR,'0',chip_comp/TimerInterval_CE(2)); chip_comp/TimerInterval_CE(2) <= (chip_comp/CommandReceived(10) AND NOT chip_comp/CommandReceived(13) AND NOT chip_comp/CommandReceived(14) AND chip_comp/CommandReceived(9) AND NOT chip_comp/CommandReceived(11) AND NOT chip_comp/CommandReceived(12) AND NOT chip_comp/CommandReceived(15) AND chip_comp/CommandReceived(8) AND chip_comp/TXMAINSTATE_FFd1); FTCPE_chip_comp/TimerRestCMD: FTCPE port map (chip_comp/TimerRestCMD,chip_comp/TimerRestCMD_T,CLK_40MHZ,'0',POR); chip_comp/TimerRestCMD_T <= ((NOT chip_comp/TXMAINSTATE_FFd1 AND NOT chip_comp/TXMAINSTATE_FFd2 AND chip_comp/TimerRestCMD) OR (chip_comp/CommandReceived(10) AND NOT chip_comp/CommandReceived(13) AND NOT chip_comp/CommandReceived(14) AND NOT chip_comp/CommandReceived(9) AND NOT chip_comp/CommandReceived(11) AND NOT chip_comp/CommandReceived(12) AND NOT chip_comp/CommandReceived(15) AND NOT chip_comp/CommandReceived(8) AND chip_comp/TXMAINSTATE_FFd1 AND NOT chip_comp/TimerRestCMD)); uD_OEn_B(0) <= '1'; uD_OEn_B(1) <= '1'; uD_OEn_B(2) <= '1'; uD_OEn_B(3) <= '1'; uDw(0) <= '0'; uDw(1) <= '0'; uDw(2) <= '0'; uDw(3) <= '0'; uDw(4) <= '0'; uDw(5) <= '0'; uDw(6) <= '0'; uDw(7) <= '0'; Register Legend: FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); ****************************** Device Pin Out ***************************** Device : XC95288XL-7-TQ144 Pin Signal Pin Signal No. Name No. Name 1 VCC 73 VCC 2 HFn_B<0> 74 D_OEn_B<3> 3 HFn_B<1> 75 RCLK4_B<3> 4 HFn_B<2> 76 DAC_LOADn 5 HFn_B<3> 77 DAC_DIN 6 KPR 78 DAC_SCLK 7 KPR 79 DAC_CSn_B<0> 8 VCC 80 DAC_CSn_B<1> 9 KPR 81 DAC_CSn_B<2> 10 KPR 82 DAC_CSn_B<3> 11 ACQENnB0<3> 83 KPR 12 ACQENnB1<3> 84 VCC 13 ACQENnB2<3> 85 ENABLEn_B<3> 14 ACQENnB3<3> 86 ENABLEn_B<2> 15 ACQENnB0<2> 87 ENABLEn_B<1> 16 ACQENnB1<2> 88 ENABLEn_B<0> 17 ACQENnB2<2> 89 GND 18 GND 90 GND 19 ACQENnB3<2> 91 CTRL_OK 20 ACQENnB0<1> 92 KPR 21 ACQENnB1<1> 93 LOCKED 22 ACQENnB2<1> 94 PT0 23 ACQENnB3<1> 95 PT1 24 ACQENnB0<0> 96 DR0 25 SYSCLK 97 DR1 26 TCLK 98 TMODE 27 ACLK 99 GND 28 RCLK3 100 ADCRST 29 GND 101 KPR 30 CLK_40MHZ 102 KPR 31 CTRL 103 KPR 32 KPR 104 KPR 33 ACQENnB1<0> 105 RESETn 34 ACQENnB2<0> 106 RST_TIMERn 35 ACQENnB3<0> 107 KPR 36 GND 108 GND 37 VCC 109 VCC 38 KPR 110 KPR 39 DATA<15> 111 KPR 40 DATA<14> 112 KPR 41 DATA<13> 113 KPR 42 VCC 114 GND 43 DATA<12> 115 KPR 44 DATA<11> 116 KPR 45 DATA<10> 117 KPR 46 DATA<9> 118 KPR 47 GND 119 uD_OEn_B<0> 48 DATA<8> 120 uD_OEn_B<1> 49 DATA<7> 121 uD_OEn_B<2> 50 DATA<6> 122 TDO 51 DATA<5> 123 GND 52 DATA<4> 124 uD_OEn_B<3> 53 DATA<3> 125 uDw<7> 54 DATA<2> 126 uDw<6> 55 VCC 127 VCC 56 DATA<1> 128 uDw<5> 57 DATA<0> 129 uDw<4> 58 RST4n_B<0> 130 uDw<3> 59 D_OEn_B<0> 131 uDw<2> 60 RCLK4_B<0> 132 uDw<1> 61 RST4n_B<1> 133 uDw<0> 62 GND 134 SYNCn 63 TDI 135 KPR 64 D_OEn_B<1> 136 KPR 65 TMS 137 KPR 66 RCLK4_B<1> 138 KPR 67 TCK 139 KPR 68 RST4n_B<2> 140 KPR 69 D_OEn_B<2> 141 VCC 70 RCLK4_B<2> 142 KPR 71 RST4n_B<3> 143 POR 72 GND 144 GND Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin TIE = Unused I/O floating -- must tie to VCC, GND or other signal KPR = Unused I/O with weak keeper (leave unconnected) VCC = Dedicated Power Pin GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc95288xl-7-TQ144 Optimization Method : SPEED Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : FAST Power Mode : STD Ground on Unused IOs : OFF Set I/O Pin Termination : KEEPER Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON Input Limit : 54 Pterm Limit : 25