<?xml version='1.0' encoding='utf-8' ?>
<!DOCTYPE ibis [
<!ELEMENT ibis (part, pin+)>
<!ELEMENT part EMPTY>
<!ELEMENT pin EMPTY>
<!ATTLIST part
  arch   CDATA #REQUIRED
  device CDATA #REQUIRED
  spg    CDATA #REQUIRED
  pkg    CDATA #REQUIRED>
<!ATTLIST pin
  nm     CDATA #REQUIRED
  no     CDATA #REQUIRED
  iostd  (TTL|LVTTL|LVCMOS2|NA) "NA"
  sr     (SLOW|FAST|slow|fast) "SLOW"
  dir    (BIDIR|bidir|INPUT|input|OUTPUT|output) "BIDIR">
]>
<ibis><part pkg="TQ144" spg="-7" arch="xc9500xl" device="XC95288XL"/><pin nm="CLK_40MHZ" no="30" dir="input"/><pin nm="POR" no="143" dir="input"/><pin nm="HFn_B&lt;3&gt;" no="5" dir="input"/><pin nm="HFn_B&lt;2&gt;" no="4" dir="input"/><pin nm="HFn_B&lt;1&gt;" no="3" dir="input"/><pin nm="HFn_B&lt;0&gt;" no="2" dir="input"/><pin nm="CTRL_OK" no="91" dir="input"/><pin nm="LOCKED" no="93" dir="input"/><pin nm="CTRL" no="31" dir="input"/><pin nm="ACLK" no="27" sr="slow" dir="output"/><pin nm="TCLK" no="26" sr="slow" dir="output"/><pin nm="ADCRST" no="100" sr="slow" dir="output"/><pin nm="DR0" no="96" sr="slow" dir="output"/><pin nm="DR1" no="97" sr="slow" dir="output"/><pin nm="PT0" no="94" sr="slow" dir="output"/><pin nm="PT1" no="95" sr="slow" dir="output"/><pin nm="TMODE" no="98" sr="slow" dir="output"/><pin nm="RCLK4_B&lt;3&gt;" no="75" sr="slow" dir="output"/><pin nm="RST4n_B&lt;0&gt;" no="58" sr="slow" dir="output"/><pin nm="RST4n_B&lt;1&gt;" no="61" sr="slow" dir="output"/><pin nm="RST4n_B&lt;2&gt;" no="68" sr="slow" dir="output"/><pin nm="RST4n_B&lt;3&gt;" no="71" sr="slow" dir="output"/><pin nm="DATA&lt;0&gt;" no="57" sr="slow" dir="output"/><pin nm="DATA&lt;10&gt;" no="45" sr="slow" dir="output"/><pin nm="DATA&lt;11&gt;" no="44" sr="slow" dir="output"/><pin nm="DATA&lt;12&gt;" no="43" sr="slow" dir="output"/><pin nm="DATA&lt;13&gt;" no="41" sr="slow" dir="output"/><pin nm="DATA&lt;14&gt;" no="40" sr="slow" dir="output"/><pin nm="DATA&lt;15&gt;" no="39" sr="slow" dir="output"/><pin nm="DATA&lt;1&gt;" no="56" sr="slow" dir="output"/><pin nm="DATA&lt;2&gt;" no="54" sr="slow" dir="output"/><pin nm="DATA&lt;3&gt;" no="53" sr="slow" dir="output"/><pin nm="DATA&lt;4&gt;" no="52" sr="slow" dir="output"/><pin nm="DATA&lt;5&gt;" no="51" sr="slow" dir="output"/><pin nm="DATA&lt;6&gt;" no="50" sr="slow" dir="output"/><pin nm="DATA&lt;7&gt;" no="49" sr="slow" dir="output"/><pin nm="DATA&lt;8&gt;" no="48" sr="slow" dir="output"/><pin nm="DATA&lt;9&gt;" no="46" sr="slow" dir="output"/><pin nm="ACQENnB0&lt;0&gt;" no="24" sr="slow" dir="output"/><pin nm="ACQENnB0&lt;1&gt;" no="20" sr="slow" dir="output"/><pin nm="ACQENnB0&lt;2&gt;" no="15" sr="slow" dir="output"/><pin nm="ACQENnB0&lt;3&gt;" no="11" sr="slow" dir="output"/><pin nm="ACQENnB1&lt;0&gt;" no="33" sr="slow" dir="output"/><pin nm="ACQENnB1&lt;1&gt;" no="21" sr="slow" dir="output"/><pin nm="ACQENnB1&lt;2&gt;" no="16" sr="slow" dir="output"/><pin nm="ACQENnB1&lt;3&gt;" no="12" sr="slow" dir="output"/><pin nm="ACQENnB2&lt;0&gt;" no="34" sr="slow" dir="output"/><pin nm="ACQENnB2&lt;1&gt;" no="22" sr="slow" dir="output"/><pin nm="ACQENnB2&lt;2&gt;" no="17" sr="slow" dir="output"/><pin nm="ACQENnB2&lt;3&gt;" no="13" sr="slow" dir="output"/><pin nm="ACQENnB3&lt;0&gt;" no="35" sr="slow" dir="output"/><pin nm="ACQENnB3&lt;1&gt;" no="23" sr="slow" dir="output"/><pin nm="ACQENnB3&lt;2&gt;" no="19" sr="slow" dir="output"/><pin nm="ACQENnB3&lt;3&gt;" no="14" sr="slow" dir="output"/><pin nm="D_OEn_B&lt;0&gt;" no="59" sr="slow" dir="output"/><pin nm="D_OEn_B&lt;1&gt;" no="64" sr="slow" dir="output"/><pin nm="D_OEn_B&lt;2&gt;" no="69" sr="slow" dir="output"/><pin nm="D_OEn_B&lt;3&gt;" no="74" sr="slow" dir="output"/><pin nm="ENABLEn_B&lt;0&gt;" no="88" sr="slow" dir="output"/><pin nm="ENABLEn_B&lt;1&gt;" no="87" sr="slow" dir="output"/><pin nm="ENABLEn_B&lt;2&gt;" no="86" sr="slow" dir="output"/><pin nm="ENABLEn_B&lt;3&gt;" no="85" sr="slow" dir="output"/><pin nm="SYNCn" no="134" sr="slow" dir="output"/><pin nm="SYSCLK" no="25" sr="slow" dir="output"/><pin nm="RCLK3" no="28" sr="slow" dir="output"/><pin nm="RCLK4_B&lt;2&gt;" no="70" sr="slow" dir="output"/><pin nm="RCLK4_B&lt;1&gt;" no="66" sr="slow" dir="output"/><pin nm="RCLK4_B&lt;0&gt;" no="60" sr="slow" dir="output"/><pin nm="RESETn" no="105" sr="slow" dir="output"/><pin nm="RST_TIMERn" no="106" sr="slow" dir="output"/><pin nm="uD_OEn_B&lt;3&gt;" no="124" sr="slow" dir="output"/><pin nm="uD_OEn_B&lt;2&gt;" no="121" sr="slow" dir="output"/><pin nm="uD_OEn_B&lt;1&gt;" no="120" sr="slow" dir="output"/><pin nm="uD_OEn_B&lt;0&gt;" no="119" sr="slow" dir="output"/><pin nm="DAC_CSn_B&lt;3&gt;" no="82" sr="slow" dir="output"/><pin nm="DAC_CSn_B&lt;2&gt;" no="81" sr="slow" dir="output"/><pin nm="DAC_CSn_B&lt;1&gt;" no="80" sr="slow" dir="output"/><pin nm="DAC_CSn_B&lt;0&gt;" no="79" sr="slow" dir="output"/><pin nm="uDw&lt;7&gt;" no="125" sr="slow" dir="output"/><pin nm="uDw&lt;6&gt;" no="126" sr="slow" dir="output"/><pin nm="uDw&lt;5&gt;" no="128" sr="slow" dir="output"/><pin nm="uDw&lt;4&gt;" no="129" sr="slow" dir="output"/><pin nm="uDw&lt;3&gt;" no="130" sr="slow" dir="output"/><pin nm="uDw&lt;2&gt;" no="131" sr="slow" dir="output"/><pin nm="uDw&lt;1&gt;" no="132" sr="slow" dir="output"/><pin nm="uDw&lt;0&gt;" no="133" sr="slow" dir="output"/><pin nm="DAC_SCLK" no="78" sr="slow" dir="output"/><pin nm="DAC_LOADn" no="76" sr="slow" dir="output"/><pin nm="DAC_DIN" no="77" sr="slow" dir="output"/></ibis>
