---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 11:06:05 02/01/2007 -- Design Name: -- Module Name: chip - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity chip is Port ( RST : in STD_LOGIC; --POR : in STD_LOGIC; -- RESET CLK : in STD_LOGIC; --CLK_40MHZ : in STD_LOGIC; --Main clock CLK_OK : in STD_LOGIC; --CLK_40MHZ_OK: in STD_LOGIC; --Status of main clock link --Control link CTRL : in STD_LOGIC; --Serial input for Control data CTRL_OK : in STD_LOGIC; --Status of the Control link --GLINK signals LOCKED : in STD_LOGIC; --PLL of the GLINK is locked DATA : out STD_LOGIC_VECTOR(15 downto 0); -- Data that will be transmitted DATA_TS : out STD_LOGIC; -- TS signal for Data (internal to CPLD) SYNCn : out STD_LOGIC; -- when high GLINK will send data, when low GLINK will send IDLE words --Channel and mother board RESETn : out STD_LOGIC; -- main reset TCLK : out STD_LOGIC; -- --Mother board signals SYSCLK : out STD_LOGIC; -- 40MHz clock for all boards ENABLEn_B : out STD_LOGIC_VECTOR( 3 downto 0); -- enable the board RST_TIMERn : out STD_LOGIC; -- reset timers RST4n_B : out STD_LOGIC_VECTOR( 3 downto 0); -- Mother board FIFO reset RCLK4_B : out STD_LOGIC_VECTOR( 3 downto 0); -- Mother board FIFO read clock HFn_B : in STD_LOGIC_VECTOR( 3 downto 0); -- Mother board FIFO Half full FFn_B : in STD_LOGIC_VECTOR( 3 downto 0); -- Mother board FIFO Fifo full D_OEn_B : out STD_LOGIC_VECTOR( 3 downto 0); -- Enable Driver in the TX board to read a given board DAC_LOADn : out STD_LOGIC; -- DAC signals DAC_DIN : out STD_LOGIC; -- DAC signals DAC_SCLK : out STD_LOGIC; -- DAC signals DAC_CSn_B : out STD_LOGIC_VECTOR( 3 downto 0); -- DAC signals --Channel signals ACQENnB0 : out STD_LOGIC_VECTOR( 3 downto 0); -- Enabel channels in the mother board 0 ACQENnB1 : out STD_LOGIC_VECTOR( 3 downto 0); -- Enabel channels in the mother board 1 ACQENnB2 : out STD_LOGIC_VECTOR( 3 downto 0); -- Enabel channels in the mother board 2 ACQENnB3 : out STD_LOGIC_VECTOR( 3 downto 0); -- Enabel channels in the mother board 3 ACLK : out STD_LOGIC; -- Sampling clock that is programable RCLK3 : out STD_LOGIC; -- Read clock FIFO 3 ADCRST : out STD_LOGIC; -- ADC reset TMODE : out STD_LOGIC; -- Trigger Mode DR0 : out STD_LOGIC; -- Decimation ratio DR1 : out STD_LOGIC; -- Decimation ratio PT0 : out STD_LOGIC; -- Pre trigger PT1 : out STD_LOGIC; -- Pre trigger uD_OEn_B : out STD_LOGIC_VECTOR( 3 downto 0); -- uDw : out STD_LOGIC_VECTOR( 7 downto 0); -- uDr : in STD_LOGIC_VECTOR( 7 downto 0) -- ); end chip; architecture Behavioral of chip is --------------------------------------------------- -- Component Declaration -- --------------------------------------------------- component ReceiveCommand is Port ( rst : in STD_LOGIC; clk : in STD_LOGIC; ser_in : in STD_LOGIC; command_out : out STD_LOGIC_VECTOR (15 downto 0); dav : out STD_LOGIC ); end component; --------------------------------------------------- -- Signal Declaration -- --------------------------------------------------- type TXMAINSTATE_TYPE is (IDLE, NOLINKST, COMMANDRECEIVEDST); type TXREADOUTSTATE_TYPE is (IDLE, GENDATACMDST, GENDATAST, Reset_B0_ST, SENDDATA_B0_ST, Reset_B1_ST, SENDDATA_B1_ST, Reset_B2_ST, SENDDATA_B2_ST, Reset_B3_ST, SENDDATA_B3_ST); signal TXMAINSTATE : TXMAINSTATE_TYPE; signal TXREADOUTSTATE : TXREADOUTSTATE_TYPE; signal Busy : STD_LOGIC; -- SM is busy signal LinkStablished : STD_LOGIC; -- SM is busy signal DataPackageSize : STD_LOGIC_VECTOR (15 downto 0); --size of the data package, typically 4096 words signal RunningFlag : STD_LOGIC; -- SM is busy --Signals used for the optical link signal CommandReceived : STD_LOGIC_VECTOR (15 downto 0); signal CommandAvailable : STD_LOGIC; signal Datasig : STD_LOGIC_VECTOR (15 downto 0); signal SYNCnsig : STD_LOGIC; --Signals used to generate the simulated data signal GenDataCMD : STD_LOGIC; -- Tells the SM that it needs to generate a set of simulated data signal GenDatasig : STD_LOGIC; -- Tells the Simulated Data Generator to start working signal GenDataDonesig : STD_LOGIC; -- Flags when the data was completed generated signal SimulData : STD_LOGIC_VECTOR(15 downto 0); -- contains the simulated data signal GenDataCounter : STD_LOGIC_VECTOR(15 downto 0); -- couter needed to generate the simulated data --Signals used for ACLK signal ACLKCounter : STD_LOGIC_VECTOR(8 downto 0); -- signal ACLKsig : STD_LOGIC; -- --Signals used for AReset signal ACLKsig_1 : STD_LOGIC; -- signal ADCRestCMD : STD_LOGIC; -- signal ADCRSTsig : STD_LOGIC; -- --Signals used for TCLK signal TCLKCounter : STD_LOGIC_VECTOR(10 downto 0); -- signal TCLKsig : STD_LOGIC; -- --Signals used for TReset signal TCLKsig_1 : STD_LOGIC; -- signal TimerRestCMD : STD_LOGIC; -- signal RST_TIMERnsig : STD_LOGIC; -- --Signals to read from mother boards signal RST4n_Bsig : STD_LOGIC_VECTOR( 3 downto 0); -- signal HasDataFlag : STD_LOGIC; -- signal HFn_Bsig : STD_LOGIC_VECTOR( 3 downto 0); -- --registers signal TriggerMode : STD_LOGIC; -- signal DecimationRatio : STD_LOGIC_VECTOR (1 downto 0); -- signal PreTriggerData : STD_LOGIC_VECTOR (1 downto 0); -- signal SamplingClock : STD_LOGIC_VECTOR (1 downto 0); -- signal TimerInterval : STD_LOGIC_VECTOR (2 downto 0); -- --Register used for enable signal ACQENnB0Reg : STD_LOGIC_VECTOR( 3 downto 0); -- Enabel channels in the mother board 0 signal ACQENnB1Reg : STD_LOGIC_VECTOR( 3 downto 0); -- Enabel channels in the mother board 1 signal ACQENnB2Reg : STD_LOGIC_VECTOR( 3 downto 0); -- Enabel channels in the mother board 2 signal ACQENnB3Reg : STD_LOGIC_VECTOR( 3 downto 0); -- Enabel channels in the mother board 3 signal ENABLEn_BReg : STD_LOGIC_VECTOR( 3 downto 0); -- Enabel channels in the mother board 3 -- Signals used to enable the data package to be sent over the optical link only if there is space at the RX FIFO signal DataPackageTXEn : STD_LOGIC; -- --signal DataPackageLoad : STD_LOGIC; -- --signal DataPackageSub : STD_LOGIC; -- --signal DataPackageCount : STD_LOGIC_VECTOR( 3 downto 0); -- -- Signals to read the status of the board signal StatusDataSel : STD_LOGIC_VECTOR(4 downto 0); -- signal StatusDataB0CH0 : STD_LOGIC_VECTOR(15 downto 0); -- signal StatusDataB0CH1 : STD_LOGIC_VECTOR(15 downto 0); -- signal StatusDataB0CH2 : STD_LOGIC_VECTOR(15 downto 0); -- signal StatusDataB0CH3 : STD_LOGIC_VECTOR(15 downto 0); -- signal StatusDataB1CH0 : STD_LOGIC_VECTOR(15 downto 0); -- signal StatusDataB1CH1 : STD_LOGIC_VECTOR(15 downto 0); -- signal StatusDataB1CH2 : STD_LOGIC_VECTOR(15 downto 0); -- signal StatusDataB1CH3 : STD_LOGIC_VECTOR(15 downto 0); -- signal StatusDataB2CH0 : STD_LOGIC_VECTOR(15 downto 0); -- signal StatusDataB2CH1 : STD_LOGIC_VECTOR(15 downto 0); -- signal StatusDataB2CH2 : STD_LOGIC_VECTOR(15 downto 0); -- signal StatusDataB2CH3 : STD_LOGIC_VECTOR(15 downto 0); -- signal StatusDataB3CH0 : STD_LOGIC_VECTOR(15 downto 0); -- signal StatusDataB3CH1 : STD_LOGIC_VECTOR(15 downto 0); -- signal StatusDataB3CH2 : STD_LOGIC_VECTOR(15 downto 0); -- signal StatusDataB3CH3 : STD_LOGIC_VECTOR(15 downto 0); -- begin -- DAC data not used now DAC_LOADn <= '0'; DAC_DIN <= '0'; DAC_SCLK <= '0'; DAC_CSn_B <= (others => '1');-- do not select any DAC uD_OEn_B <= (others => '1');-- do not select any user defined data uDw <= (others => '0');-- --GLINK DATA and sync command DATA <= SimulData when ((TXREADOUTSTATE = GENDATAST)) else --(TXMAINSTATE = GENDATACMDST)or Datasig; SYNCn <= SYNCnsig; ADCRST <= ADCRSTsig; TCLK <= TCLKsig; SYSCLK <= CLK; RCLK3 <= CLK; ACLK <= ACLKsig; TMODE <= TriggerMode; DR0 <= DecimationRatio(0); DR1 <= DecimationRatio(1); PT0 <= PreTriggerData(0); PT1 <= PreTriggerData(1); RST4n_B <= RST4n_Bsig; --RST4n_B <= "0000"; -- these signals are actually REN4n and they need to be zero all the time. --ADCRestCMD <= not RunningFlag;--when the system is stopped the ADC are reseted RESETn <= not RST; RST_TIMERn <= not RST_TIMERnsig; HasDataFlag <= ( (not HFn_B(0)) or (not HFn_B(1)) or (not HFn_B(2)) or (not HFn_B(3)) );-- and DataPackageTXEn; RCLK4_B(0) <= CLK when ((TXREADOUTSTATE = SENDDATA_B3_ST)) else --(TXMAINSTATE = GENDATACMDST)or '1'; RCLK4_B(1) <= CLK when ((TXREADOUTSTATE = SENDDATA_B3_ST)) else --(TXMAINSTATE = GENDATACMDST)or '1'; RCLK4_B(2) <= CLK when ((TXREADOUTSTATE = SENDDATA_B3_ST)) else --(TXMAINSTATE = GENDATACMDST)or '1'; RCLK4_B(3) <= CLK when ((TXREADOUTSTATE = SENDDATA_B3_ST)) else --(TXMAINSTATE = GENDATACMDST)or '1'; DataPackageSize <= x"1001"; -- 4096 adding 1 to AAAA ----------------------------------------------------------------------------------- --Main state machine used to receive commands from the CTRL link and -- --set all the internal registers -- ----------------------------------------------------------------------------------- TXMAINSMproc : process (RST, CLK, TXMAINSTATE, CTRL_OK, LOCKED, CommandAvailable) begin if (rst = '1') then --register initialization TriggerMode <= '0'; DecimationRatio <= "00"; PreTriggerData <= "00"; ACQENnB0Reg <= "0000"; ACQENnB1Reg <= "0000"; ACQENnB2Reg <= "0000"; ACQENnB3Reg <= "0000"; ENABLEn_BReg <= "0000"; TimerInterval <= "001"; SamplingClock <= "00"; RunningFlag <= '0'; -- the system start in a stop mode. Busy <= '0'; LinkStablished <= '0'; GenDataCMD <= '0'; TimerRestCMD <= '1'; ADCRestCMD <= '1'; SYNCnsig <= '0'; DataPackageTXEn <= '0'; StatusDataSel <= (others => '0'); --next state logic TXMAINSTATE <= NOLINKST; elsif (clk'event and clk = '1') then case (TXMAINSTATE) is when NOLINKST => Busy <= '0'; SYNCnsig <= '0'; LinkStablished <= '0'; --next state logic if (CTRL_OK = '1' and LOCKED = '1') then TXMAINSTATE <= IDLE; end if; when COMMANDRECEIVEDST => Busy <= '1'; SYNCnsig <= '1'; if (CommandReceived(15 downto 8) = x"67") then GenDataCMD <= '1'; elsif (CommandReceived(15 downto 8) = x"01") then -- enable command if (RunningFlag = '0') then -- changes the enable only if the bard is not running if (CommandReceived(7 downto 4) = x"0") then -- enable channels in board 0 ACQENnB0Reg <= CommandReceived(3 downto 0); elsif (CommandReceived(7 downto 4) = x"1") then -- enable channels in board 1 ACQENnB1Reg <= CommandReceived(3 downto 0); elsif (CommandReceived(7 downto 4) = x"2") then -- enable channels in board 2 ACQENnB2Reg <= CommandReceived(3 downto 0); elsif (CommandReceived(7 downto 4) = x"3") then -- enable channels in board 3 ACQENnB3Reg <= CommandReceived(3 downto 0); elsif (CommandReceived(7 downto 4) = x"4") then -- enable boards ENABLEn_BReg <= CommandReceived(3 downto 0); end if; end if; elsif (CommandReceived(15 downto 8) = x"02") then -- start command RunningFlag <= '1'; elsif (CommandReceived(15 downto 8) = x"03") then -- stop command RunningFlag <= '0'; elsif (CommandReceived(15 downto 8) = x"04") then -- reset_timer command TimerRestCMD <= '1'; elsif (CommandReceived(15 downto 8) = x"07") then -- timer interval command TimerInterval <= CommandReceived(2 downto 0); elsif (CommandReceived(15 downto 8) = x"08") then -- timer source command elsif (CommandReceived(15 downto 8) = x"09") then -- sampling clock command SamplingClock <= CommandReceived(1 downto 0); elsif (CommandReceived(15 downto 8) = x"0A") then -- Decimation command DecimationRatio <= CommandReceived(1 downto 0); elsif (CommandReceived(15 downto 8) = x"0B") then -- Trigger sample command PreTriggerData <= CommandReceived(1 downto 0); elsif (CommandReceived(15 downto 8) = x"0C") then -- status command StatusDataSel <= CommandReceived(4 downto 0); elsif (CommandReceived(15 downto 8) = x"0D") then -- Trigger Mode command TriggerMode <= CommandReceived(0); elsif (CommandReceived(15 downto 8) = x"69") then -- status from the RX board DataPackageTXEn <= CommandReceived(0); end if; --next state logic TXMAINSTATE <= IDLE; when others => Busy <= '0'; LinkStablished <= '1'; GenDataCMD <= '0'; ADCRestCMD <= '0'; TimerRestCMD <= '0'; SYNCnsig <= '1'; --next state logic if (CTRL_OK = '0' or LOCKED = '0') then TXMAINSTATE <= NOLINKST; elsif (CommandAvailable = '1') then --Command received through the CTRL fiber optic link TXMAINSTATE <= COMMANDRECEIVEDST; end if; end case; end if; end process; ----------------------------------------------------------------------------------- --State machine used to send the data packages from the mother boards to the -- --RX board throgh the optical link (GNLINK) -- ----------------------------------------------------------------------------------- TXREADOUTSMproc : process (RST, CLK, TXREADOUTSTATE, GenDataCMD, LinkStablished, StatusDataSel) begin if (rst = '1') then DATAsig <= x"0000"; DATA_TS <= '1'; -- data is tri-stated D_OEn_B <= "1111"; -- All mother boards outputdata buffer are High Z RST4n_Bsig <= "0000"; -- reset mode GenDatasig <= '0'; HFn_Bsig <= (others => '0'); --DataPackageSub <= '0'; --next state logic TXREADOUTSTATE <= IDLE; elsif (clk'event and clk = '1') then case (TXREADOUTSTATE) is when GENDATACMDST =>-- starts generating simulated data DATAsig <= x"AAAA"; DATA_TS <= '0'; -- data is not tri-stated D_OEn_B <= "1111"; -- All mother boards outputdata buffer are High Z GenDatasig <= '1'; TXREADOUTSTATE <= GENDATAST; when GENDATAST => --stays here until all simulated data is generated DATAsig <= x"0000"; DATA_TS <= '0'; -- data is not tri-stated D_OEn_B <= "1111"; -- All mother boards outputdata buffer are High Z GenDatasig <= '1'; if (GenDataDonesig = '1') then TXREADOUTSTATE <= IDLE; else TXREADOUTSTATE <= TXREADOUTSTATE; end if; when Reset_B0_ST =>-- resets the couter needed to readout data and verify if there is data to be readout in this board DATAsig <= DATAsig; DATA_TS <= '0'; -- data is not tri-stated D_OEn_B <= "1111"; -- All mother boards outputdata buffer are High Z GenDatasig <= '0'; if (HFn_B(0) = '1') then -- if there is no data to readout in this board goes to the next one TXREADOUTSTATE <= Reset_B1_ST; -- else DATAsig <= x"AAAA"; DATA_TS <= '0'; -- data is NOT tri-stated GenDatasig <= '1'; --DataPackageSub <= '1'; TXREADOUTSTATE <= SENDDATA_B0_ST; end if; when SENDDATA_B0_ST => --stays here until all simulated data is generated DATAsig <= (others => '0'); DATA_TS <= '1'; -- data is tri-stated D_OEn_B <= "1110"; -- All mother boards outputdata buffer are High Z GenDatasig <= '1'; --DataPackageSub <= '0'; if (GenDataDonesig = '1') then TXREADOUTSTATE <= Reset_B1_ST; end if; when Reset_B1_ST =>-- resets the couter needed to readout data and verify if there is data to be readout in this board DATAsig <= DATAsig; DATA_TS <= '0'; -- data is not tri-stated D_OEn_B <= "1111"; -- All mother boards outputdata buffer are High Z GenDatasig <= '0'; if (HFn_B(1) = '1') then -- if there is no data to readout in this board goes to the next one TXREADOUTSTATE <= Reset_B2_ST; -- else DATAsig <= x"AAAA"; DATA_TS <= '0'; -- data is NOT tri-stated GenDatasig <= '1'; --DataPackageSub <= '1'; TXREADOUTSTATE <= SENDDATA_B1_ST; end if; when SENDDATA_B1_ST => --stays here until all simulated data is generated DATAsig <= (others => '0'); DATA_TS <= '1'; -- data is tri-stated D_OEn_B <= "1101"; -- All mother boards outputdata buffer are High Z GenDatasig <= '1'; --DataPackageSub <= '0'; if (GenDataDonesig = '1') then TXREADOUTSTATE <= Reset_B2_ST; end if; when Reset_B2_ST =>-- resets the couter needed to readout data and verify if there is data to be readout in this board DATAsig <= DATAsig; DATA_TS <= '0'; -- data is not tri-stated D_OEn_B <= "1111"; -- All mother boards outputdata buffer are High Z GenDatasig <= '0'; if (HFn_B(2) = '1') then -- if there is no data to readout in this board goes to the next one TXREADOUTSTATE <= Reset_B3_ST; -- else DATAsig <= x"AAAA"; DATA_TS <= '0'; -- data is NOT tri-stated GenDatasig <= '1'; --DataPackageSub <= '1'; TXREADOUTSTATE <= SENDDATA_B2_ST; end if; when SENDDATA_B2_ST => --stays here until all simulated data is generated DATAsig <= (others => '0'); DATA_TS <= '1'; -- data is tri-stated D_OEn_B <= "1011"; -- All mother boards outputdata buffer are High Z GenDatasig <= '1'; --DataPackageSub <= '0'; if (GenDataDonesig = '1') then TXREADOUTSTATE <= Reset_B3_ST; end if; when Reset_B3_ST =>-- resets the couter needed to readout data and verify if there is data to be readout in this board DATAsig <= DATAsig; DATA_TS <= '0'; -- data is not tri-stated D_OEn_B <= "1111"; -- All mother boards outputdata buffer are High Z GenDatasig <= '0'; if (HFn_B(3) = '1') then -- if there is no data to readout in this board goes to the next one TXREADOUTSTATE <= IDLE; -- else DATAsig <= x"AAAA"; DATA_TS <= '0'; -- data is NOT tri-stated GenDatasig <= '1'; --DataPackageSub <= '1'; TXREADOUTSTATE <= SENDDATA_B3_ST; end if; when SENDDATA_B3_ST => --stays here until all simulated data is generated DATAsig <= (others => '0'); DATA_TS <= '1'; -- data is tri-stated D_OEn_B <= "0111"; -- All mother boards outputdata buffer are High Z GenDatasig <= '1'; --DataPackageSub <= '0'; if (GenDataDonesig = '1') then TXREADOUTSTATE <= IDLE; end if; --when => --next state logic -- if (CTRL_OK = '1' and LOCKED = '1') then -- TXREADOUTSTATE <= IDLE; -- end if; when others => --IDLE (send status word) HFn_Bsig <= HFn_B; --Select which data will be sent back throgh the Glink while in IDLE if (StatusDataSel = "00000") then DATAsig(15) <= '0'; DATAsig(14 downto 10) <= StatusDataSel; --DATAsig(14 downto 13) <= PreTriggerData; --DATAsig(12) <= TriggerMode; --DATAsig(11 downto 10) <= DecimationRatio; --DATAsig( 9 downto 8) <= SamplingClock; --DATAsig(7) <= '0'; --DATAsig(6 downto 4) <= TimerInterval; DATAsig(3 downto 0) <= ACQENnB0Reg; elsif (StatusDataSel = "00001") then DATAsig(15) <= '0'; DATAsig(14 downto 10) <= StatusDataSel; --DATAsig(14 downto 13) <= PreTriggerData; --DATAsig(12) <= TriggerMode; --DATAsig(11 downto 10) <= DecimationRatio; --DATAsig( 9 downto 8) <= SamplingClock; --DATAsig(7) <= '0'; --DATAsig(6 downto 4) <= TimerInterval; DATAsig(3 downto 0) <= ACQENnB1Reg; elsif (StatusDataSel = "00010") then DATAsig(15) <= '0'; DATAsig(14 downto 10) <= StatusDataSel; --DATAsig(14 downto 13) <= PreTriggerData; --DATAsig(12) <= TriggerMode; --DATAsig(11 downto 10) <= DecimationRatio; --DATAsig( 9 downto 8) <= SamplingClock; --DATAsig(7) <= '0'; --DATAsig(6 downto 4) <= TimerInterval; DATAsig(3 downto 0) <= ACQENnB2Reg; elsif (StatusDataSel = "00011") then DATAsig(15) <= '0'; DATAsig(14 downto 10) <= StatusDataSel; --DATAsig(14 downto 13) <= PreTriggerData; --DATAsig(12) <= TriggerMode; --DATAsig(11 downto 10) <= DecimationRatio; --DATAsig( 9 downto 8) <= SamplingClock; --DATAsig(7) <= '0'; --DATAsig(6 downto 4) <= TimerInterval; DATAsig(3 downto 0) <= ACQENnB3Reg; elsif (StatusDataSel = "00100") then DATAsig(15) <= '0'; DATAsig(14 downto 10) <= StatusDataSel; --DATAsig(14 downto 13) <= PreTriggerData; --DATAsig(12) <= TriggerMode; --DATAsig( 9 downto 8) <= DecimationRatio; DATAsig( 9) <= '0'; DATAsig( 8 downto 7) <= SamplingClock; DATAsig( 6 downto 4) <= TimerInterval; DATAsig( 3 downto 0) <= ENABLEn_BReg; else DATAsig(15) <= '0'; DATAsig(14 downto 10) <= StatusDataSel; DATAsig( 9 downto 8) <= PreTriggerData; DATAsig( 7) <= TriggerMode; DATAsig(6 downto 5) <= DecimationRatio; --DATAsig( 9 downto 8) <= SamplingClock; DATAsig(4) <= '0'; --DATAsig(6 downto 4) <= TimerInterval; DATAsig(3 downto 0) <= ENABLEn_BReg; end if; DATA_TS <= '0'; -- data is not tri-stated D_OEn_B <= "1111"; -- All mother boards outputdata buffer are High Z RST4n_Bsig <= "1111";--normal operation mode GenDatasig <= '0'; --DataPackageSub <= '0'; --next state logic if(LinkStablished = '1') then if (GenDataCMD = '1') then DATAsig <= x"AAAA"; DATA_TS <= '0'; -- data is not tri-stated D_OEn_B <= "1111"; -- All mother boards outputdata buffer are High Z --GenDatasig <= '1'; --next state logic TXREADOUTSTATE <= GENDATACMDST; elsif (HasDataFlag = '1' and DataPackageTXEn = '1') then --next state logic TXREADOUTSTATE <= Reset_B0_ST; end if; end if; end case; end if; end process; ----------------------------------------------------------------------------------- --Process that generates ADC clock Aclk ----------------------------------------------------------------------------------- ACLKComp : process (rst, clk, SamplingClock) begin if (rst = '1') then ACLKCounter <= (others => '0'); ACLKsig <= '0';-- the clock signal start with elsif (clk'event and clk = '1') then --Count up with auto reload if(ACLKCounter = "000000000") then if (SamplingClock = "00") then ACLKCounter <= "000100111";-- 2 micro seconds elsif (SamplingClock = "01") then ACLKCounter <= "001001111";-- 4 micro seconds elsif (SamplingClock = "10") then ACLKCounter <= "010011111";-- 8 micro seconds else ACLKCounter <= "100111111";-- 16 micro seconds end if; else ACLKCounter <= ACLKCounter - 1;--increment counter end if; --Change clock state if(ACLKCounter = "000000000") then ACLKsig <= not ACLKsig; end if; end if; end process; ----------------------------------------------------------------------------------- --Process that generates ADC reset ----------------------------------------------------------------------------------- ADCResetComp : process (rst, clk, ACLKsig, ACLKsig_1, ADCRSTsig) begin if (rst = '1') then ACLKsig_1 <= '0';-- the clock signal start with ADCRSTsig <= '1'; elsif (clk'event and clk = '1') then --pipeline ACLKsig ACLKsig_1 <= ACLKsig; --ADCRST chage state logic if(ADCRestCMD = '1')then ADCRSTsig <= '1'; elsif (ACLKsig_1 = '0' and ACLKsig = '1' and ADCRSTsig = '1' and ADCRestCMD = '0') then ADCRSTsig <= '0'; end if; end if; end process; ----------------------------------------------------------------------------------- --Process that generates Timer clock Tclk ----------------------------------------------------------------------------------- TCLKComp : process (rst, clk, TimerInterval) begin if (rst = '1') then TCLKCounter <= (others => '0'); TCLKsig <= '0';-- the clock signal start with elsif (clk'event and clk = '1') then --Count up with auto reload if(TCLKCounter = "00000000000") then if (TimerInterval = "000") then TCLKCounter <= "00000010011";-- 1 micro seconds elsif (TimerInterval = "001") then TCLKCounter <= "00011000111";-- 10 micro seconds elsif (TimerInterval = "010") then TCLKCounter <= "00110001111";-- 20 micro seconds elsif (TimerInterval = "011") then TCLKCounter <= "01111100111";-- 50 micro seconds elsif (TimerInterval = "100") then TCLKCounter <= "11111001111";-- 100 micro seconds else TCLKCounter <= TCLKCounter; -- doesn't change end if; else TCLKCounter <= TCLKCounter - 1;--increment counter end if; --Change clock state if(TCLKCounter = "0000000000") then TCLKsig <= not TCLKsig; end if; end if; end process; ----------------------------------------------------------------------------------- --Process that generates Timer reset ----------------------------------------------------------------------------------- TimerResetComp : process (rst, clk, TCLKsig, TCLKsig_1, TimerRestCMD) begin if (rst = '1') then TCLKsig_1 <= '0';-- the clock signal start with RST_TIMERnsig <= '1'; elsif (clk'event and clk = '1') then --pipeline ACLKsig TCLKsig_1 <= TCLKsig; --ADCRST chage state logic if(TimerRestCMD = '1')then RST_TIMERnsig <= '1'; elsif (TCLKsig_1 = '0' and TCLKsig = '1' and RST_TIMERnsig = '1' and TimerRestCMD = '0') then RST_TIMERnsig <= '0'; end if; end if; end process; ----------------------------------------------------------------------------------- --Precess that enable all channes and board when a start command is received -- ----------------------------------------------------------------------------------- EnableChannelsAndBoardsComp : process (rst, clk, RunningFlag) begin if (rst = '1') then ACQENnB0 <= "1111"; --disable all ACQENnB1 <= "1111"; --disable all ACQENnB2 <= "1111"; --disable all ACQENnB3 <= "1111"; --disable all ENABLEn_B <= "1111"; --disable all elsif (clk'event and clk = '1') then --enable the proper channels and board when system is running if (RunningFlag = '1') then ACQENnB0(0)<= not ACQENnB0Reg(0); ACQENnB0(1)<= not ACQENnB0Reg(1); ACQENnB0(2)<= not ACQENnB0Reg(2); ACQENnB0(3)<= not ACQENnB0Reg(3); ACQENnB1(0)<= not ACQENnB1Reg(0); ACQENnB1(1)<= not ACQENnB1Reg(1); ACQENnB1(2)<= not ACQENnB1Reg(2); ACQENnB1(3)<= not ACQENnB1Reg(3); ACQENnB2(0)<= not ACQENnB2Reg(0); ACQENnB2(1)<= not ACQENnB2Reg(1); ACQENnB2(2)<= not ACQENnB2Reg(2); ACQENnB2(3)<= not ACQENnB2Reg(3); ACQENnB3(0)<= not ACQENnB3Reg(0); ACQENnB3(1)<= not ACQENnB3Reg(1); ACQENnB3(2)<= not ACQENnB3Reg(2); ACQENnB3(3)<= not ACQENnB3Reg(3); ENABLEn_B(0)<= not ENABLEn_BReg(0);ENABLEn_B(1)<= not ENABLEn_BReg(1);ENABLEn_B(2)<= not ENABLEn_BReg(2);ENABLEn_B(3)<= not ENABLEn_BReg(3); else ACQENnB0 <= "1111"; --disable all ACQENnB1 <= "1111"; --disable all ACQENnB2 <= "1111"; --disable all ACQENnB3 <= "1111"; --disable all ENABLEn_B <= "1111"; --disable all end if; end if; end process; ----------------------------------------------------------------------------------- --process that generate simulated data -- ----------------------------------------------------------------------------------- IB_SimulDataGen : process (rst, clk, GenDatasig) begin if (rst = '1') then GenDataCounter <= (others => '0'); SimulData <= (others => '0'); GenDataDonesig <= '0'; elsif (clk'event and clk = '1') then -- implements the counter if (GenDatasig = '0') then GenDataCounter <= (others => '0'); else GenDataCounter <= GenDataCounter + 1; end if; SimulData <= GenDataCounter; --end condition if (GenDataCounter = DataPackageSize-3) then GenDataDonesig <= '1'; else GenDataDonesig <= '0'; end if; end if; end process; ----------------------------------------------------------------------------------- --Module that deserialize the commands received from the CTRL link -- ----------------------------------------------------------------------------------- ReceiveCommandComp : ReceiveCommand Port Map( rst => RST, clk => CLK, ser_in => CTRL, command_out => CommandReceived, dav => CommandAvailable ); end Behavioral;