----------------------------------------------------------------------------------
-- Company:				Lawrence Berkeley National Laboratory 
-- Engineer:			Jean-Marie Bussat 
-- Create Date:    	14:04:23 08/10/2006 
-- Design Name: 
-- Module Name:    	ReceiveCommand - Behavioral 
-- Project Name: 		SAO - Multiple Waveform Digitizer System
-- Target Devices:	XC95288TQ144-7 
-- Tool versions: 	Webpack 8.2i 
-- Description:		Receive a 16-bit command sent over the optical link 
--							by the PC-NI interface.
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments:	Simulated and verified 08/10/06 
--                      Testbench is SimTransmitCommand.vhd
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ReceiveCommand is
	Port ( 
		rst 			: in  	STD_LOGIC;
		clk 			: in  	STD_LOGIC;
		ser_in 		: in  	STD_LOGIC;
		command_out : out  	STD_LOGIC_VECTOR (15 downto 0);
		dav 			: out 	STD_LOGIC
	);
end ReceiveCommand;

architecture Behavioral of ReceiveCommand is

constant HEADER : std_logic_vector(3 downto 0) := "1011";

signal sr : std_logic_vector(20 downto 0);
signal cmd_reg : std_logic_vector(15 downto 0);
signal clr_sr : std_logic;

begin
	-- Receive shift register. Constantly shift data in 
	-- except when it receive a clear (clr_sr=1) command.
	-- This shift register is active on the the FALLING EDGE
	-- of the clock since data is sent on the rising edge.
	SHIFT_REGISTER : process(rst,clk,ser_in,sr)
	begin
		if rst='1' then
			sr<=(others=>'0');
		else
			if clk'event and clk='0' then
				if clr_sr='1' then
					sr<=(others=>'0');
				else
					sr(20)<=ser_in;
					sr(19 downto 0)<=sr(20 downto 1);
				end if;
			end if;
		end if;
	end process SHIFT_REGISTER;
	
	-- Detect the presence of the header in the shift
	-- register and load the command register if it has
	-- been found. Also set the flag indicating a new
	-- command has been received. The flag stays at 1 
	-- for one clock period.
	WORD_DETECT : process(rst,clk,sr)
	begin
		if rst='1' then
			cmd_reg<=(others=>'0');
			dav<='0';
		else
			if clk'event and clk='1' then
				if sr(4 downto 1)=HEADER then	-- look for header in bit 1 to 4
					cmd_reg<=sr(20 downto 5);
					dav<='1';
				else
					cmd_reg<=cmd_reg;
					dav<='0';
				end if;
			end if;
		end if;
	end process WORD_DETECT;
	
	command_out<=cmd_reg;

	-- Clear the shift register once a command has been
	-- received. This is to prevent false header detection
	-- triggered by the remaining of the data in the shift
	-- register. To avoid the use of a state machine or a
	-- counter, the shift register has been made one bit 
	-- longer and the second detection of the header cause
	-- the reset of the register.
	SR_CLEAR : process(rst,clk,sr)
	begin
		if rst='1' then
			clr_sr<='0';
		else
			if clk'event and clk='1' then
				if sr(3 downto 0)=HEADER then	-- look for header in bit 0 to 3
					clr_sr<='1';
				else
					clr_sr<='0';
				end if;
			end if;
		end if;
	end process SR_CLEAR;
	
end Behavioral;