-- VHDL Test Bench Created from source file chn2syst.vhd -- 13:44:43 07/03/2006
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY chn2syst_tb_vhd_tb IS
END chn2syst_tb_vhd_tb;

ARCHITECTURE behavior OF chn2syst_tb_vhd_tb IS 

	COMPONENT chn2syst
	PORT(
		reset 			: IN std_logic ;
		clk 				: IN std_logic ;
		enable 			: IN std_logic ;
		dry 				: IN std_logic_vector(3 downto 0) := "0000";          
		rsdry 			: OUT std_logic_vector(3 downto 0);
		timer_oe 		: OUT std_logic_vector(3 downto 0);
		timer_header 	: OUT std_logic;
		timer_chnid 	: OUT std_logic;
		timer_upper 	: OUT std_logic;
		timer_lower 	: OUT std_logic;
		timer_dwc 		: OUT std_logic;
		timer_ndwc 		: OUT std_logic;
		ebeam_oe 		: OUT std_logic;
		ebeam_timer1 	: OUT std_logic;
		ebeam_timer2 	: OUT std_logic;
		ebeam_upword 	: OUT std_logic;
		ebeam_loword 	: OUT std_logic;
		chn_ren 			: OUT std_logic_vector(3 downto 0);
		wen4 				: OUT std_logic
		);
	END COMPONENT;

	-- inputs
	SIGNAL reset 			:  std_logic; 
	SIGNAL clk 				:  std_logic := '0';
	SIGNAL enable 			:  std_logic;
	SIGNAL dry 				:  std_logic_vector(3 downto 0);

	-- outputs
	SIGNAL rsdry 			:  std_logic_vector(3 downto 0);
	SIGNAL timer_oe 		:  std_logic_vector(3 downto 0);
	SIGNAL timer_header 	:  std_logic;
	SIGNAL timer_chnid 	:  std_logic;
	SIGNAL timer_upper 	:  std_logic;
	SIGNAL timer_lower 	:  std_logic;
	SIGNAL timer_dwc 		:  std_logic;
	SIGNAL timer_ndwc 	:  std_logic;
	SIGNAL ebeam_oe 		:  std_logic;
	SIGNAL ebeam_timer1 	:  std_logic;
	SIGNAL ebeam_timer2 	:  std_logic;
	SIGNAL ebeam_upword 	:  std_logic;
	SIGNAL ebeam_loword 	:  std_logic;
	SIGNAL chn_ren 		:  std_logic_vector(3 downto 0);
	SIGNAL wen4 			:  std_logic;

BEGIN

	uut: chn2syst PORT MAP(
		reset 			=> reset,
		clk 				=> clk,
		enable 			=> enable,
		dry 				=> dry,
		rsdry 			=> rsdry,
		timer_oe 		=> timer_oe,
		timer_header 	=> timer_header,
		timer_chnid 	=> timer_chnid,
		timer_upper 	=> timer_upper,
		timer_lower 	=> timer_lower,
		timer_dwc 		=> timer_dwc,
		timer_ndwc 		=> timer_ndwc,
		ebeam_oe 		=> ebeam_oe,
		ebeam_timer1 	=> ebeam_timer1,
		ebeam_timer2 	=> ebeam_timer2,
		ebeam_upword 	=> ebeam_upword,
		ebeam_loword 	=> ebeam_loword,
		chn_ren 			=> chn_ren,
		wen4 				=> wen4
	);


	clk		<=	(not clk) after 50 ns;
	reset		<=	'0','1' after 300 ns;

	enable	<=	'1', '0' after 500 ns;

	dry		<=	"0000", "0001" after 412 us;


END behavior;