library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity sdff is
    Port ( reset : in std_logic;
           clk : in std_logic;
           din : in std_logic;
           qout : out std_logic);
end sdff;

architecture Behavioral of sdff is

begin

	process (reset, clk, din)
	begin
		if (clk'event and clk = '1') then
		
			if reset = '0' then 
				qout <= '0';
			else 
				qout <= din;
			end if;
		
		end if;
	
	end process;


end Behavioral;