library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

-- ************************************************************
--	ALL SIGNALS ARE ACTIVE LOW UNLESS SPECIFIED
-- ************************************************************
--
--	REV 1.1 / DEC 5 2004
--
-- DATAREADY SIGNALS ARE ACTIVE HIGH
--
--	Functionality verified on Feb 21, 2005
--
-- ************************************************************

-- ************************************************************
-- 
-- REV 1.2 / JULY 13, 2006
-- 
-- Fully Synchronous design
-- 
-- ************************************************************


entity request is
    Port ( reset 			: in  std_logic;								 -- reset
           clk 			: in  std_logic;								 -- clock
			  dataready		: in  std_logic_vector(3 downto 0);		 -- data ready = request // ACTIVE HIGH
			  latchen1		: in 	std_logic;								 -- request latch enable #1 /  synchronization latch
			  latchen2		: in  std_logic;								 -- request latch enable #2 / locking latch
			  clr_req		: in 	std_logic;								 -- clear request
			  chn_sel		: out std_logic_vector(3 downto 0);		 -- channel select (output of the encoder)
			  txreq			: out std_logic								 -- transfer request
		   );

end request;


architecture Behavioral of request is

-------------------------------------------------------------	
-- Components
-------------------------------------------------------------	

	COMPONENT sdff
	PORT(
		reset 		: IN std_logic;
		clk 			: IN std_logic;
		din 			: IN std_logic;          
		qout 			: OUT std_logic
		);
	END COMPONENT;

	COMPONENT sdffen
	PORT(
		reset 		: IN std_logic;
		clk 			: IN std_logic;
		en 			: IN std_logic;		-- latch en = 0 / =1 is mem
		din 			: IN std_logic;          
		qout 			: OUT std_logic
		);
	END COMPONENT;

	COMPONENT priority
	PORT(
		clk 			: IN std_logic;
		data_in 		: IN std_logic_vector(3 downto 0);          
		chn_sel 		: OUT std_logic_vector(3 downto 0)
		);
	END COMPONENT;

-------------------------------------------------------------	
-- Signals
-------------------------------------------------------------	
	-- Data ready -> txreq
	signal synched_dry 	: std_logic_vector (3 downto 0);	 -- latch for the data ready signals -> event detect 
	signal latched_dry 	: std_logic_vector (3 downto 0);	 -- latch for the data ready signals -> event detect 
	signal clear			: std_logic_vector (3 downto 0);
	signal txreq_sig		: std_logic;
	signal chn_sel_sig	: std_logic_vector (3 downto 0);
-------------------------------------------------------------	
-- Architecture description
-------------------------------------------------------------	
									
begin
-------------------------------------------------------------	
	-- INSTANCIATION / Data Ready Latches
-------------------------------------------------------------
	-- Synchronization of the DR signal
	-- Inputs are DataReady signals form channels
	-- Outputs are sync'd to the syst. clock
	-- Clear signal controlled from the FSM (individual reset for each DR) and from the master reset.
	
	Inst_sdffen0: sdffen PORT MAP( reset => clear(0), clk => clk, en => latchen1, din => dataready(0), qout => synched_dry(0) );
	Inst_sdffen1: sdffen PORT MAP( reset => clear(1), clk => clk, en => latchen1, din => dataready(1), qout => synched_dry(1) );
	Inst_sdffen2: sdffen PORT MAP( reset => clear(2), clk => clk, en => latchen1, din => dataready(2), qout => synched_dry(2) );
	Inst_sdffen3: sdffen PORT MAP( reset => clear(3), clk => clk, en => latchen1, din => dataready(3), qout => synched_dry(3) );

	Inst_sdffen4: sdffen PORT MAP( reset => reset, clk => clk, en => latchen2, din => synched_dry(0), qout => latched_dry(0) );
	Inst_sdffen5: sdffen PORT MAP( reset => reset, clk => clk, en => latchen2, din => synched_dry(1), qout => latched_dry(1) );
	Inst_sdffen6: sdffen PORT MAP( reset => reset, clk => clk, en => latchen2, din => synched_dry(2), qout => latched_dry(2) );
	Inst_sdffen7: sdffen PORT MAP( reset => reset, clk => clk, en => latchen2, din => synched_dry(3), qout => latched_dry(3) );

	Inst_sdff	: sdff 	PORT MAP( reset => reset, clk => clk, din => txreq_sig, qout => txreq );

-------------------------------------------------------------	

-------------------------------------------------------------	
	-- INSTANCIATION / Priority Encoder
-------------------------------------------------------------	
	-- Provides a channel select signal (LUT)
	
  	Inst_priority: priority PORT MAP( clk => clk, data_in => latched_dry, chn_sel => chn_sel_sig	);


-------------------------------------------------------------	
	-- ASSIGNMENT / Latched Data Ready OR for Transfer txreq 
-------------------------------------------------------------	
	txreq_sig <= latched_dry(0) or latched_dry(1)  or latched_dry(2)  or latched_dry(3);

-------------------------------------------------------------	
	-- ASSIGNMENT / clear latch
-------------------------------------------------------------	
	clear(0)	<= reset and ( chn_sel_sig(0) or clr_req);
	clear(1)	<= reset and ( chn_sel_sig(1) or clr_req);
	clear(2)	<= reset and ( chn_sel_sig(2) or clr_req);
	clear(3)	<= reset and ( chn_sel_sig(3) or clr_req);

-------------------------------------------------------------	
	-- ASSIGNMENT / channel select
-------------------------------------------------------------	
	chn_sel <= chn_sel_sig;

end Behavioral;