library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity priority is
    Port ( 
	 		  clk			: in std_logic;
			  data_in 	: in 	std_logic_vector(3 downto 0);  
           chn_sel	: out std_logic_vector(3 downto 0)
			 ); -- channel select
end priority;

architecture Behavioral of priority is

-- signal
signal chn_sel_sig : std_logic_vector (3 downto 0);


begin

	chn_sel <= chn_sel_sig;

	process(clk,data_in)
	begin
		if (clk'event and clk = '1') then
			if	   (data_in(3) = '1') then chn_sel_sig <= "0111";
			elsif (data_in(2) = '1') then chn_sel_sig <= "1011";
			elsif (data_in(1) = '1') then chn_sel_sig <= "1101";
			elsif (data_in(0) = '1') then chn_sel_sig <= "1110";
			else 	 chn_sel_sig <= "1111";
			end if;
		end if;

	end process;

end Behavioral;