cpldfit: version I.31 Xilinx Inc.
Fitter Report
Design Name: chn2syst Date: 3-21-2007, 4:38PM
Device Used: XC95288XL-6-TQ144
Fitting Status: Successful
************************* Mapped Resource Summary **************************
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
56 /288 ( 19%) 244 /1440 ( 17%) 93 /864 ( 11%) 32 /288 ( 11%) 31 /117 ( 26%)
** Function Block Resources **
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 0/18 0/54 0/90 0/ 8
FB2 11/18 18/54 39/90 4/10
FB3 0/18 0/54 0/90 0/ 5
FB4 9/18 18/54 34/90 4/ 6
FB5 9/18 14/54 24/90 2/ 8
FB6 0/18 0/54 0/90 0/ 8
FB7 4/18 7/54 10/90 4/ 4*
FB8 0/18 0/54 0/90 0/ 5
FB9 16/18 18/54 80/90 8/ 9
FB10 0/18 0/54 0/90 0/10
FB11 7/18 18/54 57/90 2/ 7
FB12 0/18 0/54 0/90 0/ 6
FB13 0/18 0/54 0/90 0/ 6
FB14 0/18 0/54 0/90 0/ 8
FB15 0/18 0/54 0/90 0/ 9
FB16 0/18 0/54 0/90 0/ 8
----- ----- ----- -----
56/288 93/864 244/1440 24/117
* - Resource is exhausted
** Global Control Resources **
Signal 'clk' mapped onto global clock net GCK1.
Global output enable net(s) unused.
Signal 'reset' mapped onto global set/reset net GSR.
** Pin Resources **
Signal Type Required Mapped | Pin Type Used Total
------------------------------------|------------------------------------
Input : 5 5 | I/O : 26 109
Output : 24 24 | GCK/IO : 1 3
Bidirectional : 0 0 | GTS/IO : 3 4
GCK : 1 1 | GSR/IO : 1 1
GTS : 0 0 |
GSR : 1 1 |
---- ----
Total 31 31
** Power Data **
There are 56 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
************************* Summary of Mapped Logic ************************
** 24 Outputs **
Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
Name Pts Inps No. Type Use Mode Rate State
chn_ren<0> 1 6 FB2_8 13 I/O O STD FAST
chn_ren<1> 1 6 FB2_10 14 I/O O STD FAST
chn_ren<2> 1 6 FB2_12 15 I/O O STD FAST
chn_ren<3> 1 6 FB2_14 16 I/O O STD FAST
rsdry<0> 2 7 FB4_5 3 GTS/I/O O STD FAST
rsdry<1> 2 7 FB4_6 4 I/O O STD FAST
rsdry<2> 2 7 FB4_8 5 GTS/I/O O STD FAST
rsdry<3> 2 7 FB4_12 6 GTS/I/O O STD FAST
timer_oe<0> 4 6 FB5_15 43 I/O O STD FAST
timer_oe<1> 4 6 FB5_17 44 I/O O STD FAST
timer_oe<2> 4 6 FB7_3 45 I/O O STD FAST
timer_oe<3> 4 6 FB7_5 46 I/O O STD FAST
timer_header 1 5 FB7_12 48 I/O O STD FAST
timer_chnid 1 5 FB7_15 49 I/O O STD FAST
timer_upper 1 5 FB9_2 50 I/O O STD FAST
timer_lower 1 5 FB9_3 51 I/O O STD FAST
timer_dwc 1 5 FB9_5 52 I/O O STD FAST
timer_ndwc 1 5 FB9_6 53 I/O O STD FAST
ebeam_loword 1 4 FB9_11 56 I/O O STD FAST
ebeam_upword 1 4 FB9_12 57 I/O O STD FAST
ebeam_timer2 1 4 FB9_14 58 I/O O STD FAST
ebeam_timer1 1 4 FB9_17 59 I/O O STD FAST
ebeam_oe 1 3 FB11_3 60 I/O O STD FAST
wen4 6 5 FB11_14 69 I/O O STD FAST
** 32 Buried Nodes **
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
Inst_transfer_fsm/state_FFd4 8 8 FB2_1 STD RESET
Inst_transfer_fsm/state_FFd2 2 5 FB2_9 STD RESET
Inst_transfer_fsm/state_FFd1 3 6 FB2_11 STD RESET
Inst_request/latched_dry<1> 5 8 FB2_13 STD RESET
Inst_request/latched_dry<0> 5 8 FB2_15 STD RESET
Inst_transfer_fsm/state_FFd5 6 9 FB2_17 STD RESET
Inst_transfer_fsm/state_FFd3 6 6 FB2_18 STD RESET
Inst_request/synched_dry<3> 4 9 FB4_14 STD RESET
Inst_request/synched_dry<2> 4 9 FB4_15 STD RESET
Inst_request/synched_dry<1> 4 9 FB4_16 STD RESET
Inst_request/synched_dry<0> 4 9 FB4_17 STD RESET
Inst_transfer_fsm/clr_req_ovf 10 14 FB4_18 STD RESET
chn_sel_sig<3> 1 1 FB5_10 STD RESET
chn_sel_sig<2> 1 2 FB5_11 STD RESET
chn_sel_sig<1> 1 3 FB5_12 STD RESET
chn_sel_sig<0> 1 4 FB5_13 STD RESET
txreq_sig 2 5 FB5_14 STD RESET
Inst_request/latched_dry<3> 5 8 FB5_16 STD RESET
Inst_request/latched_dry<2> 5 8 FB5_18 STD RESET
Inst_transfer_fsm/data_tx_ovf 3 18 FB9_1 STD RESET
Inst_transfer_fsm/data_tx_cnt<10> 10 18 FB9_4 STD RESET
Inst_transfer_fsm/data_tx_cnt<11> 10 18 FB9_7 STD RESET
Inst_transfer_fsm/data_tx_cnt<1> 10 18 FB9_9 STD RESET
Inst_transfer_fsm/data_tx_cnt<4> 10 18 FB9_10 STD RESET
Inst_transfer_fsm/data_tx_cnt<5> 10 18 FB9_13 STD RESET
Inst_transfer_fsm/data_tx_cnt<0> 8 17 FB9_15 STD RESET
Inst_transfer_fsm/data_tx_cnt<3> 11 18 FB9_18 STD RESET
Inst_transfer_fsm/data_tx_cnt<6> 10 18 FB11_1 STD RESET
Inst_transfer_fsm/data_tx_cnt<2> 10 17 FB11_2 STD RESET
Inst_transfer_fsm/data_tx_cnt<9> 10 18 FB11_11 STD RESET
Inst_transfer_fsm/data_tx_cnt<8> 10 18 FB11_13 STD RESET
Inst_transfer_fsm/data_tx_cnt<7> 10 18 FB11_17 STD RESET
** 7 Inputs **
Signal Loc Pin Pin Pin
Name No. Type Use
dry<0> FB2_2 9 I/O I
dry<1> FB2_3 10 I/O I
dry<2> FB2_5 11 I/O I
dry<3> FB2_6 12 I/O I
clk FB3_10 30 GCK/I/O GCK
enable FB6_14 142 I/O I
reset FB6_15 143 GSR/I/O GSR/I
Legend:
Pin No. - ~ - User Assigned
************************** Function Block Details ************************
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X - Signal used as input to the macrocell logic.
Pin No. - ~ - User Assigned
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 0/54
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB1_1 (b)
(unused) 0 0 0 5 FB1_2 (b)
(unused) 0 0 0 5 FB1_3 (b)
(unused) 0 0 0 5 FB1_4 (b)
(unused) 0 0 0 5 FB1_5 20 I/O
(unused) 0 0 0 5 FB1_6 21 I/O
(unused) 0 0 0 5 FB1_7 (b)
(unused) 0 0 0 5 FB1_8 22 I/O
(unused) 0 0 0 5 FB1_9 (b)
(unused) 0 0 0 5 FB1_10 23 I/O
(unused) 0 0 0 5 FB1_11 (b)
(unused) 0 0 0 5 FB1_12 24 I/O
(unused) 0 0 0 5 FB1_13 (b)
(unused) 0 0 0 5 FB1_14 25 I/O
(unused) 0 0 0 5 FB1_15 26 I/O
(unused) 0 0 0 5 FB1_16 (b)
(unused) 0 0 0 5 FB1_17 27 I/O
(unused) 0 0 0 5 FB1_18 (b)
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 18/36
Number of signals used by logic mapping into function block: 18
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
Inst_transfer_fsm/state_FFd4
8 4<- /\1 0 FB2_1 (b) (b)
(unused) 0 0 /\4 1 FB2_2 9 I/O I
(unused) 0 0 0 5 FB2_3 10 I/O I
(unused) 0 0 0 5 FB2_4 (b)
(unused) 0 0 0 5 FB2_5 11 I/O I
(unused) 0 0 0 5 FB2_6 12 I/O I
(unused) 0 0 0 5 FB2_7 (b)
chn_ren<0> 1 0 0 4 FB2_8 13 I/O O
Inst_transfer_fsm/state_FFd2
2 0 0 3 FB2_9 (b) (b)
chn_ren<1> 1 0 0 4 FB2_10 14 I/O O
Inst_transfer_fsm/state_FFd1
3 0 0 2 FB2_11 (b) (b)
chn_ren<2> 1 0 0 4 FB2_12 15 I/O O
Inst_request/latched_dry<1>
5 0 0 0 FB2_13 (b) (b)
chn_ren<3> 1 0 0 4 FB2_14 16 I/O O
Inst_request/latched_dry<0>
5 0 0 0 FB2_15 17 I/O (b)
(unused) 0 0 \/1 4 FB2_16 (b) (b)
Inst_transfer_fsm/state_FFd5
6 1<- 0 0 FB2_17 19 I/O (b)
Inst_transfer_fsm/state_FFd3
6 1<- 0 0 FB2_18 (b) (b)
Signals Used by Logic in Function Block
1: Inst_request/latched_dry<0> 7: Inst_transfer_fsm/state_FFd1 13: chn_sel_sig<1>
2: Inst_request/latched_dry<1> 8: Inst_transfer_fsm/state_FFd2 14: chn_sel_sig<2>
3: Inst_request/synched_dry<0> 9: Inst_transfer_fsm/state_FFd3 15: chn_sel_sig<3>
4: Inst_request/synched_dry<1> 10: Inst_transfer_fsm/state_FFd4 16: enable
5: Inst_transfer_fsm/clr_req_ovf 11: Inst_transfer_fsm/state_FFd5 17: reset
6: Inst_transfer_fsm/data_tx_ovf 12: chn_sel_sig<0> 18: txreq_sig
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
Inst_transfer_fsm/state_FFd4
....X.XXXXX....X.X...................... 8
chn_ren<0> ......XXXXXX............................ 6
Inst_transfer_fsm/state_FFd2
.......XXXX....X........................ 5
chn_ren<1> ......XXXXX.X........................... 6
Inst_transfer_fsm/state_FFd1
......XXXXX....X........................ 6
chn_ren<2> ......XXXXX..X.......................... 6
Inst_request/latched_dry<1>
.X.X..XXXXX.....X....................... 8
chn_ren<3> ......XXXXX...X......................... 6
Inst_request/latched_dry<0>
X.X...XXXXX.....X....................... 8
Inst_transfer_fsm/state_FFd5
....XXXXXXX....X.X...................... 9
Inst_transfer_fsm/state_FFd3
......XXXXX....X........................ 6
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 0/54
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB3_1 (b)
(unused) 0 0 0 5 FB3_2 28 I/O
(unused) 0 0 0 5 FB3_3 (b)
(unused) 0 0 0 5 FB3_4 (b)
(unused) 0 0 0 5 FB3_5 (b)
(unused) 0 0 0 5 FB3_6 (b)
(unused) 0 0 0 5 FB3_7 (b)
(unused) 0 0 0 5 FB3_8 (b)
(unused) 0 0 0 5 FB3_9 (b)
(unused) 0 0 0 5 FB3_10 30 GCK/I/O GCK
(unused) 0 0 0 5 FB3_11 (b)
(unused) 0 0 0 5 FB3_12 31 I/O
(unused) 0 0 0 5 FB3_13 (b)
(unused) 0 0 0 5 FB3_14 32 GCK/I/O
(unused) 0 0 0 5 FB3_15 33 I/O
(unused) 0 0 0 5 FB3_16 (b)
(unused) 0 0 0 5 FB3_17 (b)
(unused) 0 0 0 5 FB3_18 (b)
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 18/36
Number of signals used by logic mapping into function block: 18
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 /\4 1 FB4_1 (b) (b)
(unused) 0 0 0 5 FB4_2 2 GTS/I/O
(unused) 0 0 0 5 FB4_3 (b)
(unused) 0 0 0 5 FB4_4 (b)
rsdry<0> 2 0 0 3 FB4_5 3 GTS/I/O O
rsdry<1> 2 0 0 3 FB4_6 4 I/O O
(unused) 0 0 0 5 FB4_7 (b)
rsdry<2> 2 0 0 3 FB4_8 5 GTS/I/O O
(unused) 0 0 0 5 FB4_9 (b)
(unused) 0 0 0 5 FB4_10 (b)
(unused) 0 0 0 5 FB4_11 (b)
rsdry<3> 2 0 0 3 FB4_12 6 GTS/I/O O
(unused) 0 0 0 5 FB4_13 (b)
Inst_request/synched_dry<3>
4 0 0 1 FB4_14 7 I/O (b)
Inst_request/synched_dry<2>
4 0 0 1 FB4_15 (b) (b)
Inst_request/synched_dry<1>
4 0 0 1 FB4_16 (b) (b)
Inst_request/synched_dry<0>
4 0 \/1 0 FB4_17 (b) (b)
Inst_transfer_fsm/clr_req_ovf
10 5<- 0 0 FB4_18 (b) (b)
Signals Used by Logic in Function Block
1: Inst_request/synched_dry<0> 7: Inst_transfer_fsm/state_FFd3 13: chn_sel_sig<3>
2: Inst_request/synched_dry<1> 8: Inst_transfer_fsm/state_FFd4 14: dry<0>
3: Inst_request/synched_dry<2> 9: Inst_transfer_fsm/state_FFd5 15: dry<1>
4: Inst_request/synched_dry<3> 10: chn_sel_sig<0> 16: dry<2>
5: Inst_transfer_fsm/state_FFd1 11: chn_sel_sig<1> 17: dry<3>
6: Inst_transfer_fsm/state_FFd2 12: chn_sel_sig<2> 18: reset
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
rsdry<0> ....XXXXXX.......X...................... 7
rsdry<1> ....XXXXX.X......X...................... 7
rsdry<2> ....XXXXX..X.....X...................... 7
rsdry<3> ....XXXXX...X....X...................... 7
Inst_request/synched_dry<3>
...XXXXXX...X...XX...................... 9
Inst_request/synched_dry<2>
..X.XXXXX..X...X.X...................... 9
Inst_request/synched_dry<1>
.X..XXXXX.X...X..X...................... 9
Inst_request/synched_dry<0>
X...XXXXXX...X...X...................... 9
Inst_transfer_fsm/clr_req_ovf
....XXXXXXXXXXXXXX...................... 14
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB5 ***********************************
Number of function block inputs used/remaining: 14/40
Number of signals used by logic mapping into function block: 14
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB5_1 (b)
(unused) 0 0 0 5 FB5_2 34 I/O
(unused) 0 0 0 5 FB5_3 (b)
(unused) 0 0 0 5 FB5_4 (b)
(unused) 0 0 0 5 FB5_5 35 I/O
(unused) 0 0 0 5 FB5_6 (b)
(unused) 0 0 0 5 FB5_7 (b)
(unused) 0 0 0 5 FB5_8 38 GCK/I/O
(unused) 0 0 0 5 FB5_9 (b)
chn_sel_sig<3> 1 0 0 4 FB5_10 39 I/O (b)
chn_sel_sig<2> 1 0 0 4 FB5_11 (b) (b)
chn_sel_sig<1> 1 0 0 4 FB5_12 40 I/O (b)
chn_sel_sig<0> 1 0 0 4 FB5_13 (b) (b)
txreq_sig 2 0 0 3 FB5_14 41 I/O (b)
timer_oe<0> 4 0 0 1 FB5_15 43 I/O O
Inst_request/latched_dry<3>
5 0 0 0 FB5_16 (b) (b)
timer_oe<1> 4 0 0 1 FB5_17 44 I/O O
Inst_request/latched_dry<2>
5 0 0 0 FB5_18 (b) (b)
Signals Used by Logic in Function Block
1: Inst_request/latched_dry<0> 6: Inst_request/synched_dry<3> 11: Inst_transfer_fsm/state_FFd5
2: Inst_request/latched_dry<1> 7: Inst_transfer_fsm/state_FFd1 12: chn_sel_sig<0>
3: Inst_request/latched_dry<2> 8: Inst_transfer_fsm/state_FFd2 13: chn_sel_sig<1>
4: Inst_request/latched_dry<3> 9: Inst_transfer_fsm/state_FFd3 14: reset
5: Inst_request/synched_dry<2> 10: Inst_transfer_fsm/state_FFd4
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
chn_sel_sig<3> ...X.................................... 1
chn_sel_sig<2> ..XX.................................... 2
chn_sel_sig<1> .XXX.................................... 3
chn_sel_sig<0> XXXX.................................... 4
txreq_sig XXXX.........X.......................... 5
timer_oe<0> ......XXXXXX............................ 6
Inst_request/latched_dry<3>
...X.XXXXXX..X.......................... 8
timer_oe<1> ......XXXXX.X........................... 6
Inst_request/latched_dry<2>
..X.X.XXXXX..X.......................... 8
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB6 ***********************************
Number of function block inputs used/remaining: 0/54
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB6_1 (b)
(unused) 0 0 0 5 FB6_2 135 I/O
(unused) 0 0 0 5 FB6_3 136 I/O
(unused) 0 0 0 5 FB6_4 (b)
(unused) 0 0 0 5 FB6_5 137 I/O
(unused) 0 0 0 5 FB6_6 138 I/O
(unused) 0 0 0 5 FB6_7 (b)
(unused) 0 0 0 5 FB6_8 139 I/O
(unused) 0 0 0 5 FB6_9 (b)
(unused) 0 0 0 5 FB6_10 140 I/O
(unused) 0 0 0 5 FB6_11 (b)
(unused) 0 0 0 5 FB6_12 (b)
(unused) 0 0 0 5 FB6_13 (b)
(unused) 0 0 0 5 FB6_14 142 I/O I
(unused) 0 0 0 5 FB6_15 143 GSR/I/O GSR/I
(unused) 0 0 0 5 FB6_16 (b)
(unused) 0 0 0 5 FB6_17 (b)
(unused) 0 0 0 5 FB6_18 (b)
*********************************** FB7 ***********************************
Number of function block inputs used/remaining: 7/47
Number of signals used by logic mapping into function block: 7
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB7_1 (b)
(unused) 0 0 0 5 FB7_2 (b)
timer_oe<2> 4 0 0 1 FB7_3 45 I/O O
(unused) 0 0 0 5 FB7_4 (b)
timer_oe<3> 4 0 0 1 FB7_5 46 I/O O
(unused) 0 0 0 5 FB7_6 (b)
(unused) 0 0 0 5 FB7_7 (b)
(unused) 0 0 0 5 FB7_8 (b)
(unused) 0 0 0 5 FB7_9 (b)
(unused) 0 0 0 5 FB7_10 (b)
(unused) 0 0 0 5 FB7_11 (b)
timer_header 1 0 0 4 FB7_12 48 I/O O
(unused) 0 0 0 5 FB7_13 (b)
(unused) 0 0 0 5 FB7_14 (b)
timer_chnid 1 0 0 4 FB7_15 49 I/O O
(unused) 0 0 0 5 FB7_16 (b)
(unused) 0 0 0 5 FB7_17 (b)
(unused) 0 0 0 5 FB7_18 (b)
Signals Used by Logic in Function Block
1: Inst_transfer_fsm/state_FFd1 4: Inst_transfer_fsm/state_FFd4 6: chn_sel_sig<2>
2: Inst_transfer_fsm/state_FFd2 5: Inst_transfer_fsm/state_FFd5 7: chn_sel_sig<3>
3: Inst_transfer_fsm/state_FFd3
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
timer_oe<2> XXXXXX.................................. 6
timer_oe<3> XXXXX.X................................. 6
timer_header XXXXX................................... 5
timer_chnid XXXXX................................... 5
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB8 ***********************************
Number of function block inputs used/remaining: 0/54
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB8_1 (b)
(unused) 0 0 0 5 FB8_2 130 I/O
(unused) 0 0 0 5 FB8_3 131 I/O
(unused) 0 0 0 5 FB8_4 (b)
(unused) 0 0 0 5 FB8_5 132 I/O
(unused) 0 0 0 5 FB8_6 (b)
(unused) 0 0 0 5 FB8_7 (b)
(unused) 0 0 0 5 FB8_8 133 I/O
(unused) 0 0 0 5 FB8_9 (b)
(unused) 0 0 0 5 FB8_10 134 I/O
(unused) 0 0 0 5 FB8_11 (b)
(unused) 0 0 0 5 FB8_12 (b)
(unused) 0 0 0 5 FB8_13 (b)
(unused) 0 0 0 5 FB8_14 (b)
(unused) 0 0 0 5 FB8_15 (b)
(unused) 0 0 0 5 FB8_16 (b)
(unused) 0 0 0 5 FB8_17 (b)
(unused) 0 0 0 5 FB8_18 (b)
*********************************** FB9 ***********************************
Number of function block inputs used/remaining: 18/36
Number of signals used by logic mapping into function block: 18
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
Inst_transfer_fsm/data_tx_ovf
3 0 /\2 0 FB9_1 (b) (b)
timer_upper 1 0 \/1 3 FB9_2 50 I/O O
timer_lower 1 1<- \/5 0 FB9_3 51 I/O O
Inst_transfer_fsm/data_tx_cnt<10>
10 5<- 0 0 FB9_4 (b) (b)
timer_dwc 1 0 \/1 3 FB9_5 52 I/O O
timer_ndwc 1 1<- \/5 0 FB9_6 53 I/O O
Inst_transfer_fsm/data_tx_cnt<11>
10 5<- 0 0 FB9_7 (b) (b)
(unused) 0 0 \/5 0 FB9_8 54 I/O (b)
Inst_transfer_fsm/data_tx_cnt<1>
10 5<- 0 0 FB9_9 (b) (b)
Inst_transfer_fsm/data_tx_cnt<4>
10 5<- 0 0 FB9_10 (b) (b)
ebeam_loword 1 1<- /\5 0 FB9_11 56 I/O O
ebeam_upword 1 0 /\1 3 FB9_12 57 I/O O
Inst_transfer_fsm/data_tx_cnt<5>
10 5<- 0 0 FB9_13 (b) (b)
ebeam_timer2 1 1<- /\5 0 FB9_14 58 I/O O
Inst_transfer_fsm/data_tx_cnt<0>
8 4<- /\1 0 FB9_15 (b) (b)
(unused) 0 0 /\4 1 FB9_16 (b) (b)
ebeam_timer1 1 0 \/4 0 FB9_17 59 I/O O
Inst_transfer_fsm/data_tx_cnt<3>
11 6<- 0 0 FB9_18 (b) (b)
Signals Used by Logic in Function Block
1: Inst_transfer_fsm/data_tx_cnt<0> 7: Inst_transfer_fsm/data_tx_cnt<4> 13: Inst_transfer_fsm/state_FFd1
2: Inst_transfer_fsm/data_tx_cnt<10> 8: Inst_transfer_fsm/data_tx_cnt<5> 14: Inst_transfer_fsm/state_FFd2
3: Inst_transfer_fsm/data_tx_cnt<11> 9: Inst_transfer_fsm/data_tx_cnt<6> 15: Inst_transfer_fsm/state_FFd3
4: Inst_transfer_fsm/data_tx_cnt<1> 10: Inst_transfer_fsm/data_tx_cnt<7> 16: Inst_transfer_fsm/state_FFd4
5: Inst_transfer_fsm/data_tx_cnt<2> 11: Inst_transfer_fsm/data_tx_cnt<8> 17: Inst_transfer_fsm/state_FFd5
6: Inst_transfer_fsm/data_tx_cnt<3> 12: Inst_transfer_fsm/data_tx_cnt<9> 18: reset
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
Inst_transfer_fsm/data_tx_ovf
XXXXXXXXXXXXXXXXXX...................... 18
timer_upper ............XXXXX....................... 5
timer_lower ............XXXXX....................... 5
Inst_transfer_fsm/data_tx_cnt<10>
XXXXXXXXXXXXXXXXXX...................... 18
timer_dwc ............XXXXX....................... 5
timer_ndwc ............XXXXX....................... 5
Inst_transfer_fsm/data_tx_cnt<11>
XXXXXXXXXXXXXXXXXX...................... 18
Inst_transfer_fsm/data_tx_cnt<1>
XXXXXXXXXXXXXXXXXX...................... 18
Inst_transfer_fsm/data_tx_cnt<4>
XXXXXXXXXXXXXXXXXX...................... 18
ebeam_loword ............XXX.X....................... 4
ebeam_upword ............XXX.X....................... 4
Inst_transfer_fsm/data_tx_cnt<5>
XXXXXXXXXXXXXXXXXX...................... 18
ebeam_timer2 ............XXXX........................ 4
Inst_transfer_fsm/data_tx_cnt<0>
XXX.XXXXXXXXXXXXXX...................... 17
ebeam_timer1 ............XXXX........................ 4
Inst_transfer_fsm/data_tx_cnt<3>
XXXXXXXXXXXXXXXXXX...................... 18
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB10 ***********************************
Number of function block inputs used/remaining: 0/54
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB10_1 (b)
(unused) 0 0 0 5 FB10_2 117 I/O
(unused) 0 0 0 5 FB10_3 118 I/O
(unused) 0 0 0 5 FB10_4 (b)
(unused) 0 0 0 5 FB10_5 119 I/O
(unused) 0 0 0 5 FB10_6 120 I/O
(unused) 0 0 0 5 FB10_7 (b)
(unused) 0 0 0 5 FB10_8 121 I/O
(unused) 0 0 0 5 FB10_9 (b)
(unused) 0 0 0 5 FB10_10 124 I/O
(unused) 0 0 0 5 FB10_11 125 I/O
(unused) 0 0 0 5 FB10_12 126 I/O
(unused) 0 0 0 5 FB10_13 (b)
(unused) 0 0 0 5 FB10_14 128 I/O
(unused) 0 0 0 5 FB10_15 (b)
(unused) 0 0 0 5 FB10_16 (b)
(unused) 0 0 0 5 FB10_17 129 I/O
(unused) 0 0 0 5 FB10_18 (b)
*********************************** FB11 ***********************************
Number of function block inputs used/remaining: 18/36
Number of signals used by logic mapping into function block: 18
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
Inst_transfer_fsm/data_tx_cnt<6>
10 5<- 0 0 FB11_1 (b) (b)
Inst_transfer_fsm/data_tx_cnt<2>
10 5<- 0 0 FB11_2 (b) (b)
ebeam_oe 1 1<- /\5 0 FB11_3 60 I/O O
(unused) 0 0 /\1 4 FB11_4 (b) (b)
(unused) 0 0 0 5 FB11_5 61 I/O
(unused) 0 0 0 5 FB11_6 (b)
(unused) 0 0 0 5 FB11_7 (b)
(unused) 0 0 0 5 FB11_8 (b)
(unused) 0 0 0 5 FB11_9 (b)
(unused) 0 0 \/5 0 FB11_10 64 I/O (b)
Inst_transfer_fsm/data_tx_cnt<9>
10 5<- 0 0 FB11_11 66 I/O (b)
(unused) 0 0 \/5 0 FB11_12 68 I/O (b)
Inst_transfer_fsm/data_tx_cnt<8>
10 5<- 0 0 FB11_13 (b) (b)
wen4 6 1<- 0 0 FB11_14 69 I/O O
(unused) 0 0 /\1 4 FB11_15 (b) (b)
(unused) 0 0 \/5 0 FB11_16 (b) (b)
Inst_transfer_fsm/data_tx_cnt<7>
10 5<- 0 0 FB11_17 70 I/O (b)
(unused) 0 0 \/5 0 FB11_18 (b) (b)
Signals Used by Logic in Function Block
1: Inst_transfer_fsm/data_tx_cnt<0> 7: Inst_transfer_fsm/data_tx_cnt<4> 13: Inst_transfer_fsm/state_FFd1
2: Inst_transfer_fsm/data_tx_cnt<10> 8: Inst_transfer_fsm/data_tx_cnt<5> 14: Inst_transfer_fsm/state_FFd2
3: Inst_transfer_fsm/data_tx_cnt<11> 9: Inst_transfer_fsm/data_tx_cnt<6> 15: Inst_transfer_fsm/state_FFd3
4: Inst_transfer_fsm/data_tx_cnt<1> 10: Inst_transfer_fsm/data_tx_cnt<7> 16: Inst_transfer_fsm/state_FFd4
5: Inst_transfer_fsm/data_tx_cnt<2> 11: Inst_transfer_fsm/data_tx_cnt<8> 17: Inst_transfer_fsm/state_FFd5
6: Inst_transfer_fsm/data_tx_cnt<3> 12: Inst_transfer_fsm/data_tx_cnt<9> 18: reset
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
Inst_transfer_fsm/data_tx_cnt<6>
XXXXXXXXXXXXXXXXXX...................... 18
Inst_transfer_fsm/data_tx_cnt<2>
XXXXX.XXXXXXXXXXXX...................... 17
ebeam_oe ............XXX......................... 3
Inst_transfer_fsm/data_tx_cnt<9>
XXXXXXXXXXXXXXXXXX...................... 18
Inst_transfer_fsm/data_tx_cnt<8>
XXXXXXXXXXXXXXXXXX...................... 18
wen4 ............XXXXX....................... 5
Inst_transfer_fsm/data_tx_cnt<7>
XXXXXXXXXXXXXXXXXX...................... 18
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB12 ***********************************
Number of function block inputs used/remaining: 0/54
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB12_1 (b)
(unused) 0 0 0 5 FB12_2 110 I/O
(unused) 0 0 0 5 FB12_3 111 I/O
(unused) 0 0 0 5 FB12_4 (b)
(unused) 0 0 0 5 FB12_5 112 I/O
(unused) 0 0 0 5 FB12_6 (b)
(unused) 0 0 0 5 FB12_7 (b)
(unused) 0 0 0 5 FB12_8 113 I/O
(unused) 0 0 0 5 FB12_9 (b)
(unused) 0 0 0 5 FB12_10 115 I/O
(unused) 0 0 0 5 FB12_11 (b)
(unused) 0 0 0 5 FB12_12 116 I/O
(unused) 0 0 0 5 FB12_13 (b)
(unused) 0 0 0 5 FB12_14 (b)
(unused) 0 0 0 5 FB12_15 (b)
(unused) 0 0 0 5 FB12_16 (b)
(unused) 0 0 0 5 FB12_17 (b)
(unused) 0 0 0 5 FB12_18 (b)
*********************************** FB13 ***********************************
Number of function block inputs used/remaining: 0/54
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB13_1 (b)
(unused) 0 0 0 5 FB13_2 71 I/O
(unused) 0 0 0 5 FB13_3 (b)
(unused) 0 0 0 5 FB13_4 (b)
(unused) 0 0 0 5 FB13_5 (b)
(unused) 0 0 0 5 FB13_6 (b)
(unused) 0 0 0 5 FB13_7 (b)
(unused) 0 0 0 5 FB13_8 74 I/O
(unused) 0 0 0 5 FB13_9 (b)
(unused) 0 0 0 5 FB13_10 (b)
(unused) 0 0 0 5 FB13_11 75 I/O
(unused) 0 0 0 5 FB13_12 (b)
(unused) 0 0 0 5 FB13_13 (b)
(unused) 0 0 0 5 FB13_14 76 I/O
(unused) 0 0 0 5 FB13_15 77 I/O
(unused) 0 0 0 5 FB13_16 (b)
(unused) 0 0 0 5 FB13_17 78 I/O
(unused) 0 0 0 5 FB13_18 (b)
*********************************** FB14 ***********************************
Number of function block inputs used/remaining: 0/54
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB14_1 (b)
(unused) 0 0 0 5 FB14_2 (b)
(unused) 0 0 0 5 FB14_3 100 I/O
(unused) 0 0 0 5 FB14_4 (b)
(unused) 0 0 0 5 FB14_5 101 I/O
(unused) 0 0 0 5 FB14_6 102 I/O
(unused) 0 0 0 5 FB14_7 (b)
(unused) 0 0 0 5 FB14_8 103 I/O
(unused) 0 0 0 5 FB14_9 (b)
(unused) 0 0 0 5 FB14_10 104 I/O
(unused) 0 0 0 5 FB14_11 105 I/O
(unused) 0 0 0 5 FB14_12 (b)
(unused) 0 0 0 5 FB14_13 (b)
(unused) 0 0 0 5 FB14_14 106 I/O
(unused) 0 0 0 5 FB14_15 107 I/O
(unused) 0 0 0 5 FB14_16 (b)
(unused) 0 0 0 5 FB14_17 (b)
(unused) 0 0 0 5 FB14_18 (b)
*********************************** FB15 ***********************************
Number of function block inputs used/remaining: 0/54
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB15_1 (b)
(unused) 0 0 0 5 FB15_2 79 I/O
(unused) 0 0 0 5 FB15_3 80 I/O
(unused) 0 0 0 5 FB15_4 (b)
(unused) 0 0 0 5 FB15_5 (b)
(unused) 0 0 0 5 FB15_6 (b)
(unused) 0 0 0 5 FB15_7 (b)
(unused) 0 0 0 5 FB15_8 81 I/O
(unused) 0 0 0 5 FB15_9 (b)
(unused) 0 0 0 5 FB15_10 82 I/O
(unused) 0 0 0 5 FB15_11 83 I/O
(unused) 0 0 0 5 FB15_12 85 I/O
(unused) 0 0 0 5 FB15_13 (b)
(unused) 0 0 0 5 FB15_14 86 I/O
(unused) 0 0 0 5 FB15_15 87 I/O
(unused) 0 0 0 5 FB15_16 (b)
(unused) 0 0 0 5 FB15_17 88 I/O
(unused) 0 0 0 5 FB15_18 (b)
*********************************** FB16 ***********************************
Number of function block inputs used/remaining: 0/54
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB16_1 (b)
(unused) 0 0 0 5 FB16_2 91 I/O
(unused) 0 0 0 5 FB16_3 92 I/O
(unused) 0 0 0 5 FB16_4 (b)
(unused) 0 0 0 5 FB16_5 93 I/O
(unused) 0 0 0 5 FB16_6 94 I/O
(unused) 0 0 0 5 FB16_7 (b)
(unused) 0 0 0 5 FB16_8 95 I/O
(unused) 0 0 0 5 FB16_9 (b)
(unused) 0 0 0 5 FB16_10 96 I/O
(unused) 0 0 0 5 FB16_11 97 I/O
(unused) 0 0 0 5 FB16_12 98 I/O
(unused) 0 0 0 5 FB16_13 (b)
(unused) 0 0 0 5 FB16_14 (b)
(unused) 0 0 0 5 FB16_15 (b)
(unused) 0 0 0 5 FB16_16 (b)
(unused) 0 0 0 5 FB16_17 (b)
(unused) 0 0 0 5 FB16_18 (b)
******************************* Equations ********************************
********** Mapped Logic **********
FTCPE_Inst_request/latched_dry0: FTCPE port map (Inst_request/latched_dry(0),Inst_request/latched_dry_T(0),clk,'0','0');
Inst_request/latched_dry_T(0) <= ((NOT reset AND Inst_request/latched_dry(0))
OR (Inst_transfer_fsm/state_FFd5 AND
NOT Inst_transfer_fsm/state_FFd1 AND NOT Inst_transfer_fsm/state_FFd4 AND
NOT Inst_transfer_fsm/state_FFd3 AND NOT Inst_transfer_fsm/state_FFd2 AND
Inst_request/latched_dry(0) AND NOT Inst_request/synched_dry(0))
OR (NOT Inst_transfer_fsm/state_FFd5 AND
Inst_transfer_fsm/state_FFd1 AND Inst_transfer_fsm/state_FFd4 AND
NOT Inst_transfer_fsm/state_FFd3 AND NOT Inst_transfer_fsm/state_FFd2 AND
Inst_request/latched_dry(0) AND NOT Inst_request/synched_dry(0))
OR (reset AND Inst_transfer_fsm/state_FFd5 AND
NOT Inst_transfer_fsm/state_FFd1 AND NOT Inst_transfer_fsm/state_FFd4 AND
NOT Inst_transfer_fsm/state_FFd3 AND NOT Inst_transfer_fsm/state_FFd2 AND
NOT Inst_request/latched_dry(0) AND Inst_request/synched_dry(0))
OR (reset AND NOT Inst_transfer_fsm/state_FFd5 AND
Inst_transfer_fsm/state_FFd1 AND Inst_transfer_fsm/state_FFd4 AND
NOT Inst_transfer_fsm/state_FFd3 AND NOT Inst_transfer_fsm/state_FFd2 AND
NOT Inst_request/latched_dry(0) AND Inst_request/synched_dry(0)));
FTCPE_Inst_request/latched_dry1: FTCPE port map (Inst_request/latched_dry(1),Inst_request/latched_dry_T(1),clk,'0','0');
Inst_request/latched_dry_T(1) <= ((NOT reset AND Inst_request/latched_dry(1))
OR (Inst_transfer_fsm/state_FFd5 AND
NOT Inst_transfer_fsm/state_FFd1 AND NOT Inst_transfer_fsm/state_FFd4 AND
NOT Inst_transfer_fsm/state_FFd3 AND NOT Inst_transfer_fsm/state_FFd2 AND
Inst_request/latched_dry(1) AND NOT Inst_request/synched_dry(1))
OR (NOT Inst_transfer_fsm/state_FFd5 AND
Inst_transfer_fsm/state_FFd1 AND Inst_transfer_fsm/state_FFd4 AND
NOT Inst_transfer_fsm/state_FFd3 AND NOT Inst_transfer_fsm/state_FFd2 AND
Inst_request/latched_dry(1) AND NOT Inst_request/synched_dry(1))
OR (reset AND Inst_transfer_fsm/state_FFd5 AND
NOT Inst_transfer_fsm/state_FFd1 AND NOT Inst_transfer_fsm/state_FFd4 AND
NOT Inst_transfer_fsm/state_FFd3 AND NOT Inst_transfer_fsm/state_FFd2 AND
NOT Inst_request/latched_dry(1) AND Inst_request/synched_dry(1))
OR (reset AND NOT Inst_transfer_fsm/state_FFd5 AND
Inst_transfer_fsm/state_FFd1 AND Inst_transfer_fsm/state_FFd4 AND
NOT Inst_transfer_fsm/state_FFd3 AND NOT Inst_transfer_fsm/state_FFd2 AND
NOT Inst_request/latched_dry(1) AND Inst_request/synched_dry(1)));
FTCPE_Inst_request/latched_dry2: FTCPE port map (Inst_request/latched_dry(2),Inst_request/latched_dry_T(2),clk,'0','0');
Inst_request/latched_dry_T(2) <= ((NOT reset AND Inst_request/latched_dry(2))
OR (Inst_transfer_fsm/state_FFd5 AND
NOT Inst_transfer_fsm/state_FFd1 AND NOT Inst_transfer_fsm/state_FFd4 AND
NOT Inst_transfer_fsm/state_FFd3 AND NOT Inst_transfer_fsm/state_FFd2 AND
Inst_request/latched_dry(2) AND NOT Inst_request/synched_dry(2))
OR (NOT Inst_transfer_fsm/state_FFd5 AND
Inst_transfer_fsm/state_FFd1 AND Inst_transfer_fsm/state_FFd4 AND
NOT Inst_transfer_fsm/state_FFd3 AND NOT Inst_transfer_fsm/state_FFd2 AND
Inst_request/latched_dry(2) AND NOT Inst_request/synched_dry(2))
OR (reset AND Inst_transfer_fsm/state_FFd5 AND
NOT Inst_transfer_fsm/state_FFd1 AND NOT Inst_transfer_fsm/state_FFd4 AND
NOT Inst_transfer_fsm/state_FFd3 AND NOT Inst_transfer_fsm/state_FFd2 AND
NOT Inst_request/latched_dry(2) AND Inst_request/synched_dry(2))
OR (reset AND NOT Inst_transfer_fsm/state_FFd5 AND
Inst_transfer_fsm/state_FFd1 AND Inst_transfer_fsm/state_FFd4 AND
NOT Inst_transfer_fsm/state_FFd3 AND NOT Inst_transfer_fsm/state_FFd2 AND
NOT Inst_request/latched_dry(2) AND Inst_request/synched_dry(2)));
FTCPE_Inst_request/latched_dry3: FTCPE port map (Inst_request/latched_dry(3),Inst_request/latched_dry_T(3),clk,'0','0');
Inst_request/latched_dry_T(3) <= ((NOT reset AND Inst_request/latched_dry(3))
OR (Inst_transfer_fsm/state_FFd5 AND
NOT Inst_transfer_fsm/state_FFd1 AND NOT Inst_transfer_fsm/state_FFd4 AND
NOT Inst_transfer_fsm/state_FFd3 AND NOT Inst_transfer_fsm/state_FFd2 AND
Inst_request/latched_dry(3) AND NOT Inst_request/synched_dry(3))
OR (NOT Inst_transfer_fsm/state_FFd5 AND
Inst_transfer_fsm/state_FFd1 AND Inst_transfer_fsm/state_FFd4 AND
NOT Inst_transfer_fsm/state_FFd3 AND NOT Inst_transfer_fsm/state_FFd2 AND
Inst_request/latched_dry(3) AND NOT Inst_request/synched_dry(3))
OR (reset AND Inst_transfer_fsm/state_FFd5 AND
NOT Inst_transfer_fsm/state_FFd1 AND NOT Inst_transfer_fsm/state_FFd4 AND
NOT Inst_transfer_fsm/state_FFd3 AND NOT Inst_transfer_fsm/state_FFd2 AND
NOT Inst_request/latched_dry(3) AND Inst_request/synched_dry(3))
OR (reset AND NOT Inst_transfer_fsm/state_FFd5 AND
Inst_transfer_fsm/state_FFd1 AND Inst_transfer_fsm/state_FFd4 AND
NOT Inst_transfer_fsm/state_FFd3 AND NOT Inst_transfer_fsm/state_FFd2 AND
NOT Inst_request/latched_dry(3) AND Inst_request/synched_dry(3)));
FTCPE_Inst_request/synched_dry0: FTCPE port map (Inst_request/synched_dry(0),Inst_request/synched_dry_T(0),clk,'0','0');
Inst_request/synched_dry_T(0) <= ((NOT reset AND Inst_request/synched_dry(0))
OR (Inst_transfer_fsm/state_FFd5 AND
Inst_transfer_fsm/state_FFd1 AND NOT Inst_transfer_fsm/state_FFd4 AND
NOT Inst_transfer_fsm/state_FFd3 AND NOT Inst_transfer_fsm/state_FFd2 AND
Inst_request/synched_dry(0) AND NOT chn_sel_sig(0))
OR (Inst_transfer_fsm/state_FFd5 AND
NOT Inst_transfer_fsm/state_FFd1 AND NOT Inst_transfer_fsm/state_FFd4 AND
NOT Inst_transfer_fsm/state_FFd3 AND NOT Inst_transfer_fsm/state_FFd2 AND
Inst_request/synched_dry(0) AND NOT dry(0))
OR (reset AND Inst_transfer_fsm/state_FFd5 AND
NOT Inst_transfer_fsm/state_FFd1 AND NOT Inst_transfer_fsm/state_FFd4 AND
NOT Inst_transfer_fsm/state_FFd3 AND NOT Inst_transfer_fsm/state_FFd2 AND
NOT Inst_request/synched_dry(0) AND dry(0)));
FTCPE_Inst_request/synched_dry1: FTCPE port map (Inst_request/synched_dry(1),Inst_request/synched_dry_T(1),clk,'0','0');
Inst_request/synched_dry_T(1) <= ((NOT reset AND Inst_request/synched_dry(1))
OR (Inst_transfer_fsm/state_FFd5 AND
Inst_transfer_fsm/state_FFd1 AND NOT Inst_transfer_fsm/state_FFd4 AND
NOT Inst_transfer_fsm/state_FFd3 AND NOT Inst_transfer_fsm/state_FFd2 AND
Inst_request/synched_dry(1) AND NOT chn_sel_sig(1))
OR (Inst_transfer_fsm/state_FFd5 AND
NOT Inst_transfer_fsm/state_FFd1 AND NOT Inst_transfer_fsm/state_FFd4 AND
NOT Inst_transfer_fsm/state_FFd3 AND NOT Inst_transfer_fsm/state_FFd2 AND
Inst_request/synched_dry(1) AND NOT dry(1))
OR (reset AND Inst_transfer_fsm/state_FFd5 AND
NOT Inst_transfer_fsm/state_FFd1 AND NOT Inst_transfer_fsm/state_FFd4 AND
NOT Inst_transfer_fsm/state_FFd3 AND NOT Inst_transfer_fsm/state_FFd2 AND
NOT Inst_request/synched_dry(1) AND dry(1)));
FTCPE_Inst_request/synched_dry2: FTCPE port map (Inst_request/synched_dry(2),Inst_request/synched_dry_T(2),clk,'0','0');
Inst_request/synched_dry_T(2) <= ((NOT reset AND Inst_request/synched_dry(2))
OR (Inst_transfer_fsm/state_FFd5 AND
Inst_transfer_fsm/state_FFd1 AND NOT Inst_transfer_fsm/state_FFd4 AND
NOT Inst_transfer_fsm/state_FFd3 AND NOT Inst_transfer_fsm/state_FFd2 AND
Inst_request/synched_dry(2) AND NOT chn_sel_sig(2))
OR (Inst_transfer_fsm/state_FFd5 AND
NOT Inst_transfer_fsm/state_FFd1 AND NOT Inst_transfer_fsm/state_FFd4 AND
NOT Inst_transfer_fsm/state_FFd3 AND NOT Inst_transfer_fsm/state_FFd2 AND
Inst_request/synched_dry(2) AND NOT dry(2))
OR (reset AND Inst_transfer_fsm/state_FFd5 AND
NOT Inst_transfer_fsm/state_FFd1 AND NOT Inst_transfer_fsm/state_FFd4 AND
NOT Inst_transfer_fsm/state_FFd3 AND NOT Inst_transfer_fsm/state_FFd2 AND
NOT Inst_request/synched_dry(2) AND dry(2)));
FTCPE_Inst_request/synched_dry3: FTCPE port map (Inst_request/synched_dry(3),Inst_request/synched_dry_T(3),clk,'0','0');
Inst_request/synched_dry_T(3) <= ((NOT reset AND Inst_request/synched_dry(3))
OR (Inst_transfer_fsm/state_FFd5 AND
Inst_transfer_fsm/state_FFd1 AND NOT Inst_transfer_fsm/state_FFd4 AND
NOT Inst_transfer_fsm/state_FFd3 AND NOT Inst_transfer_fsm/state_FFd2 AND
Inst_request/synched_dry(3) AND NOT chn_sel_sig(3))
OR (Inst_transfer_fsm/state_FFd5 AND
NOT Inst_transfer_fsm/state_FFd1 AND NOT Inst_transfer_fsm/state_FFd4 AND
NOT Inst_transfer_fsm/state_FFd3 AND NOT Inst_transfer_fsm/state_FFd2 AND
Inst_request/synched_dry(3) AND NOT dry(3))
OR (reset AND Inst_transfer_fsm/state_FFd5 AND
NOT Inst_transfer_fsm/state_FFd1 AND NOT Inst_transfer_fsm/state_FFd4 AND
NOT Inst_transfer_fsm/state_FFd3 AND NOT Inst_transfer_fsm/state_FFd2 AND
NOT Inst_request/synched_dry(3) AND dry(3)));
FDCPE_Inst_transfer_fsm/clr_req_ovf: FDCPE port map (Inst_transfer_fsm/clr_req_ovf,Inst_transfer_fsm/clr_req_ovf_D,clk,'0','0');
Inst_transfer_fsm/clr_req_ovf_D <= ((NOT Inst_transfer_fsm/state_FFd5)
OR (NOT Inst_transfer_fsm/state_FFd1)
OR (Inst_transfer_fsm/state_FFd4)
OR (Inst_transfer_fsm/state_FFd3)
OR (Inst_transfer_fsm/state_FFd2)
OR (EXP20_.EXP)
OR (Inst_request/synched_dry(0).EXP));
FTCPE_Inst_transfer_fsm/data_tx_cnt0: FTCPE port map (Inst_transfer_fsm/data_tx_cnt(0),Inst_transfer_fsm/data_tx_cnt_T(0),clk,'0','0');
Inst_transfer_fsm/data_tx_cnt_T(0) <= ((EXP22_.EXP)
OR (Inst_transfer_fsm/state_FFd5 AND
NOT Inst_transfer_fsm/data_tx_cnt(0))
OR (Inst_transfer_fsm/state_FFd4 AND
NOT Inst_transfer_fsm/data_tx_cnt(0))
OR (Inst_transfer_fsm/state_FFd3 AND
NOT Inst_transfer_fsm/data_tx_cnt(0))
OR (Inst_transfer_fsm/state_FFd2 AND
NOT Inst_transfer_fsm/data_tx_cnt(0)));
FDCPE_Inst_transfer_fsm/data_tx_cnt1: FDCPE port map (Inst_transfer_fsm/data_tx_cnt(1),Inst_transfer_fsm/data_tx_cnt_D(1),clk,'0','0');
Inst_transfer_fsm/data_tx_cnt_D(1) <= ((Inst_transfer_fsm/state_FFd5)
OR (NOT Inst_transfer_fsm/state_FFd1)
OR (Inst_transfer_fsm/state_FFd4)
OR (Inst_transfer_fsm/state_FFd3)
OR (Inst_transfer_fsm/state_FFd2)
OR (EXP21_.EXP));
FDCPE_Inst_transfer_fsm/data_tx_cnt2: FDCPE port map (Inst_transfer_fsm/data_tx_cnt(2),Inst_transfer_fsm/data_tx_cnt_D(2),clk,'0','0');
Inst_transfer_fsm/data_tx_cnt_D(2) <= ((Inst_transfer_fsm/state_FFd5)
OR (NOT Inst_transfer_fsm/state_FFd1)
OR (Inst_transfer_fsm/state_FFd4)
OR (Inst_transfer_fsm/state_FFd3)
OR (Inst_transfer_fsm/state_FFd2)
OR (ebeam_oe_OBUF.EXP));
FDCPE_Inst_transfer_fsm/data_tx_cnt3: FDCPE port map (Inst_transfer_fsm/data_tx_cnt(3),Inst_transfer_fsm/data_tx_cnt_D(3),clk,'0','0');
Inst_transfer_fsm/data_tx_cnt_D(3) <= ((Inst_transfer_fsm/state_FFd5)
OR (NOT Inst_transfer_fsm/state_FFd1)
OR (Inst_transfer_fsm/state_FFd4)
OR (Inst_transfer_fsm/state_FFd3)
OR (Inst_transfer_fsm/state_FFd2)
OR (Inst_transfer_fsm/data_tx_ovf.EXP)
OR (ebeam_timer1_OBUF.EXP));
FTCPE_Inst_transfer_fsm/data_tx_cnt4: FTCPE port map (Inst_transfer_fsm/data_tx_cnt(4),Inst_transfer_fsm/data_tx_cnt_T(4),clk,'0','0');
Inst_transfer_fsm/data_tx_cnt_T(4) <= ((ebeam_loword_OBUF.EXP)
OR (Inst_transfer_fsm/state_FFd5 AND
Inst_transfer_fsm/data_tx_cnt(4))
OR (NOT Inst_transfer_fsm/state_FFd1 AND
Inst_transfer_fsm/data_tx_cnt(4))
OR (Inst_transfer_fsm/state_FFd4 AND
Inst_transfer_fsm/data_tx_cnt(4))
OR (Inst_transfer_fsm/state_FFd3 AND
Inst_transfer_fsm/data_tx_cnt(4))
OR (Inst_transfer_fsm/state_FFd2 AND
Inst_transfer_fsm/data_tx_cnt(4)));
FTCPE_Inst_transfer_fsm/data_tx_cnt5: FTCPE port map (Inst_transfer_fsm/data_tx_cnt(5),Inst_transfer_fsm/data_tx_cnt_T(5),clk,'0','0');
Inst_transfer_fsm/data_tx_cnt_T(5) <= ((ebeam_timer2_OBUF.EXP)
OR (Inst_transfer_fsm/state_FFd5 AND
Inst_transfer_fsm/data_tx_cnt(5))
OR (NOT Inst_transfer_fsm/state_FFd1 AND
Inst_transfer_fsm/data_tx_cnt(5))
OR (Inst_transfer_fsm/state_FFd4 AND
Inst_transfer_fsm/data_tx_cnt(5))
OR (Inst_transfer_fsm/state_FFd3 AND
Inst_transfer_fsm/data_tx_cnt(5))
OR (Inst_transfer_fsm/state_FFd2 AND
Inst_transfer_fsm/data_tx_cnt(5)));
FTCPE_Inst_transfer_fsm/data_tx_cnt6: FTCPE port map (Inst_transfer_fsm/data_tx_cnt(6),Inst_transfer_fsm/data_tx_cnt_T(6),clk,'0','0');
Inst_transfer_fsm/data_tx_cnt_T(6) <= ((EXP28_.EXP)
OR (Inst_transfer_fsm/state_FFd5 AND
Inst_transfer_fsm/data_tx_cnt(6))
OR (NOT Inst_transfer_fsm/state_FFd1 AND
Inst_transfer_fsm/data_tx_cnt(6))
OR (Inst_transfer_fsm/state_FFd4 AND
Inst_transfer_fsm/data_tx_cnt(6))
OR (Inst_transfer_fsm/state_FFd3 AND
Inst_transfer_fsm/data_tx_cnt(6))
OR (Inst_transfer_fsm/state_FFd2 AND
Inst_transfer_fsm/data_tx_cnt(6)));
FTCPE_Inst_transfer_fsm/data_tx_cnt7: FTCPE port map (Inst_transfer_fsm/data_tx_cnt(7),Inst_transfer_fsm/data_tx_cnt_T(7),clk,'0','0');
Inst_transfer_fsm/data_tx_cnt_T(7) <= ((EXP27_.EXP)
OR (Inst_transfer_fsm/state_FFd5 AND
Inst_transfer_fsm/data_tx_cnt(7))
OR (NOT Inst_transfer_fsm/state_FFd1 AND
Inst_transfer_fsm/data_tx_cnt(7))
OR (Inst_transfer_fsm/state_FFd4 AND
Inst_transfer_fsm/data_tx_cnt(7))
OR (Inst_transfer_fsm/state_FFd3 AND
Inst_transfer_fsm/data_tx_cnt(7))
OR (Inst_transfer_fsm/state_FFd2 AND
Inst_transfer_fsm/data_tx_cnt(7)));
FTCPE_Inst_transfer_fsm/data_tx_cnt8: FTCPE port map (Inst_transfer_fsm/data_tx_cnt(8),Inst_transfer_fsm/data_tx_cnt_T(8),clk,'0','0');
Inst_transfer_fsm/data_tx_cnt_T(8) <= ((EXP25_.EXP)
OR (Inst_transfer_fsm/state_FFd5 AND
Inst_transfer_fsm/data_tx_cnt(8))
OR (NOT Inst_transfer_fsm/state_FFd1 AND
Inst_transfer_fsm/data_tx_cnt(8))
OR (Inst_transfer_fsm/state_FFd4 AND
Inst_transfer_fsm/data_tx_cnt(8))
OR (Inst_transfer_fsm/state_FFd3 AND
Inst_transfer_fsm/data_tx_cnt(8))
OR (Inst_transfer_fsm/state_FFd2 AND
Inst_transfer_fsm/data_tx_cnt(8)));
FTCPE_Inst_transfer_fsm/data_tx_cnt9: FTCPE port map (Inst_transfer_fsm/data_tx_cnt(9),Inst_transfer_fsm/data_tx_cnt_T(9),clk,'0','0');
Inst_transfer_fsm/data_tx_cnt_T(9) <= ((EXP24_.EXP)
OR (NOT reset AND Inst_transfer_fsm/data_tx_cnt(9))
OR (Inst_transfer_fsm/data_tx_cnt(10) AND
Inst_transfer_fsm/data_tx_cnt(2) AND Inst_transfer_fsm/data_tx_cnt(4) AND
Inst_transfer_fsm/data_tx_cnt(5) AND Inst_transfer_fsm/data_tx_cnt(6) AND
Inst_transfer_fsm/data_tx_cnt(7) AND Inst_transfer_fsm/data_tx_cnt(8) AND
Inst_transfer_fsm/data_tx_cnt(9) AND Inst_transfer_fsm/data_tx_cnt(11))
OR (Inst_transfer_fsm/data_tx_cnt(10) AND
Inst_transfer_fsm/data_tx_cnt(3) AND Inst_transfer_fsm/data_tx_cnt(4) AND
Inst_transfer_fsm/data_tx_cnt(5) AND Inst_transfer_fsm/data_tx_cnt(6) AND
Inst_transfer_fsm/data_tx_cnt(7) AND Inst_transfer_fsm/data_tx_cnt(8) AND
Inst_transfer_fsm/data_tx_cnt(9) AND Inst_transfer_fsm/data_tx_cnt(11))
OR (Inst_transfer_fsm/data_tx_cnt(0) AND
Inst_transfer_fsm/data_tx_cnt(10) AND Inst_transfer_fsm/data_tx_cnt(1) AND
Inst_transfer_fsm/data_tx_cnt(4) AND Inst_transfer_fsm/data_tx_cnt(5) AND
Inst_transfer_fsm/data_tx_cnt(6) AND Inst_transfer_fsm/data_tx_cnt(7) AND
Inst_transfer_fsm/data_tx_cnt(8) AND Inst_transfer_fsm/data_tx_cnt(9) AND
Inst_transfer_fsm/data_tx_cnt(11))
OR (reset AND NOT Inst_transfer_fsm/state_FFd5 AND
Inst_transfer_fsm/state_FFd1 AND NOT Inst_transfer_fsm/state_FFd4 AND
NOT Inst_transfer_fsm/state_FFd3 AND NOT Inst_transfer_fsm/state_FFd2 AND
Inst_transfer_fsm/data_tx_cnt(0) AND Inst_transfer_fsm/data_tx_cnt(1) AND
Inst_transfer_fsm/data_tx_cnt(2) AND Inst_transfer_fsm/data_tx_cnt(3) AND
Inst_transfer_fsm/data_tx_cnt(4) AND Inst_transfer_fsm/data_tx_cnt(5) AND
Inst_transfer_fsm/data_tx_cnt(6) AND Inst_transfer_fsm/data_tx_cnt(7) AND
Inst_transfer_fsm/data_tx_cnt(8)));
FTCPE_Inst_transfer_fsm/data_tx_cnt10: FTCPE port map (Inst_transfer_fsm/data_tx_cnt(10),Inst_transfer_fsm/data_tx_cnt_T(10),clk,'0','0');
Inst_transfer_fsm/data_tx_cnt_T(10) <= ((timer_lower_OBUF.EXP)
OR (NOT reset AND Inst_transfer_fsm/data_tx_cnt(10))
OR (Inst_transfer_fsm/data_tx_cnt(10) AND
Inst_transfer_fsm/data_tx_cnt(2) AND Inst_transfer_fsm/data_tx_cnt(4) AND
Inst_transfer_fsm/data_tx_cnt(5) AND Inst_transfer_fsm/data_tx_cnt(6) AND
Inst_transfer_fsm/data_tx_cnt(7) AND Inst_transfer_fsm/data_tx_cnt(8) AND
Inst_transfer_fsm/data_tx_cnt(9) AND Inst_transfer_fsm/data_tx_cnt(11))
OR (Inst_transfer_fsm/data_tx_cnt(10) AND
Inst_transfer_fsm/data_tx_cnt(3) AND Inst_transfer_fsm/data_tx_cnt(4) AND
Inst_transfer_fsm/data_tx_cnt(5) AND Inst_transfer_fsm/data_tx_cnt(6) AND
Inst_transfer_fsm/data_tx_cnt(7) AND Inst_transfer_fsm/data_tx_cnt(8) AND
Inst_transfer_fsm/data_tx_cnt(9) AND Inst_transfer_fsm/data_tx_cnt(11))
OR (Inst_transfer_fsm/data_tx_cnt(0) AND
Inst_transfer_fsm/data_tx_cnt(10) AND Inst_transfer_fsm/data_tx_cnt(1) AND
Inst_transfer_fsm/data_tx_cnt(4) AND Inst_transfer_fsm/data_tx_cnt(5) AND
Inst_transfer_fsm/data_tx_cnt(6) AND Inst_transfer_fsm/data_tx_cnt(7) AND
Inst_transfer_fsm/data_tx_cnt(8) AND Inst_transfer_fsm/data_tx_cnt(9) AND
Inst_transfer_fsm/data_tx_cnt(11))
OR (reset AND NOT Inst_transfer_fsm/state_FFd5 AND
Inst_transfer_fsm/state_FFd1 AND NOT Inst_transfer_fsm/state_FFd4 AND
NOT Inst_transfer_fsm/state_FFd3 AND NOT Inst_transfer_fsm/state_FFd2 AND
Inst_transfer_fsm/data_tx_cnt(0) AND Inst_transfer_fsm/data_tx_cnt(1) AND
Inst_transfer_fsm/data_tx_cnt(2) AND Inst_transfer_fsm/data_tx_cnt(3) AND
Inst_transfer_fsm/data_tx_cnt(4) AND Inst_transfer_fsm/data_tx_cnt(5) AND
Inst_transfer_fsm/data_tx_cnt(6) AND Inst_transfer_fsm/data_tx_cnt(7) AND
Inst_transfer_fsm/data_tx_cnt(8) AND Inst_transfer_fsm/data_tx_cnt(9)));
FDCPE_Inst_transfer_fsm/data_tx_cnt11: FDCPE port map (Inst_transfer_fsm/data_tx_cnt(11),Inst_transfer_fsm/data_tx_cnt_D(11),clk,'0','0');
Inst_transfer_fsm/data_tx_cnt_D(11) <= ((timer_ndwc_OBUF.EXP)
OR (reset AND NOT Inst_transfer_fsm/state_FFd5 AND
Inst_transfer_fsm/state_FFd1 AND NOT Inst_transfer_fsm/state_FFd4 AND
NOT Inst_transfer_fsm/state_FFd3 AND NOT Inst_transfer_fsm/state_FFd2 AND
NOT Inst_transfer_fsm/data_tx_cnt(10) AND Inst_transfer_fsm/data_tx_cnt(11))
OR (reset AND NOT Inst_transfer_fsm/state_FFd5 AND
Inst_transfer_fsm/state_FFd1 AND NOT Inst_transfer_fsm/state_FFd4 AND
NOT Inst_transfer_fsm/state_FFd3 AND NOT Inst_transfer_fsm/state_FFd2 AND
NOT Inst_transfer_fsm/data_tx_cnt(4) AND Inst_transfer_fsm/data_tx_cnt(11))
OR (reset AND NOT Inst_transfer_fsm/state_FFd5 AND
Inst_transfer_fsm/state_FFd1 AND NOT Inst_transfer_fsm/state_FFd4 AND
NOT Inst_transfer_fsm/state_FFd3 AND NOT Inst_transfer_fsm/state_FFd2 AND
NOT Inst_transfer_fsm/data_tx_cnt(5) AND Inst_transfer_fsm/data_tx_cnt(11))
OR (reset AND NOT Inst_transfer_fsm/state_FFd5 AND
Inst_transfer_fsm/state_FFd1 AND NOT Inst_transfer_fsm/state_FFd4 AND
NOT Inst_transfer_fsm/state_FFd3 AND NOT Inst_transfer_fsm/state_FFd2 AND
NOT Inst_transfer_fsm/data_tx_cnt(6) AND Inst_transfer_fsm/data_tx_cnt(11))
OR (reset AND NOT Inst_transfer_fsm/state_FFd5 AND
Inst_transfer_fsm/state_FFd1 AND NOT Inst_transfer_fsm/state_FFd4 AND
NOT Inst_transfer_fsm/state_FFd3 AND NOT Inst_transfer_fsm/state_FFd2 AND
NOT Inst_transfer_fsm/data_tx_cnt(7) AND Inst_transfer_fsm/data_tx_cnt(11)));
FDCPE_Inst_transfer_fsm/data_tx_ovf: FDCPE port map (Inst_transfer_fsm/data_tx_ovf,Inst_transfer_fsm/data_tx_ovf_D,clk,'0','0');
Inst_transfer_fsm/data_tx_ovf_D <= ((reset AND NOT Inst_transfer_fsm/state_FFd5 AND
Inst_transfer_fsm/state_FFd1 AND NOT Inst_transfer_fsm/state_FFd4 AND
NOT Inst_transfer_fsm/state_FFd3 AND NOT Inst_transfer_fsm/state_FFd2 AND
Inst_transfer_fsm/data_tx_cnt(10) AND Inst_transfer_fsm/data_tx_cnt(2) AND
Inst_transfer_fsm/data_tx_cnt(4) AND Inst_transfer_fsm/data_tx_cnt(5) AND
Inst_transfer_fsm/data_tx_cnt(6) AND Inst_transfer_fsm/data_tx_cnt(7) AND
Inst_transfer_fsm/data_tx_cnt(8) AND Inst_transfer_fsm/data_tx_cnt(9) AND
Inst_transfer_fsm/data_tx_cnt(11))
OR (reset AND NOT Inst_transfer_fsm/state_FFd5 AND
Inst_transfer_fsm/state_FFd1 AND NOT Inst_transfer_fsm/state_FFd4 AND
NOT Inst_transfer_fsm/state_FFd3 AND NOT Inst_transfer_fsm/state_FFd2 AND
Inst_transfer_fsm/data_tx_cnt(10) AND Inst_transfer_fsm/data_tx_cnt(3) AND
Inst_transfer_fsm/data_tx_cnt(4) AND Inst_transfer_fsm/data_tx_cnt(5) AND
Inst_transfer_fsm/data_tx_cnt(6) AND Inst_transfer_fsm/data_tx_cnt(7) AND
Inst_transfer_fsm/data_tx_cnt(8) AND Inst_transfer_fsm/data_tx_cnt(9) AND
Inst_transfer_fsm/data_tx_cnt(11))
OR (reset AND NOT Inst_transfer_fsm/state_FFd5 AND
Inst_transfer_fsm/state_FFd1 AND NOT Inst_transfer_fsm/state_FFd4 AND
NOT Inst_transfer_fsm/state_FFd3 AND NOT Inst_transfer_fsm/state_FFd2 AND
Inst_transfer_fsm/data_tx_cnt(0) AND Inst_transfer_fsm/data_tx_cnt(10) AND
Inst_transfer_fsm/data_tx_cnt(1) AND Inst_transfer_fsm/data_tx_cnt(4) AND
Inst_transfer_fsm/data_tx_cnt(5) AND Inst_transfer_fsm/data_tx_cnt(6) AND
Inst_transfer_fsm/data_tx_cnt(7) AND Inst_transfer_fsm/data_tx_cnt(8) AND
Inst_transfer_fsm/data_tx_cnt(9) AND Inst_transfer_fsm/data_tx_cnt(11)));
FTCPE_Inst_transfer_fsm/state_FFd1: FTCPE port map (Inst_transfer_fsm/state_FFd1,Inst_transfer_fsm/state_FFd1_T,clk,NOT reset,'0');
Inst_transfer_fsm/state_FFd1_T <= ((Inst_transfer_fsm/state_FFd1 AND
NOT Inst_transfer_fsm/state_FFd4 AND enable)
OR (NOT Inst_transfer_fsm/state_FFd5 AND
Inst_transfer_fsm/state_FFd1 AND NOT Inst_transfer_fsm/state_FFd4 AND
Inst_transfer_fsm/state_FFd3)
OR (Inst_transfer_fsm/state_FFd5 AND
NOT Inst_transfer_fsm/state_FFd1 AND Inst_transfer_fsm/state_FFd4 AND
Inst_transfer_fsm/state_FFd3 AND NOT enable AND Inst_transfer_fsm/state_FFd2));
FTCPE_Inst_transfer_fsm/state_FFd2: FTCPE port map (Inst_transfer_fsm/state_FFd2,Inst_transfer_fsm/state_FFd2_T,clk,NOT reset,'0');
Inst_transfer_fsm/state_FFd2_T <= ((enable AND Inst_transfer_fsm/state_FFd2)
OR (Inst_transfer_fsm/state_FFd5 AND
Inst_transfer_fsm/state_FFd4 AND Inst_transfer_fsm/state_FFd3 AND NOT enable));
FDCPE_Inst_transfer_fsm/state_FFd3: FDCPE port map (Inst_transfer_fsm/state_FFd3,Inst_transfer_fsm/state_FFd3_D,clk,NOT reset,'0');
Inst_transfer_fsm/state_FFd3_D <= ((Inst_transfer_fsm/state_FFd4.EXP)
OR (Inst_transfer_fsm/state_FFd5 AND
Inst_transfer_fsm/state_FFd1 AND Inst_transfer_fsm/state_FFd4)
OR (Inst_transfer_fsm/state_FFd5 AND
NOT Inst_transfer_fsm/state_FFd4 AND Inst_transfer_fsm/state_FFd3 AND NOT enable)
OR (NOT Inst_transfer_fsm/state_FFd5 AND
NOT Inst_transfer_fsm/state_FFd1 AND Inst_transfer_fsm/state_FFd3 AND NOT enable)
OR (NOT Inst_transfer_fsm/state_FFd5 AND
Inst_transfer_fsm/state_FFd4 AND Inst_transfer_fsm/state_FFd3 AND NOT enable)
OR (NOT Inst_transfer_fsm/state_FFd5 AND
Inst_transfer_fsm/state_FFd3 AND NOT enable AND Inst_transfer_fsm/state_FFd2));
FDCPE_Inst_transfer_fsm/state_FFd4: FDCPE port map (Inst_transfer_fsm/state_FFd4,Inst_transfer_fsm/state_FFd4_D,clk,NOT reset,'0');
Inst_transfer_fsm/state_FFd4_D <= ((EXP18_.EXP)
OR (NOT Inst_transfer_fsm/state_FFd5 AND
Inst_transfer_fsm/state_FFd1 AND Inst_transfer_fsm/state_FFd4)
OR (NOT Inst_transfer_fsm/state_FFd5 AND
Inst_transfer_fsm/state_FFd4 AND NOT enable)
OR (Inst_transfer_fsm/state_FFd1 AND
Inst_transfer_fsm/state_FFd3 AND enable)
OR (Inst_transfer_fsm/state_FFd1 AND
Inst_transfer_fsm/state_FFd3 AND txreq_sig));
FDCPE_Inst_transfer_fsm/state_FFd5: FDCPE port map (Inst_transfer_fsm/state_FFd5,Inst_transfer_fsm/state_FFd5_D,clk,NOT reset,'0');
Inst_transfer_fsm/state_FFd5_D <= ((EXP19_.EXP)
OR (NOT Inst_transfer_fsm/state_FFd5 AND
Inst_transfer_fsm/state_FFd1 AND Inst_transfer_fsm/state_FFd4)
OR (NOT Inst_transfer_fsm/state_FFd5 AND
NOT Inst_transfer_fsm/state_FFd1 AND NOT enable)
OR (NOT Inst_transfer_fsm/state_FFd5 AND NOT enable AND
Inst_transfer_fsm/state_FFd2)
OR (NOT Inst_transfer_fsm/state_FFd5 AND
NOT Inst_transfer_fsm/state_FFd3 AND NOT enable AND NOT Inst_transfer_fsm/data_tx_ovf)
OR (Inst_transfer_fsm/state_FFd5 AND
Inst_transfer_fsm/state_FFd1 AND NOT Inst_transfer_fsm/state_FFd4 AND NOT enable AND
Inst_transfer_fsm/clr_req_ovf));
chn_ren(0) <= NOT ((NOT Inst_transfer_fsm/state_FFd5 AND
Inst_transfer_fsm/state_FFd1 AND NOT Inst_transfer_fsm/state_FFd4 AND
NOT Inst_transfer_fsm/state_FFd3 AND NOT Inst_transfer_fsm/state_FFd2 AND NOT chn_sel_sig(0)));
chn_ren(1) <= NOT ((NOT Inst_transfer_fsm/state_FFd5 AND
Inst_transfer_fsm/state_FFd1 AND NOT Inst_transfer_fsm/state_FFd4 AND
NOT Inst_transfer_fsm/state_FFd3 AND NOT Inst_transfer_fsm/state_FFd2 AND NOT chn_sel_sig(1)));
chn_ren(2) <= NOT ((NOT Inst_transfer_fsm/state_FFd5 AND
Inst_transfer_fsm/state_FFd1 AND NOT Inst_transfer_fsm/state_FFd4 AND
NOT Inst_transfer_fsm/state_FFd3 AND NOT Inst_transfer_fsm/state_FFd2 AND NOT chn_sel_sig(2)));
chn_ren(3) <= NOT ((NOT Inst_transfer_fsm/state_FFd5 AND
Inst_transfer_fsm/state_FFd1 AND NOT Inst_transfer_fsm/state_FFd4 AND
NOT Inst_transfer_fsm/state_FFd3 AND NOT Inst_transfer_fsm/state_FFd2 AND NOT chn_sel_sig(3)));
FDCPE_chn_sel_sig0: FDCPE port map (chn_sel_sig(0),chn_sel_sig_D(0),clk,'0','0');
chn_sel_sig_D(0) <= (NOT Inst_request/latched_dry(3) AND
NOT Inst_request/latched_dry(2) AND NOT Inst_request/latched_dry(1) AND
Inst_request/latched_dry(0));
FDCPE_chn_sel_sig1: FDCPE port map (chn_sel_sig(1),chn_sel_sig_D(1),clk,'0','0');
chn_sel_sig_D(1) <= (NOT Inst_request/latched_dry(3) AND
NOT Inst_request/latched_dry(2) AND Inst_request/latched_dry(1));
FDCPE_chn_sel_sig2: FDCPE port map (chn_sel_sig(2),chn_sel_sig_D(2),clk,'0','0');
chn_sel_sig_D(2) <= (NOT Inst_request/latched_dry(3) AND
Inst_request/latched_dry(2));
FDCPE_chn_sel_sig3: FDCPE port map (chn_sel_sig(3),NOT Inst_request/latched_dry(3),clk,'0','0');
ebeam_loword <= NOT (ebeam_upword_OBUF.EXP);
ebeam_oe <= NOT (EXP23_.EXP);
ebeam_timer1 <= NOT ((NOT Inst_transfer_fsm/state_FFd1 AND
NOT Inst_transfer_fsm/state_FFd4 AND NOT Inst_transfer_fsm/state_FFd3 AND
Inst_transfer_fsm/state_FFd2));
ebeam_timer2 <= NOT (Inst_transfer_fsm/data_tx_cnt(0).EXP);
ebeam_upword <= NOT ((NOT Inst_transfer_fsm/state_FFd5 AND
NOT Inst_transfer_fsm/state_FFd1 AND NOT Inst_transfer_fsm/state_FFd3 AND
Inst_transfer_fsm/state_FFd2));
rsdry(0) <= NOT (((NOT reset)
OR (Inst_transfer_fsm/state_FFd5 AND
Inst_transfer_fsm/state_FFd1 AND NOT Inst_transfer_fsm/state_FFd4 AND
NOT Inst_transfer_fsm/state_FFd3 AND NOT Inst_transfer_fsm/state_FFd2 AND NOT chn_sel_sig(0))));
rsdry(1) <= NOT (((NOT reset)
OR (Inst_transfer_fsm/state_FFd5 AND
Inst_transfer_fsm/state_FFd1 AND NOT Inst_transfer_fsm/state_FFd4 AND
NOT Inst_transfer_fsm/state_FFd3 AND NOT Inst_transfer_fsm/state_FFd2 AND NOT chn_sel_sig(1))));
rsdry(2) <= NOT (((NOT reset)
OR (Inst_transfer_fsm/state_FFd5 AND
Inst_transfer_fsm/state_FFd1 AND NOT Inst_transfer_fsm/state_FFd4 AND
NOT Inst_transfer_fsm/state_FFd3 AND NOT Inst_transfer_fsm/state_FFd2 AND NOT chn_sel_sig(2))));
rsdry(3) <= NOT (((NOT reset)
OR (Inst_transfer_fsm/state_FFd5 AND
Inst_transfer_fsm/state_FFd1 AND NOT Inst_transfer_fsm/state_FFd4 AND
NOT Inst_transfer_fsm/state_FFd3 AND NOT Inst_transfer_fsm/state_FFd2 AND NOT chn_sel_sig(3))));
timer_chnid <= NOT ((NOT Inst_transfer_fsm/state_FFd5 AND
NOT Inst_transfer_fsm/state_FFd1 AND NOT Inst_transfer_fsm/state_FFd4 AND
Inst_transfer_fsm/state_FFd3 AND NOT Inst_transfer_fsm/state_FFd2));
timer_dwc <= NOT ((Inst_transfer_fsm/state_FFd5 AND
NOT Inst_transfer_fsm/state_FFd1 AND NOT Inst_transfer_fsm/state_FFd4 AND
Inst_transfer_fsm/state_FFd3 AND Inst_transfer_fsm/state_FFd2));
timer_header <= NOT ((Inst_transfer_fsm/state_FFd5 AND
NOT Inst_transfer_fsm/state_FFd1 AND Inst_transfer_fsm/state_FFd4 AND
NOT Inst_transfer_fsm/state_FFd3 AND NOT Inst_transfer_fsm/state_FFd2));
timer_lower <= NOT (timer_upper_OBUF.EXP);
timer_ndwc <= NOT (timer_dwc_OBUF.EXP);
timer_oe(0) <= NOT (((Inst_transfer_fsm/state_FFd5 AND
NOT Inst_transfer_fsm/state_FFd1 AND NOT Inst_transfer_fsm/state_FFd4 AND
Inst_transfer_fsm/state_FFd3 AND NOT chn_sel_sig(0))
OR (NOT Inst_transfer_fsm/state_FFd5 AND
NOT Inst_transfer_fsm/state_FFd1 AND Inst_transfer_fsm/state_FFd4 AND
Inst_transfer_fsm/state_FFd3 AND NOT chn_sel_sig(0))
OR (NOT Inst_transfer_fsm/state_FFd1 AND
NOT Inst_transfer_fsm/state_FFd4 AND Inst_transfer_fsm/state_FFd3 AND
NOT Inst_transfer_fsm/state_FFd2 AND NOT chn_sel_sig(0))
OR (Inst_transfer_fsm/state_FFd5 AND
NOT Inst_transfer_fsm/state_FFd1 AND Inst_transfer_fsm/state_FFd4 AND
NOT Inst_transfer_fsm/state_FFd3 AND NOT Inst_transfer_fsm/state_FFd2 AND NOT chn_sel_sig(0))));
timer_oe(1) <= NOT (((Inst_transfer_fsm/state_FFd5 AND
NOT Inst_transfer_fsm/state_FFd1 AND NOT Inst_transfer_fsm/state_FFd4 AND
Inst_transfer_fsm/state_FFd3 AND NOT chn_sel_sig(1))
OR (NOT Inst_transfer_fsm/state_FFd5 AND
NOT Inst_transfer_fsm/state_FFd1 AND Inst_transfer_fsm/state_FFd4 AND
Inst_transfer_fsm/state_FFd3 AND NOT chn_sel_sig(1))
OR (NOT Inst_transfer_fsm/state_FFd1 AND
NOT Inst_transfer_fsm/state_FFd4 AND Inst_transfer_fsm/state_FFd3 AND
NOT Inst_transfer_fsm/state_FFd2 AND NOT chn_sel_sig(1))
OR (Inst_transfer_fsm/state_FFd5 AND
NOT Inst_transfer_fsm/state_FFd1 AND Inst_transfer_fsm/state_FFd4 AND
NOT Inst_transfer_fsm/state_FFd3 AND NOT Inst_transfer_fsm/state_FFd2 AND NOT chn_sel_sig(1))));
timer_oe(2) <= NOT (((Inst_transfer_fsm/state_FFd5 AND
NOT Inst_transfer_fsm/state_FFd1 AND NOT Inst_transfer_fsm/state_FFd4 AND
Inst_transfer_fsm/state_FFd3 AND NOT chn_sel_sig(2))
OR (NOT Inst_transfer_fsm/state_FFd5 AND
NOT Inst_transfer_fsm/state_FFd1 AND Inst_transfer_fsm/state_FFd4 AND
Inst_transfer_fsm/state_FFd3 AND NOT chn_sel_sig(2))
OR (NOT Inst_transfer_fsm/state_FFd1 AND
NOT Inst_transfer_fsm/state_FFd4 AND Inst_transfer_fsm/state_FFd3 AND
NOT Inst_transfer_fsm/state_FFd2 AND NOT chn_sel_sig(2))
OR (Inst_transfer_fsm/state_FFd5 AND
NOT Inst_transfer_fsm/state_FFd1 AND Inst_transfer_fsm/state_FFd4 AND
NOT Inst_transfer_fsm/state_FFd3 AND NOT Inst_transfer_fsm/state_FFd2 AND NOT chn_sel_sig(2))));
timer_oe(3) <= NOT (((Inst_transfer_fsm/state_FFd5 AND
NOT Inst_transfer_fsm/state_FFd1 AND NOT Inst_transfer_fsm/state_FFd4 AND
Inst_transfer_fsm/state_FFd3 AND NOT chn_sel_sig(3))
OR (NOT Inst_transfer_fsm/state_FFd5 AND
NOT Inst_transfer_fsm/state_FFd1 AND Inst_transfer_fsm/state_FFd4 AND
Inst_transfer_fsm/state_FFd3 AND NOT chn_sel_sig(3))
OR (NOT Inst_transfer_fsm/state_FFd1 AND
NOT Inst_transfer_fsm/state_FFd4 AND Inst_transfer_fsm/state_FFd3 AND
NOT Inst_transfer_fsm/state_FFd2 AND NOT chn_sel_sig(3))
OR (Inst_transfer_fsm/state_FFd5 AND
NOT Inst_transfer_fsm/state_FFd1 AND Inst_transfer_fsm/state_FFd4 AND
NOT Inst_transfer_fsm/state_FFd3 AND NOT Inst_transfer_fsm/state_FFd2 AND NOT chn_sel_sig(3))));
timer_upper <= NOT ((Inst_transfer_fsm/state_FFd5 AND
NOT Inst_transfer_fsm/state_FFd1 AND NOT Inst_transfer_fsm/state_FFd4 AND
Inst_transfer_fsm/state_FFd3 AND NOT Inst_transfer_fsm/state_FFd2));
FDCPE_txreq_sig: FDCPE port map (txreq_sig,txreq_sig_D,clk,'0','0');
txreq_sig_D <= ((NOT reset)
OR (NOT Inst_request/latched_dry(3) AND
NOT Inst_request/latched_dry(2) AND NOT Inst_request/latched_dry(1) AND
NOT Inst_request/latched_dry(0)));
wen4 <= NOT (((EXP26_.EXP)
OR (NOT Inst_transfer_fsm/state_FFd1 AND
NOT Inst_transfer_fsm/state_FFd3 AND Inst_transfer_fsm/state_FFd2)
OR (Inst_transfer_fsm/state_FFd5 AND
NOT Inst_transfer_fsm/state_FFd1 AND Inst_transfer_fsm/state_FFd4 AND
NOT Inst_transfer_fsm/state_FFd3)
OR (Inst_transfer_fsm/state_FFd5 AND
NOT Inst_transfer_fsm/state_FFd1 AND NOT Inst_transfer_fsm/state_FFd4 AND
Inst_transfer_fsm/state_FFd3)
OR (NOT Inst_transfer_fsm/state_FFd5 AND
NOT Inst_transfer_fsm/state_FFd1 AND Inst_transfer_fsm/state_FFd4 AND
Inst_transfer_fsm/state_FFd3)
OR (NOT Inst_transfer_fsm/state_FFd5 AND
NOT Inst_transfer_fsm/state_FFd1 AND Inst_transfer_fsm/state_FFd3 AND
NOT Inst_transfer_fsm/state_FFd2)));
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE);
FTCPE (Q,D,C,CLR,PRE,CE);
LDCP (Q,D,G,CLR,PRE);
****************************** Device Pin Out *****************************
Device : XC95288XL-6-TQ144
Pin Signal Pin Signal
No. Name No. Name
1 VCC 73 VCC
2 KPR 74 KPR
3 rsdry<0> 75 KPR
4 rsdry<1> 76 KPR
5 rsdry<2> 77 KPR
6 rsdry<3> 78 KPR
7 KPR 79 KPR
8 VCC 80 KPR
9 dry<0> 81 KPR
10 dry<1> 82 KPR
11 dry<2> 83 KPR
12 dry<3> 84 VCC
13 chn_ren<0> 85 KPR
14 chn_ren<1> 86 KPR
15 chn_ren<2> 87 KPR
16 chn_ren<3> 88 KPR
17 KPR 89 GND
18 GND 90 GND
19 KPR 91 KPR
20 KPR 92 KPR
21 KPR 93 KPR
22 KPR 94 KPR
23 KPR 95 KPR
24 KPR 96 KPR
25 KPR 97 KPR
26 KPR 98 KPR
27 KPR 99 GND
28 KPR 100 KPR
29 GND 101 KPR
30 clk 102 KPR
31 KPR 103 KPR
32 KPR 104 KPR
33 KPR 105 KPR
34 KPR 106 KPR
35 KPR 107 KPR
36 GND 108 GND
37 VCC 109 VCC
38 KPR 110 KPR
39 KPR 111 KPR
40 KPR 112 KPR
41 KPR 113 KPR
42 VCC 114 GND
43 timer_oe<0> 115 KPR
44 timer_oe<1> 116 KPR
45 timer_oe<2> 117 KPR
46 timer_oe<3> 118 KPR
47 GND 119 KPR
48 timer_header 120 KPR
49 timer_chnid 121 KPR
50 timer_upper 122 TDO
51 timer_lower 123 GND
52 timer_dwc 124 KPR
53 timer_ndwc 125 KPR
54 KPR 126 KPR
55 VCC 127 VCC
56 ebeam_loword 128 KPR
57 ebeam_upword 129 KPR
58 ebeam_timer2 130 KPR
59 ebeam_timer1 131 KPR
60 ebeam_oe 132 KPR
61 KPR 133 KPR
62 GND 134 KPR
63 TDI 135 KPR
64 KPR 136 KPR
65 TMS 137 KPR
66 KPR 138 KPR
67 TCK 139 KPR
68 KPR 140 KPR
69 wen4 141 VCC
70 KPR 142 enable
71 KPR 143 reset
72 GND 144 GND
Legend : NC = Not Connected, unbonded pin
PGND = Unused I/O configured as additional Ground pin
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
KPR = Unused I/O with weak keeper (leave unconnected)
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : xc95288xl-6-TQ144
Optimization Method : SPEED
Multi-Level Logic Optimization : ON
Ignore Timing Specifications : OFF
Default Register Power Up Value : LOW
Keep User Location Constraints : ON
What-You-See-Is-What-You-Get : OFF
Exhaustive Fitting : OFF
Keep Unused Inputs : OFF
Slew Rate : FAST
Power Mode : STD
Ground on Unused IOs : OFF
Set I/O Pin Termination : KEEPER
Global Clock Optimization : ON
Global Set/Reset Optimization : ON
Global Ouput Enable Optimization : ON
Input Limit : 54
Pterm Limit : 25