LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

ENTITY chn2syst IS
    PORT (reset        : IN  STD_LOGIC;
          clk          : IN  STD_LOGIC;
          enable       : IN  STD_LOGIC;
          dry          : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);  -- Data Ready       -- ACTIVE HIGH
          rsdry        : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);  -- Reset Data Ready --                          
          timer_oe     : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);  -- sel chn/output buffer
          timer_header : OUT STD_LOGIC;  -- mux sel  header
          timer_chnid  : OUT STD_LOGIC;  -- mux sel  channel addr
          timer_upper  : OUT STD_LOGIC;  -- mux sel  timer msb
          timer_lower  : OUT STD_LOGIC;  -- mux sel  timer msb
          timer_dwc    : OUT STD_LOGIC;  -- mux sel  decimation word count
          timer_ndwc   : OUT STD_LOGIC;  -- mux sel  non decimation word count                 
          ebeam_oe     : OUT STD_LOGIC;  -- sel chn/output buffer
          ebeam_timer1 : OUT STD_LOGIC;  -- mux sel  header
          ebeam_timer2 : OUT STD_LOGIC;  -- mux sel  channel addr
          ebeam_upword : OUT STD_LOGIC;  -- mux sel  timer msb
          ebeam_loword : OUT STD_LOGIC;  -- mux sel  timer msb
          chn_ren      : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);  -- sel chn/output buffer  
          wen4         : OUT STD_LOGIC  -- 
          );
END chn2syst;

ARCHITECTURE Behavioral OF chn2syst IS
----------------------------------------------------------------
-- Components
----------------------------------------------------------------
    COMPONENT request
        PORT(
            reset     : IN  STD_LOGIC;
            clk       : IN  STD_LOGIC;
            dataready : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
            latchen1  : IN  STD_LOGIC;
            latchen2  : IN  STD_LOGIC;
            clr_req   : IN  STD_LOGIC;
            chn_sel   : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
            txreq     : OUT STD_LOGIC
            );
    END COMPONENT;

    COMPONENT transfer_fsm
        PORT(
            reset        : IN  STD_LOGIC;
            clk          : IN  STD_LOGIC;
            enable       : IN  STD_LOGIC;
            txreq        : IN  STD_LOGIC;
            dataready    : IN  STD_LOGIC;  -- added for handshake with channel
                                           -- control CPLD
            latchen1     : OUT STD_LOGIC;
            latchen2     : OUT STD_LOGIC;
            timer_oe     : OUT STD_LOGIC;
            timer_header : OUT STD_LOGIC;
            timer_chnid  : OUT STD_LOGIC;
            timer_upper  : OUT STD_LOGIC;
            timer_lower  : OUT STD_LOGIC;
            timer_dwc    : OUT STD_LOGIC;
            timer_ndwc   : OUT STD_LOGIC;
            ebeam_oe     : OUT STD_LOGIC;
            ebeam_timer1 : OUT STD_LOGIC;
            ebeam_timer2 : OUT STD_LOGIC;
            ebeam_upword : OUT STD_LOGIC;
            ebeam_loword : OUT STD_LOGIC;
            chn_data_ren : OUT STD_LOGIC;
            clr_req      : OUT STD_LOGIC;
            wen4         : OUT STD_LOGIC
            );
    END COMPONENT;

----------------------------------------------------------------
-- Signals
----------------------------------------------------------------
    SIGNAL chn_data_ren_sig : STD_LOGIC;
    SIGNAL chn_sel_sig      : STD_LOGIC_VECTOR (3 DOWNTO 0);
    SIGNAL clr_req_sig      : STD_LOGIC;
    SIGNAL timer_oe_sig     : STD_LOGIC;
    SIGNAL txreq_sig        : STD_LOGIC;
    SIGNAL latchen1_sig     : STD_LOGIC;
    SIGNAL latchen2_sig     : STD_LOGIC;
    SIGNAL dataready        : STD_LOGIC;  -- for channel handshake

----------------------------------------------------------------
-- Architecture's description
----------------------------------------------------------------
BEGIN

    Inst_request : request PORT MAP(
        reset     => reset,
        clk       => clk,
        dataready => dry,
        latchen1  => latchen1_sig,
        latchen2  => latchen2_sig,
        clr_req   => clr_req_sig,
        chn_sel   => chn_sel_sig,
        txreq     => txreq_sig
        );


    Inst_transfer_fsm : transfer_fsm PORT MAP(
        reset        => reset,
        clk          => clk,
        enable       => enable,
        txreq        => txreq_sig,
        dataready    => dataready,
        latchen1     => latchen1_sig,
        latchen2     => latchen2_sig,
        timer_oe     => timer_oe_sig,
        timer_header => timer_header,
        timer_chnid  => timer_chnid,
        timer_upper  => timer_upper,
        timer_lower  => timer_lower,
        timer_dwc    => timer_dwc,
        timer_ndwc   => timer_ndwc,
        ebeam_oe     => ebeam_oe,
        ebeam_timer1 => ebeam_timer1,
        ebeam_timer2 => ebeam_timer2,
        ebeam_upword => ebeam_upword,
        ebeam_loword => ebeam_loword,
        chn_data_ren => chn_data_ren_sig,
        clr_req      => clr_req_sig,
        wen4         => wen4
        );

    rsdry(0) <= (reset AND (chn_sel_sig(0) OR clr_req_sig));
    rsdry(1) <= (reset AND (chn_sel_sig(1) OR clr_req_sig));
    rsdry(2) <= (reset AND (chn_sel_sig(2) OR clr_req_sig));
    rsdry(3) <= (reset AND (chn_sel_sig(3) OR clr_req_sig));

    chn_ren(0) <= (chn_sel_sig(0) OR chn_data_ren_sig);
    chn_ren(1) <= (chn_sel_sig(1) OR chn_data_ren_sig);
    chn_ren(2) <= (chn_sel_sig(2) OR chn_data_ren_sig);
    chn_ren(3) <= (chn_sel_sig(3) OR chn_data_ren_sig);

    timer_oe(0) <= (chn_sel_sig(0) OR timer_oe_sig);
    timer_oe(1) <= (chn_sel_sig(1) OR timer_oe_sig);
    timer_oe(2) <= (chn_sel_sig(2) OR timer_oe_sig);
    timer_oe(3) <= (chn_sel_sig(3) OR timer_oe_sig);

    dataready <= '1' WHEN (dry(0) = '1' AND chn_sel_sig(0) = '0')
                 OR (dry(1) = '1' AND chn_sel_sig(1) = '0')
                 OR (dry(2) = '1' AND chn_sel_sig(2) = '0')
                 OR (dry(3) = '1' AND chn_sel_sig(3) = '0') ELSE '0';

END Behavioral;