Release 8.2i - xst I.31 Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to ./xst/projnav.tmp CPU : 0.00 / 0.30 s | Elapsed : 0.00 / 0.00 s --> Parameter xsthdpdir set to ./xst CPU : 0.00 / 0.30 s | Elapsed : 0.00 / 0.00 s --> Reading design: chn2syst.prj TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) Design Hierarchy Analysis 4) HDL Analysis 5) HDL Synthesis 5.1) HDL Synthesis Report 6) Advanced HDL Synthesis 6.1) Advanced HDL Synthesis Report 7) Low Level Synthesis 8) Partition Report 9) Final Report ========================================================================= * Synthesis Options Summary * ========================================================================= ---- Source Parameters Input File Name : "chn2syst.prj" Input Format : mixed Ignore Synthesis Constraint File : NO ---- Target Parameters Output File Name : "chn2syst" Output Format : NGC Target Device : XC9500XL CPLDs ---- Source Options Top Module Name : chn2syst Automatic FSM Extraction : YES FSM Encoding Algorithm : Auto Mux Extraction : YES Resource Sharing : YES ---- Target Options Add IO Buffers : YES MACRO Preserve : YES XOR Preserve : YES Equivalent register Removal : YES ---- General Options Optimization Goal : Speed Optimization Effort : 1 Keep Hierarchy : YES RTL Output : Yes Hierarchy Separator : / Bus Delimiter : <> Case Specifier : maintain ---- Other Options lso : chn2syst.lso verilog2001 : YES safe_implementation : No Clock Enable : YES wysiwyg : NO ========================================================================= ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file "//engfile3/ddoering/Projects/SAO/VHDL/chn2syst/sdffen.vhd" in Library work. Architecture behavioral of Entity sdffen is up to date. Compiling vhdl file "//engfile3/ddoering/Projects/SAO/VHDL/chn2syst/sdff.vhd" in Library work. Architecture behavioral of Entity sdff is up to date. Compiling vhdl file "//engfile3/ddoering/Projects/SAO/VHDL/chn2syst/priority.vhd" in Library work. Architecture behavioral of Entity priority is up to date. Compiling vhdl file "//engfile3/ddoering/Projects/SAO/VHDL/chn2syst/request.vhd" in Library work. Architecture behavioral of Entity request is up to date. Compiling vhdl file "//engfile3/ddoering/Projects/SAO/VHDL/chn2syst/transfer_fsm.vhd" in Library work. Entity compiled. Entity (Architecture ) compiled. Compiling vhdl file "//engfile3/ddoering/Projects/SAO/VHDL/chn2syst/chn2syst.vhd" in Library work. Architecture behavioral of Entity chn2syst is up to date. ========================================================================= * Design Hierarchy Analysis * ========================================================================= Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Building hierarchy successfully finished. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Set property "ENUM_ENCODING = 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100" for signal . Set property "ENUM_ENCODING = 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100" for signal . Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Performing bidirectional port resolution... Synthesizing Unit . Related source file is "//engfile3/ddoering/Projects/SAO/VHDL/chn2syst/transfer_fsm.vhd". Found finite state machine for signal . ----------------------------------------------------------------------- | States | 21 | | Transitions | 44 | | Inputs | 4 | | Outputs | 17 | | Clock | clk (rising_edge) | | Reset | reset (negative) | | Reset type | asynchronous | | Reset State | s0 | | Power Up State | s0 | | Encoding | automatic | | Implementation | automatic | ----------------------------------------------------------------------- Found 12-bit comparator greatequal for signal <$cmp_ge0000> created at line 747. Found 12-bit comparator less for signal <$cmp_lt0000> created at line 747. Found 5-bit up counter for signal . Found 1-bit register for signal . Found 12-bit up counter for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 2 Counter(s). inferred 2 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is "//engfile3/ddoering/Projects/SAO/VHDL/chn2syst/sdffen.vhd". Found 1-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is "//engfile3/ddoering/Projects/SAO/VHDL/chn2syst/sdff.vhd". Found 1-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is "//engfile3/ddoering/Projects/SAO/VHDL/chn2syst/priority.vhd". Found 4-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is "//engfile3/ddoering/Projects/SAO/VHDL/chn2syst/request.vhd". Unit synthesized. Synthesizing Unit . Related source file is "//engfile3/ddoering/Projects/SAO/VHDL/chn2syst/chn2syst.vhd". Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # Counters : 2 12-bit up counter : 1 5-bit up counter : 1 # Registers : 12 1-bit register : 11 4-bit register : 1 # Comparators : 2 12-bit comparator greatequal : 1 12-bit comparator less : 1 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Analyzing FSM for best encoding. Optimizing FSM on signal with sequential encoding. ------------------- State | Encoding ------------------- s0 | 00000 s1 | 00001 s2 | 00010 s3 | 00011 s4 | 00100 s5 | 00101 s6 | 00110 s7 | 00111 s8 | 01000 s9 | 01001 s10 | 01010 s11 | 01011 s12 | 01100 s13 | 01101 s14 | 01110 s15 | 01111 s16 | 10000 s17 | 10001 s18 | 10010 s19 | 10011 s20 | 10100 ------------------- ========================================================================= Advanced HDL Synthesis Report Macro Statistics # FSMs : 1 # Counters : 2 12-bit up counter : 1 5-bit up counter : 1 # Registers : 26 Flip-Flops : 26 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... implementation constraint: INIT=r : state_FFd5 implementation constraint: INIT=r : data_tx_cnt_0 implementation constraint: INIT=r : state_FFd4 implementation constraint: INIT=r : state_FFd3 implementation constraint: INIT=r : state_FFd2 implementation constraint: INIT=r : state_FFd1 implementation constraint: INIT=r : data_tx_cnt_11 implementation constraint: INIT=r : data_tx_cnt_10 implementation constraint: INIT=r : data_tx_cnt_9 implementation constraint: INIT=r : data_tx_cnt_8 implementation constraint: INIT=r : data_tx_cnt_7 implementation constraint: INIT=r : data_tx_cnt_6 implementation constraint: INIT=r : data_tx_cnt_5 implementation constraint: INIT=r : data_tx_cnt_4 implementation constraint: INIT=r : data_tx_cnt_3 implementation constraint: INIT=r : data_tx_cnt_2 implementation constraint: INIT=r : data_tx_cnt_1 Optimizing unit ... Optimizing unit ... ========================================================================= * Partition Report * ========================================================================= Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- ========================================================================= * Final Report * ========================================================================= Final Results RTL Top Level Output File Name : chn2syst.ngr Top Level Output File Name : chn2syst Output Format : NGC Optimization Goal : Speed Keep Hierarchy : YES Target Technology : XC9500XL CPLDs Macro Preserve : YES XOR Preserve : YES Clock Enable : YES wysiwyg : NO Design Statistics # IOs : 31 Cell Usage : # BELS : 355 # AND2 : 80 # AND3 : 9 # AND4 : 2 # AND8 : 1 # GND : 8 # INV : 134 # OR2 : 88 # OR3 : 15 # OR4 : 7 # XOR2 : 11 # FlipFlops/Latches : 32 # FD : 19 # FDC : 5 # FDCE : 8 # IO Buffers : 31 # IBUF : 7 # OBUF : 24 ========================================================================= CPU : 10.91 / 11.22 s | Elapsed : 11.00 / 11.00 s --> Total memory usage is 114964 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 5 ( 0 filtered) Number of infos : 0 ( 0 filtered)