version 3
U:/Projects/SAO/VHDL/SAO8_2/top.vhd
top
VHDL
VHDL
top_tb0.xwv
Clocked
-
-
100000000000
ns
GSR:true
PRLD:false
100000000
CLOCK_LIST_BEGIN
clk
10000000
10000000
5000000
5000000
100000000
RISING
CLOCK_LIST_END
SIGNAL_LIST_BEGIN
ACK1
clk
ACK2
clk
CTRL
clk
D
clk
DATAOK
clk
DIOA
clk
DIOB
clk
DIOC
clk
DIOD
clk
EFn
clk
FFn
clk
FIFO_D
clk
FIFO_Q
clk
HFn
clk
OEn
clk
PCLK1
clk
PCLK2
clk
RCLK
clk
RENn
clk
REQ1
clk
REQ2
clk
RSTn
clk
RXDATA
clk
RXERROR
clk
RXREADY
clk
SPARE
clk
STOPTRIG1
clk
STOPTRIG2
clk
WCLK
clk
WENn
clk
rst
clk
SIGNAL_LIST_END
SIGNALS_NOT_ON_DISPLAY
CTRL_DIFF
DIOC_DIFF
DIOD_DIFF
FIFO_D_DIFF
OEn_DIFF
RCLK_DIFF
RENn_DIFF
REQ1_DIFF
REQ2_DIFF
RSTn_DIFF
STOPTRIG1_DIFF
STOPTRIG2_DIFF
WCLK_DIFF
WENn_DIFF
SIGNALS_NOT_ON_DISPLAY_END
MARKER_LIST_BEGIN
1165956607
MARKER_LIST_END
MEASURE_LIST_BEGIN
MEASURE_LIST_END
SIGNAL_ORDER_BEGIN
clk
ACK1
ACK2
DATAOK
EFn
FFn
HFn
PCLK1
PCLK2
RXDATA
RXERROR
RXREADY
rst
D
DIOA
DIOB
FIFO_Q
CTRL
OEn
RCLK
RENn
REQ1
REQ2
RSTn
STOPTRIG1
STOPTRIG2
WCLK
WENn
DIOC
DIOD
FIFO_D
SPARE
SIGNAL_ORDER_END
-X-X-X-