-------------------------------------------------------------------------------- -- Copyright (c) 1995-2003 Xilinx, Inc. -- All Right Reserved. -------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version : 8.2i -- \ \ Application : ISE -- / / Filename : top_tb0.ant -- /___/ /\ Timestamp : Fri Jan 12 10:33:32 2007 -- \ \ / \ -- \___\/\___\ -- --Command: --Design Name: top_tb0 --Device: Xilinx -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_TEXTIO.ALL; USE STD.TEXTIO.ALL; ENTITY top_tb0 IS END top_tb0; ARCHITECTURE testbench_arch OF top_tb0 IS FILE RESULTS: TEXT OPEN WRITE_MODE IS "\\engfile3\ddoering\Projects\SAO\VHDL\sao8_1v8_2\top_tb0.ano"; COMPONENT top PORT ( clk : In std_logic; rst : In std_logic; DIOA : In std_logic_vector (7 DownTo 0); DIOB : In std_logic_vector (7 DownTo 0); DIOC : Out std_logic_vector (7 DownTo 0); DIOD : Out std_logic_vector (7 DownTo 0); PCLK1 : In std_logic; STOPTRIG1 : Out std_logic; REQ1 : Out std_logic; ACK1 : In std_logic; PCLK2 : In std_logic; STOPTRIG2 : Out std_logic; REQ2 : Out std_logic; ACK2 : In std_logic; SPARE : InOut std_logic_vector (12 DownTo 0); D : In std_logic_vector (15 DownTo 0); DATAOK : In std_logic; RXREADY : In std_logic; RXDATA : In std_logic; RXERROR : In std_logic; CTRL : Out std_logic; FIFO_Q : In std_logic_vector (15 DownTo 0); FIFO_D : Out std_logic_vector (15 DownTo 0); FFn : In std_logic; HFn : In std_logic; EFn : In std_logic; WCLK : Out std_logic; WENn : Out std_logic; RSTn : Out std_logic; RCLK : Out std_logic; RENn : Out std_logic; OEn : Out std_logic ); END COMPONENT; SIGNAL clk : std_logic := '0'; SIGNAL rst : std_logic := '1'; SIGNAL DIOA : std_logic_vector (7 DownTo 0) := "00000000"; SIGNAL DIOB : std_logic_vector (7 DownTo 0) := "00000000"; SIGNAL DIOC : std_logic_vector (7 DownTo 0) := "00000000"; SIGNAL DIOD : std_logic_vector (7 DownTo 0) := "00000000"; SIGNAL PCLK1 : std_logic := '0'; SIGNAL STOPTRIG1 : std_logic := '0'; SIGNAL REQ1 : std_logic := '0'; SIGNAL ACK1 : std_logic := '0'; SIGNAL PCLK2 : std_logic := '0'; SIGNAL STOPTRIG2 : std_logic := '0'; SIGNAL REQ2 : std_logic := '0'; SIGNAL ACK2 : std_logic := '0'; SIGNAL SPARE : std_logic_vector (12 DownTo 0) := "0000000000000"; SIGNAL D : std_logic_vector (15 DownTo 0) := "0000000000000000"; SIGNAL DATAOK : std_logic := '0'; SIGNAL RXREADY : std_logic := '0'; SIGNAL RXDATA : std_logic := '0'; SIGNAL RXERROR : std_logic := '0'; SIGNAL CTRL : std_logic := '0'; SIGNAL FIFO_Q : std_logic_vector (15 DownTo 0) := "0000000000000000"; SIGNAL FIFO_D : std_logic_vector (15 DownTo 0) := "0000000000000000"; SIGNAL FFn : std_logic := '0'; SIGNAL HFn : std_logic := '0'; SIGNAL EFn : std_logic := '0'; SIGNAL WCLK : std_logic := '0'; SIGNAL WENn : std_logic := '0'; SIGNAL RSTn : std_logic := '0'; SIGNAL RCLK : std_logic := '0'; SIGNAL RENn : std_logic := '0'; SIGNAL OEn : std_logic := '0'; SHARED VARIABLE TX_ERROR : INTEGER := 0; SHARED VARIABLE TX_OUT : LINE; constant PERIOD : time := 20 ns; constant DUTY_CYCLE : real := 0.5; constant OFFSET : time := 100 ns; BEGIN UUT : top PORT MAP ( clk => clk, rst => rst, DIOA => DIOA, DIOB => DIOB, DIOC => DIOC, DIOD => DIOD, PCLK1 => PCLK1, STOPTRIG1 => STOPTRIG1, REQ1 => REQ1, ACK1 => ACK1, PCLK2 => PCLK2, STOPTRIG2 => STOPTRIG2, REQ2 => REQ2, ACK2 => ACK2, SPARE => SPARE, D => D, DATAOK => DATAOK, RXREADY => RXREADY, RXDATA => RXDATA, RXERROR => RXERROR, CTRL => CTRL, FIFO_Q => FIFO_Q, FIFO_D => FIFO_D, FFn => FFn, HFn => HFn, EFn => EFn, WCLK => WCLK, WENn => WENn, RSTn => RSTn, RCLK => RCLK, RENn => RENn, OEn => OEn ); PROCESS -- clock process for clk BEGIN WAIT for OFFSET; CLOCK_LOOP : LOOP clk <= '0'; WAIT FOR (PERIOD - (PERIOD * DUTY_CYCLE)); clk <= '1'; WAIT FOR (PERIOD * DUTY_CYCLE); END LOOP CLOCK_LOOP; END PROCESS; PROCESS -- Annotation process for clk VARIABLE TX_TIME : INTEGER := 0; PROCEDURE ANNOTATE_DIOC( TX_TIME : INTEGER ) IS VARIABLE TX_STR : String(1 to 4096); VARIABLE TX_LOC : LINE; BEGIN STD.TEXTIO.write(TX_LOC, string'("Annotate[")); STD.TEXTIO.write(TX_LOC, TX_TIME); STD.TEXTIO.write(TX_LOC, string'(", DIOC, ")); IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, DIOC); STD.TEXTIO.write(TX_LOC, string'("]")); TX_STR(TX_LOC.all'range) := TX_LOC.all; STD.TEXTIO.writeline(RESULTS, TX_LOC); STD.TEXTIO.Deallocate(TX_LOC); END; PROCEDURE ANNOTATE_DIOD( TX_TIME : INTEGER ) IS VARIABLE TX_STR : String(1 to 4096); VARIABLE TX_LOC : LINE; BEGIN STD.TEXTIO.write(TX_LOC, string'("Annotate[")); STD.TEXTIO.write(TX_LOC, TX_TIME); STD.TEXTIO.write(TX_LOC, string'(", DIOD, ")); IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, DIOD); STD.TEXTIO.write(TX_LOC, string'("]")); TX_STR(TX_LOC.all'range) := TX_LOC.all; STD.TEXTIO.writeline(RESULTS, TX_LOC); STD.TEXTIO.Deallocate(TX_LOC); END; PROCEDURE ANNOTATE_STOPTRIG1( TX_TIME : INTEGER ) IS VARIABLE TX_STR : String(1 to 4096); VARIABLE TX_LOC : LINE; BEGIN STD.TEXTIO.write(TX_LOC, string'("Annotate[")); STD.TEXTIO.write(TX_LOC, TX_TIME); STD.TEXTIO.write(TX_LOC, string'(", STOPTRIG1, ")); IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, STOPTRIG1); STD.TEXTIO.write(TX_LOC, string'("]")); TX_STR(TX_LOC.all'range) := TX_LOC.all; STD.TEXTIO.writeline(RESULTS, TX_LOC); STD.TEXTIO.Deallocate(TX_LOC); END; PROCEDURE ANNOTATE_REQ1( TX_TIME : INTEGER ) IS VARIABLE TX_STR : String(1 to 4096); VARIABLE TX_LOC : LINE; BEGIN STD.TEXTIO.write(TX_LOC, string'("Annotate[")); STD.TEXTIO.write(TX_LOC, TX_TIME); STD.TEXTIO.write(TX_LOC, string'(", REQ1, ")); IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, REQ1); STD.TEXTIO.write(TX_LOC, string'("]")); TX_STR(TX_LOC.all'range) := TX_LOC.all; STD.TEXTIO.writeline(RESULTS, TX_LOC); STD.TEXTIO.Deallocate(TX_LOC); END; PROCEDURE ANNOTATE_STOPTRIG2( TX_TIME : INTEGER ) IS VARIABLE TX_STR : String(1 to 4096); VARIABLE TX_LOC : LINE; BEGIN STD.TEXTIO.write(TX_LOC, string'("Annotate[")); STD.TEXTIO.write(TX_LOC, TX_TIME); STD.TEXTIO.write(TX_LOC, string'(", STOPTRIG2, ")); IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, STOPTRIG2); STD.TEXTIO.write(TX_LOC, string'("]")); TX_STR(TX_LOC.all'range) := TX_LOC.all; STD.TEXTIO.writeline(RESULTS, TX_LOC); STD.TEXTIO.Deallocate(TX_LOC); END; PROCEDURE ANNOTATE_REQ2( TX_TIME : INTEGER ) IS VARIABLE TX_STR : String(1 to 4096); VARIABLE TX_LOC : LINE; BEGIN STD.TEXTIO.write(TX_LOC, string'("Annotate[")); STD.TEXTIO.write(TX_LOC, TX_TIME); STD.TEXTIO.write(TX_LOC, string'(", REQ2, ")); IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, REQ2); STD.TEXTIO.write(TX_LOC, string'("]")); TX_STR(TX_LOC.all'range) := TX_LOC.all; STD.TEXTIO.writeline(RESULTS, TX_LOC); STD.TEXTIO.Deallocate(TX_LOC); END; PROCEDURE ANNOTATE_CTRL( TX_TIME : INTEGER ) IS VARIABLE TX_STR : String(1 to 4096); VARIABLE TX_LOC : LINE; BEGIN STD.TEXTIO.write(TX_LOC, string'("Annotate[")); STD.TEXTIO.write(TX_LOC, TX_TIME); STD.TEXTIO.write(TX_LOC, string'(", CTRL, ")); IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, CTRL); STD.TEXTIO.write(TX_LOC, string'("]")); TX_STR(TX_LOC.all'range) := TX_LOC.all; STD.TEXTIO.writeline(RESULTS, TX_LOC); STD.TEXTIO.Deallocate(TX_LOC); END; PROCEDURE ANNOTATE_FIFO_D( TX_TIME : INTEGER ) IS VARIABLE TX_STR : String(1 to 4096); VARIABLE TX_LOC : LINE; BEGIN STD.TEXTIO.write(TX_LOC, string'("Annotate[")); STD.TEXTIO.write(TX_LOC, TX_TIME); STD.TEXTIO.write(TX_LOC, string'(", FIFO_D, ")); IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, FIFO_D); STD.TEXTIO.write(TX_LOC, string'("]")); TX_STR(TX_LOC.all'range) := TX_LOC.all; STD.TEXTIO.writeline(RESULTS, TX_LOC); STD.TEXTIO.Deallocate(TX_LOC); END; PROCEDURE ANNOTATE_WCLK( TX_TIME : INTEGER ) IS VARIABLE TX_STR : String(1 to 4096); VARIABLE TX_LOC : LINE; BEGIN STD.TEXTIO.write(TX_LOC, string'("Annotate[")); STD.TEXTIO.write(TX_LOC, TX_TIME); STD.TEXTIO.write(TX_LOC, string'(", WCLK, ")); IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, WCLK); STD.TEXTIO.write(TX_LOC, string'("]")); TX_STR(TX_LOC.all'range) := TX_LOC.all; STD.TEXTIO.writeline(RESULTS, TX_LOC); STD.TEXTIO.Deallocate(TX_LOC); END; PROCEDURE ANNOTATE_WENn( TX_TIME : INTEGER ) IS VARIABLE TX_STR : String(1 to 4096); VARIABLE TX_LOC : LINE; BEGIN STD.TEXTIO.write(TX_LOC, string'("Annotate[")); STD.TEXTIO.write(TX_LOC, TX_TIME); STD.TEXTIO.write(TX_LOC, string'(", WENn, ")); IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, WENn); STD.TEXTIO.write(TX_LOC, string'("]")); TX_STR(TX_LOC.all'range) := TX_LOC.all; STD.TEXTIO.writeline(RESULTS, TX_LOC); STD.TEXTIO.Deallocate(TX_LOC); END; PROCEDURE ANNOTATE_RSTn( TX_TIME : INTEGER ) IS VARIABLE TX_STR : String(1 to 4096); VARIABLE TX_LOC : LINE; BEGIN STD.TEXTIO.write(TX_LOC, string'("Annotate[")); STD.TEXTIO.write(TX_LOC, TX_TIME); STD.TEXTIO.write(TX_LOC, string'(", RSTn, ")); IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, RSTn); STD.TEXTIO.write(TX_LOC, string'("]")); TX_STR(TX_LOC.all'range) := TX_LOC.all; STD.TEXTIO.writeline(RESULTS, TX_LOC); STD.TEXTIO.Deallocate(TX_LOC); END; PROCEDURE ANNOTATE_RCLK( TX_TIME : INTEGER ) IS VARIABLE TX_STR : String(1 to 4096); VARIABLE TX_LOC : LINE; BEGIN STD.TEXTIO.write(TX_LOC, string'("Annotate[")); STD.TEXTIO.write(TX_LOC, TX_TIME); STD.TEXTIO.write(TX_LOC, string'(", RCLK, ")); IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, RCLK); STD.TEXTIO.write(TX_LOC, string'("]")); TX_STR(TX_LOC.all'range) := TX_LOC.all; STD.TEXTIO.writeline(RESULTS, TX_LOC); STD.TEXTIO.Deallocate(TX_LOC); END; PROCEDURE ANNOTATE_RENn( TX_TIME : INTEGER ) IS VARIABLE TX_STR : String(1 to 4096); VARIABLE TX_LOC : LINE; BEGIN STD.TEXTIO.write(TX_LOC, string'("Annotate[")); STD.TEXTIO.write(TX_LOC, TX_TIME); STD.TEXTIO.write(TX_LOC, string'(", RENn, ")); IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, RENn); STD.TEXTIO.write(TX_LOC, string'("]")); TX_STR(TX_LOC.all'range) := TX_LOC.all; STD.TEXTIO.writeline(RESULTS, TX_LOC); STD.TEXTIO.Deallocate(TX_LOC); END; PROCEDURE ANNOTATE_OEn( TX_TIME : INTEGER ) IS VARIABLE TX_STR : String(1 to 4096); VARIABLE TX_LOC : LINE; BEGIN STD.TEXTIO.write(TX_LOC, string'("Annotate[")); STD.TEXTIO.write(TX_LOC, TX_TIME); STD.TEXTIO.write(TX_LOC, string'(", OEn, ")); IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, OEn); STD.TEXTIO.write(TX_LOC, string'("]")); TX_STR(TX_LOC.all'range) := TX_LOC.all; STD.TEXTIO.writeline(RESULTS, TX_LOC); STD.TEXTIO.Deallocate(TX_LOC); END; BEGIN WAIT for 1 fs; ANNOTATE_DIOC(0); ANNOTATE_DIOD(0); ANNOTATE_STOPTRIG1(0); ANNOTATE_REQ1(0); ANNOTATE_STOPTRIG2(0); ANNOTATE_REQ2(0); ANNOTATE_CTRL(0); ANNOTATE_FIFO_D(0); ANNOTATE_WCLK(0); ANNOTATE_WENn(0); ANNOTATE_RSTn(0); ANNOTATE_RCLK(0); ANNOTATE_RENn(0); ANNOTATE_OEn(0); WAIT for OFFSET; TX_TIME := TX_TIME + 100; ANNO_LOOP : LOOP --Rising Edge WAIT for 15 ns; TX_TIME := TX_TIME + 15; ANNOTATE_DIOC(TX_TIME); ANNOTATE_DIOD(TX_TIME); ANNOTATE_STOPTRIG1(TX_TIME); ANNOTATE_REQ1(TX_TIME); ANNOTATE_STOPTRIG2(TX_TIME); ANNOTATE_REQ2(TX_TIME); ANNOTATE_CTRL(TX_TIME); ANNOTATE_FIFO_D(TX_TIME); ANNOTATE_WCLK(TX_TIME); ANNOTATE_WENn(TX_TIME); ANNOTATE_RSTn(TX_TIME); ANNOTATE_RCLK(TX_TIME); ANNOTATE_RENn(TX_TIME); ANNOTATE_OEn(TX_TIME); WAIT for 5 ns; TX_TIME := TX_TIME + 5; END LOOP ANNO_LOOP; END PROCESS; PROCESS BEGIN -- ------------- Current Time: 185ns WAIT FOR 185 ns; rst <= '0'; -- ------------------------------------- -- ------------- Current Time: 365ns WAIT FOR 180 ns; DIOA <= "01100101"; DIOB <= "01100101"; -- ------------------------------------- -- ------------- Current Time: 385ns WAIT FOR 20 ns; ACK1 <= '1'; -- ------------------------------------- -- ------------- Current Time: 405ns WAIT FOR 20 ns; ACK1 <= '0'; -- ------------------------------------- WAIT FOR 99615 ns; STD.TEXTIO.write(TX_OUT, string'("Total[]")); STD.TEXTIO.writeline(RESULTS, TX_OUT); ASSERT (FALSE) REPORT "Success! Simulation for annotation completed" SEVERITY FAILURE; END PROCESS; END testbench_arch;