Equations

********** Mapped Logic **********

$OpTx$FX_SC$69 <= (NOT NIDAQLogiccomp/NIDAQSTATE_FFd3 AND
NIDAQLogiccomp/NIDAQSTATE_FFd2);

BUF_NIDAQLogiccomp/wen <= ((NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
      NOT NIDAQLogiccomp/NIDAQSTATE_FFd3)
      OR (NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
      NIDAQLogiccomp/NIDAQSTATE_FFd2));

CTRL <= (OpticalLogiccomp/TransmitCommandcomp/sending AND
OpticalLogiccomp/TransmitCommandcomp/sr(0));

FDCPE_DIOC0: FDCPE port map (DIOC(0),DIOC_D(0),clk,rst,'0');
     DIOC_D(0) <= ((FIFO_Q(0) AND
      NIDAQLogiccomp/N8/NIDAQLogiccomp/N8_D2)
      OR (DIOC(0) AND NOT BUF_NIDAQLogiccomp/wen AND
      NOT $OpTx$FX_SC$69)
      OR (NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
      NIDAQLogiccomp/NIDAQSTATE_FFd2 AND NIDAQLogiccomp/StatusDatasig(0)));

FDCPE_DIOC1: FDCPE port map (DIOC(1),DIOC_D(1),clk,rst,'0');
     DIOC_D(1) <= ((FIFO_Q(1) AND
      NIDAQLogiccomp/N8/NIDAQLogiccomp/N8_D2)
      OR (DIOC(1) AND NOT BUF_NIDAQLogiccomp/wen AND
      NOT $OpTx$FX_SC$69)
      OR (NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
      NIDAQLogiccomp/NIDAQSTATE_FFd2 AND NIDAQLogiccomp/StatusDatasig(1)));

FDCPE_DIOC2: FDCPE port map (DIOC(2),DIOC_D(2),clk,rst,'0');
     DIOC_D(2) <= ((FIFO_Q(2) AND
      NIDAQLogiccomp/N8/NIDAQLogiccomp/N8_D2)
      OR (DIOC(2) AND NOT BUF_NIDAQLogiccomp/wen AND
      NOT $OpTx$FX_SC$69)
      OR (NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
      NIDAQLogiccomp/NIDAQSTATE_FFd2 AND NIDAQLogiccomp/StatusDatasig(2)));

FDCPE_DIOC3: FDCPE port map (DIOC(3),DIOC_D(3),clk,rst,'0');
     DIOC_D(3) <= ((FIFO_Q(3) AND
      NIDAQLogiccomp/N8/NIDAQLogiccomp/N8_D2)
      OR (DIOC(3) AND NOT BUF_NIDAQLogiccomp/wen AND
      NOT $OpTx$FX_SC$69)
      OR (NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
      NIDAQLogiccomp/NIDAQSTATE_FFd2 AND NIDAQLogiccomp/StatusDatasig(3)));

FDCPE_DIOC4: FDCPE port map (DIOC(4),DIOC_D(4),clk,rst,'0');
     DIOC_D(4) <= ((FIFO_Q(4) AND
      NIDAQLogiccomp/N8/NIDAQLogiccomp/N8_D2)
      OR (DIOC(4) AND NOT BUF_NIDAQLogiccomp/wen AND
      NOT $OpTx$FX_SC$69)
      OR (NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
      NIDAQLogiccomp/NIDAQSTATE_FFd2 AND NIDAQLogiccomp/StatusDatasig(4)));

FDCPE_DIOC5: FDCPE port map (DIOC(5),DIOC_D(5),clk,rst,'0');
     DIOC_D(5) <= ((FIFO_Q(5) AND
      NIDAQLogiccomp/N8/NIDAQLogiccomp/N8_D2)
      OR (DIOC(5) AND NOT BUF_NIDAQLogiccomp/wen AND
      NOT $OpTx$FX_SC$69)
      OR (NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
      NIDAQLogiccomp/NIDAQSTATE_FFd2 AND NIDAQLogiccomp/StatusDatasig(5)));

FDCPE_DIOC6: FDCPE port map (DIOC(6),DIOC_D(6),clk,rst,'0');
     DIOC_D(6) <= ((FIFO_Q(6) AND
      NIDAQLogiccomp/N8/NIDAQLogiccomp/N8_D2)
      OR (DIOC(6) AND NOT BUF_NIDAQLogiccomp/wen AND
      NOT $OpTx$FX_SC$69)
      OR (NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
      NIDAQLogiccomp/NIDAQSTATE_FFd2 AND NIDAQLogiccomp/StatusDatasig(6)));

FDCPE_DIOC7: FDCPE port map (DIOC(7),DIOC_D(7),clk,rst,'0');
     DIOC_D(7) <= ((FIFO_Q(7) AND
      NIDAQLogiccomp/N8/NIDAQLogiccomp/N8_D2)
      OR (DIOC(7) AND NOT BUF_NIDAQLogiccomp/wen AND
      NOT $OpTx$FX_SC$69)
      OR (NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
      NIDAQLogiccomp/NIDAQSTATE_FFd2 AND NIDAQLogiccomp/StatusDatasig(7)));

FDCPE_DIOD0: FDCPE port map (DIOD(0),DIOD_D(0),clk,rst,'0');
     DIOD_D(0) <= ((FIFO_Q(8) AND
      NIDAQLogiccomp/N8/NIDAQLogiccomp/N8_D2)
      OR (DIOD(0) AND NOT BUF_NIDAQLogiccomp/wen AND
      NOT $OpTx$FX_SC$69)
      OR (NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
      NIDAQLogiccomp/NIDAQSTATE_FFd2 AND NIDAQLogiccomp/StatusDatasig(8)));

FDCPE_DIOD1: FDCPE port map (DIOD(1),DIOD_D(1),clk,rst,'0');
     DIOD_D(1) <= ((FIFO_Q(9) AND
      NIDAQLogiccomp/N8/NIDAQLogiccomp/N8_D2)
      OR (DIOD(1) AND NOT BUF_NIDAQLogiccomp/wen AND
      NOT $OpTx$FX_SC$69)
      OR (NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
      NIDAQLogiccomp/NIDAQSTATE_FFd2 AND NIDAQLogiccomp/StatusDatasig(9)));

FDCPE_DIOD2: FDCPE port map (DIOD(2),DIOD_D(2),clk,rst,'0');
     DIOD_D(2) <= ((FIFO_Q(10) AND
      NIDAQLogiccomp/N8/NIDAQLogiccomp/N8_D2)
      OR (DIOD(2) AND NOT BUF_NIDAQLogiccomp/wen AND
      NOT $OpTx$FX_SC$69)
      OR (NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
      NIDAQLogiccomp/NIDAQSTATE_FFd2 AND NIDAQLogiccomp/StatusDatasig(10)));

FDCPE_DIOD3: FDCPE port map (DIOD(3),DIOD_D(3),clk,rst,'0');
     DIOD_D(3) <= ((FIFO_Q(11) AND
      NIDAQLogiccomp/N8/NIDAQLogiccomp/N8_D2)
      OR (DIOD(3) AND NOT BUF_NIDAQLogiccomp/wen AND
      NOT $OpTx$FX_SC$69)
      OR (NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
      NIDAQLogiccomp/NIDAQSTATE_FFd2 AND NIDAQLogiccomp/StatusDatasig(11)));

FDCPE_DIOD4: FDCPE port map (DIOD(4),DIOD_D(4),clk,rst,'0');
     DIOD_D(4) <= ((FIFO_Q(12) AND
      NIDAQLogiccomp/N8/NIDAQLogiccomp/N8_D2)
      OR (DIOD(4) AND NOT BUF_NIDAQLogiccomp/wen AND
      NOT $OpTx$FX_SC$69)
      OR (NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
      NIDAQLogiccomp/NIDAQSTATE_FFd2 AND NIDAQLogiccomp/StatusDatasig(12)));

FDCPE_DIOD5: FDCPE port map (DIOD(5),DIOD_D(5),clk,rst,'0');
     DIOD_D(5) <= ((FIFO_Q(13) AND
      NIDAQLogiccomp/N8/NIDAQLogiccomp/N8_D2)
      OR (DIOD(5) AND NOT BUF_NIDAQLogiccomp/wen AND
      NOT $OpTx$FX_SC$69)
      OR (NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
      NIDAQLogiccomp/NIDAQSTATE_FFd2 AND NIDAQLogiccomp/StatusDatasig(13)));

FDCPE_DIOD6: FDCPE port map (DIOD(6),DIOD_D(6),clk,rst,'0');
     DIOD_D(6) <= ((FIFO_Q(14) AND
      NIDAQLogiccomp/N8/NIDAQLogiccomp/N8_D2)
      OR (DIOD(6) AND NOT BUF_NIDAQLogiccomp/wen AND
      NOT $OpTx$FX_SC$69)
      OR (NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
      NIDAQLogiccomp/NIDAQSTATE_FFd2 AND NIDAQLogiccomp/StatusDatasig(14)));

FDCPE_DIOD7: FDCPE port map (DIOD(7),DIOD_D(7),clk,rst,'0');
     DIOD_D(7) <= ((FIFO_Q(15) AND
      NIDAQLogiccomp/N8/NIDAQLogiccomp/N8_D2)
      OR (DIOD(7) AND NOT BUF_NIDAQLogiccomp/wen AND
      NOT $OpTx$FX_SC$69)
      OR (NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
      NIDAQLogiccomp/NIDAQSTATE_FFd2 AND NIDAQLogiccomp/StatusDatasig(15)));

FDCPE_EventReadoutsig: FDCPE port map (EventReadoutsig,EventReadoutsig_D,clk,rst,'0');
EventReadoutsig_D <= (NOT MainLogiccomp/MAINSTATE_FFd1 AND
NOT MainLogiccomp/MAINSTATE_FFd2 AND MainLogiccomp/MAINSTATE_FFd3);

FDCPE_EventReadysig: FDCPE port map (EventReadysig,'1',clk,NOT EventReadysig/EventReadysig_RSTF,'0',OpticalLogiccomp/RxDataLogiccomp/EventReadyCmd);

EventReadysig/EventReadysig_RSTF <= (NOT rst AND NOT EventReadoutsig);

FIFO_D(0) <= (
NOT OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd1 AND OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(0));

FIFO_D(1) <= (
NOT OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd1 AND OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(1));

FIFO_D(2) <= (
NOT OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd1 AND OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(2));

FIFO_D(3) <= (
NOT OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd1 AND OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(3));

FIFO_D(4) <= (
NOT OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd1 AND OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(4));

FIFO_D(5) <= (
NOT OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd1 AND OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(5));

FIFO_D(6) <= (
NOT OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd1 AND OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(6));

FIFO_D(7) <= (
NOT OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd1 AND OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(7));

FIFO_D(8) <= (
NOT OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd1 AND OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(8));

FIFO_D(9) <= (
NOT OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd1 AND OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(9));

FIFO_D(10) <= (
NOT OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd1 AND OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(10));

FIFO_D(11) <= (
NOT OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd1 AND OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(11));

FIFO_D(12) <= (
NOT OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd1 AND OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(12));

FIFO_D(13) <= (
NOT OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd1 AND OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(13));

FIFO_D(14) <= (
NOT OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd1 AND OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(14));

FIFO_D(15) <= (
NOT OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd1 AND OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(15));

FDCPE_MainLogiccomp/MAINSTATE_FFd1: FDCPE port map (MainLogiccomp/MAINSTATE_FFd1,MainLogiccomp/MAINSTATE_FFd1_D,clk,rst,'0');
     MainLogiccomp/MAINSTATE_FFd1_D <= ((SPARE(10) AND SPARE(11) AND NOT SPARE(9) AND NOT SPARE(12) AND
      NICMDsig(0) AND NOT NICMDsig(1) AND NICMDsig(2) AND NOT NICMDsig(3) AND
      NOT MainLogiccomp/MAINSTATE_FFd1 AND NOT MainLogiccomp/MAINSTATE_FFd2 AND
      NOT MainLogiccomp/MAINSTATE_FFd3 AND NICMD_Readysig)
      OR (SPARE(10) AND SPARE(11) AND NOT SPARE(9) AND NOT SPARE(12) AND
      NOT NICMDsig(0) AND NOT NICMDsig(1) AND NOT NICMDsig(2) AND NICMDsig(3) AND
      NOT MainLogiccomp/MAINSTATE_FFd1 AND NOT MainLogiccomp/MAINSTATE_FFd2 AND
      NOT MainLogiccomp/MAINSTATE_FFd3 AND NICMD_Readysig));

FDCPE_MainLogiccomp/MAINSTATE_FFd2: FDCPE port map (MainLogiccomp/MAINSTATE_FFd2,MainLogiccomp/MAINSTATE_FFd2_D,clk,rst,'0');
     MainLogiccomp/MAINSTATE_FFd2_D <= ((NOT SPARE(10) AND NOT SPARE(11) AND NOT SPARE(12) AND
      NOT MainLogiccomp/MAINSTATE_FFd1 AND NOT MainLogiccomp/MAINSTATE_FFd2 AND
      NOT MainLogiccomp/MAINSTATE_FFd3 AND NICMD_Readysig)
      OR (SPARE(10) AND SPARE(11) AND NOT SPARE(9) AND NOT SPARE(12) AND
      NICMDsig(1) AND NICMDsig(2) AND NOT NICMDsig(3) AND
      NOT MainLogiccomp/MAINSTATE_FFd1 AND NOT MainLogiccomp/MAINSTATE_FFd2 AND
      NOT MainLogiccomp/MAINSTATE_FFd3 AND NICMD_Readysig));

FDCPE_MainLogiccomp/MAINSTATE_FFd3: FDCPE port map (MainLogiccomp/MAINSTATE_FFd3,MainLogiccomp/MAINSTATE_FFd3_D,clk,rst,'0');
     MainLogiccomp/MAINSTATE_FFd3_D <= ((NOT SPARE(10) AND NOT SPARE(11) AND NOT SPARE(12) AND
      NOT MainLogiccomp/MAINSTATE_FFd1 AND NOT MainLogiccomp/MAINSTATE_FFd2 AND
      NOT MainLogiccomp/MAINSTATE_FFd3 AND NICMD_Readysig)
      OR (SPARE(10) AND SPARE(11) AND NOT SPARE(9) AND NOT SPARE(12) AND
      NICMDsig(0) AND NICMDsig(1) AND NICMDsig(2) AND NOT NICMDsig(3) AND
      NOT MainLogiccomp/MAINSTATE_FFd1 AND NOT MainLogiccomp/MAINSTATE_FFd2 AND
      NOT MainLogiccomp/MAINSTATE_FFd3 AND NICMD_Readysig)
      OR (SPARE(10) AND SPARE(11) AND NOT SPARE(9) AND NOT SPARE(12) AND
      NOT NICMDsig(0) AND NOT NICMDsig(1) AND NICMDsig(2) AND NOT NICMDsig(3) AND
      NOT MainLogiccomp/MAINSTATE_FFd1 AND NOT MainLogiccomp/MAINSTATE_FFd2 AND
      NOT MainLogiccomp/MAINSTATE_FFd3 AND NICMD_Readysig)
      OR (SPARE(10) AND SPARE(11) AND NOT SPARE(9) AND NOT SPARE(12) AND
      NOT NICMDsig(0) AND NOT NICMDsig(1) AND NOT NICMDsig(2) AND NICMDsig(3) AND
      NOT MainLogiccomp/MAINSTATE_FFd1 AND NOT MainLogiccomp/MAINSTATE_FFd2 AND
      NOT MainLogiccomp/MAINSTATE_FFd3 AND NICMD_Readysig));

FDCPE_NICMD_Argsig0: FDCPE port map (NICMD_Argsig(0),NIDAQLogiccomp/command_out(0),clk,rst,'0',NICMD_Argsig_CE(0));
NICMD_Argsig_CE(0) <= (NOT NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NIDAQLogiccomp/NIDAQSTATE_FFd3 AND NOT NIDAQLogiccomp/NIDAQSTATE_FFd2);

FDCPE_NICMD_Argsig1: FDCPE port map (NICMD_Argsig(1),NIDAQLogiccomp/command_out(1),clk,rst,'0',NICMD_Argsig_CE(1));
NICMD_Argsig_CE(1) <= (NOT NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NIDAQLogiccomp/NIDAQSTATE_FFd3 AND NOT NIDAQLogiccomp/NIDAQSTATE_FFd2);

FDCPE_NICMD_Argsig2: FDCPE port map (NICMD_Argsig(2),NIDAQLogiccomp/command_out(2),clk,rst,'0',NICMD_Argsig_CE(2));
NICMD_Argsig_CE(2) <= (NOT NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NIDAQLogiccomp/NIDAQSTATE_FFd3 AND NOT NIDAQLogiccomp/NIDAQSTATE_FFd2);

FDCPE_NICMD_Argsig3: FDCPE port map (NICMD_Argsig(3),NIDAQLogiccomp/command_out(3),clk,rst,'0',NICMD_Argsig_CE(3));
NICMD_Argsig_CE(3) <= (NOT NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NIDAQLogiccomp/NIDAQSTATE_FFd3 AND NOT NIDAQLogiccomp/NIDAQSTATE_FFd2);

FDCPE_NICMD_Argsig4: FDCPE port map (NICMD_Argsig(4),NIDAQLogiccomp/command_out(4),clk,rst,'0',NICMD_Argsig_CE(4));
NICMD_Argsig_CE(4) <= (NOT NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NIDAQLogiccomp/NIDAQSTATE_FFd3 AND NOT NIDAQLogiccomp/NIDAQSTATE_FFd2);

FDCPE_NICMD_Argsig5: FDCPE port map (NICMD_Argsig(5),NIDAQLogiccomp/command_out(5),clk,rst,'0',NICMD_Argsig_CE(5));
NICMD_Argsig_CE(5) <= (NOT NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NIDAQLogiccomp/NIDAQSTATE_FFd3 AND NOT NIDAQLogiccomp/NIDAQSTATE_FFd2);

FDCPE_NICMD_Argsig6: FDCPE port map (NICMD_Argsig(6),NIDAQLogiccomp/command_out(6),clk,rst,'0',NICMD_Argsig_CE(6));
NICMD_Argsig_CE(6) <= (NOT NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NIDAQLogiccomp/NIDAQSTATE_FFd3 AND NOT NIDAQLogiccomp/NIDAQSTATE_FFd2);

FDCPE_NICMD_Argsig7: FDCPE port map (NICMD_Argsig(7),NIDAQLogiccomp/command_out(7),clk,rst,'0',NICMD_Argsig_CE(7));
NICMD_Argsig_CE(7) <= (NOT NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NIDAQLogiccomp/NIDAQSTATE_FFd3 AND NOT NIDAQLogiccomp/NIDAQSTATE_FFd2);

FDCPE_NICMD_Readysig: FDCPE port map (NICMD_Readysig,NICMD_Readysig_D,clk,rst,'0');
NICMD_Readysig_D <= (NOT NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NIDAQLogiccomp/NIDAQSTATE_FFd3 AND NOT NIDAQLogiccomp/NIDAQSTATE_FFd2);

FDCPE_NICMDsig0: FDCPE port map (NICMDsig(0),NIDAQLogiccomp/command_out(8),clk,rst,'0',NICMDsig_CE(0));
NICMDsig_CE(0) <= (NOT NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NIDAQLogiccomp/NIDAQSTATE_FFd3 AND NOT NIDAQLogiccomp/NIDAQSTATE_FFd2);

FDCPE_NICMDsig1: FDCPE port map (NICMDsig(1),NIDAQLogiccomp/command_out(9),clk,rst,'0',NICMDsig_CE(1));
NICMDsig_CE(1) <= (NOT NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NIDAQLogiccomp/NIDAQSTATE_FFd3 AND NOT NIDAQLogiccomp/NIDAQSTATE_FFd2);

FDCPE_NICMDsig2: FDCPE port map (NICMDsig(2),NIDAQLogiccomp/command_out(10),clk,rst,'0',NICMDsig_CE(2));
NICMDsig_CE(2) <= (NOT NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NIDAQLogiccomp/NIDAQSTATE_FFd3 AND NOT NIDAQLogiccomp/NIDAQSTATE_FFd2);

FDCPE_NICMDsig3: FDCPE port map (NICMDsig(3),NIDAQLogiccomp/command_out(11),clk,rst,'0',NICMDsig_CE(3));
NICMDsig_CE(3) <= (NOT NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NIDAQLogiccomp/NIDAQSTATE_FFd3 AND NOT NIDAQLogiccomp/NIDAQSTATE_FFd2);

NIDAQLogiccomp/Msub__addsub0000__or0001/NIDAQLogiccomp/Msub__addsub0000__or0001_D2 <= (NOT NIDAQLogiccomp/NumOfWordsSentCounter(0) AND
NOT NIDAQLogiccomp/NumOfWordsSentCounter(1) AND NOT NIDAQLogiccomp/NumOfWordsSentCounter(2));

NIDAQLogiccomp/Msub__addsub0000__or0003/NIDAQLogiccomp/Msub__addsub0000__or0003_D2 <= (NOT NIDAQLogiccomp/NumOfWordsSentCounter(3) AND
NOT NIDAQLogiccomp/NumOfWordsSentCounter(4) AND
NIDAQLogiccomp/Msub__addsub0000__or0001/NIDAQLogiccomp/Msub__addsub0000__or0001_D2);

NIDAQLogiccomp/N8/NIDAQLogiccomp/N8_D2 <= ((NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
      NOT NIDAQLogiccomp/NIDAQSTATE_FFd3 AND NOT NIDAQLogiccomp/NIDAQSTATE_FFd2)
      OR (NOT NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
      NOT NIDAQLogiccomp/NIDAQSTATE_FFd3 AND NIDAQLogiccomp/NIDAQSTATE_FFd2));

FDCPE_NIDAQLogiccomp/NIDAQSTATE_FFd1: FDCPE port map (NIDAQLogiccomp/NIDAQSTATE_FFd1,NIDAQLogiccomp/NIDAQSTATE_FFd1_D,clk,rst,'0');
     NIDAQLogiccomp/NIDAQSTATE_FFd1_D <= ((BUF_NIDAQLogiccomp/wen)
      OR ($OpTx$FX_SC$69)
      OR (NOT NIDAQLogiccomp/SendingPackageFlag AND
      NOT NIDAQLogiccomp/NIDAQSTATE_FFd3 AND NOT NIDAQLogiccomp/cav AND SendDataCmdsig)
      OR (NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
      NIDAQLogiccomp/NIDAQSTATE_FFd3 AND NOT NIDAQLogiccomp/Readtimeout AND NOT NIDAQLogiccomp/wdone));

FDCPE_NIDAQLogiccomp/NIDAQSTATE_FFd2: FDCPE port map (NIDAQLogiccomp/NIDAQSTATE_FFd2,NIDAQLogiccomp/NIDAQSTATE_FFd2_D,clk,rst,'0');
     NIDAQLogiccomp/NIDAQSTATE_FFd2_D <= ((NIDAQLogiccomp/NIDAQSTATE_FFd3 AND
      NIDAQLogiccomp/NIDAQSTATE_FFd2)
      OR (NIDAQLogiccomp/SendingPackageFlag AND
      NOT NIDAQLogiccomp/NIDAQSTATE_FFd1 AND NOT NIDAQLogiccomp/NIDAQSTATE_FFd3 AND
      NOT NIDAQLogiccomp/NIDAQSTATE_FFd2 AND NOT NIDAQLogiccomp/cav)
      OR (NOT NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
      NOT NIDAQLogiccomp/NIDAQSTATE_FFd3 AND NOT NIDAQLogiccomp/NIDAQSTATE_FFd2 AND
      NOT NIDAQLogiccomp/cav AND SendDataCmdsig));

FTCPE_NIDAQLogiccomp/NIDAQSTATE_FFd3: FTCPE port map (NIDAQLogiccomp/NIDAQSTATE_FFd3,NIDAQLogiccomp/NIDAQSTATE_FFd3_T,clk,rst,'0');
     NIDAQLogiccomp/NIDAQSTATE_FFd3_T <= ((NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
      NIDAQLogiccomp/NIDAQSTATE_FFd3 AND NIDAQLogiccomp/NIDAQSTATE_FFd2)
      OR (NOT NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
      NOT NIDAQLogiccomp/NIDAQSTATE_FFd3 AND NIDAQLogiccomp/NIDAQSTATE_FFd2)
      OR (NOT NIDAQLogiccomp/SendingPackageFlag AND
      NOT NIDAQLogiccomp/NIDAQSTATE_FFd1 AND NOT NIDAQLogiccomp/NIDAQSTATE_FFd3 AND
      NOT NIDAQLogiccomp/cav)
      OR (NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
      NIDAQLogiccomp/NIDAQSTATE_FFd3 AND NOT NIDAQLogiccomp/Readtimeout AND NOT NIDAQLogiccomp/wdone));

FDCPE_NIDAQLogiccomp/NI_Interfacecomp/ack1_sync0: FDCPE port map (NIDAQLogiccomp/NI_Interfacecomp/ack1_sync(0),ACK1,NOT clk,rst,'0');

FDCPE_NIDAQLogiccomp/NI_Interfacecomp/ack1_sync1: FDCPE port map (NIDAQLogiccomp/NI_Interfacecomp/ack1_sync(1),NIDAQLogiccomp/NI_Interfacecomp/ack1_sync(0),NOT clk,rst,'0');

FDCPE_NIDAQLogiccomp/NI_Interfacecomp/ack1_sync2: FDCPE port map (NIDAQLogiccomp/NI_Interfacecomp/ack1_sync(2),NIDAQLogiccomp/NI_Interfacecomp/ack1_sync(1),NOT clk,rst,'0');

FDCPE_NIDAQLogiccomp/NI_Interfacecomp/ack2_sync: FDCPE port map (NIDAQLogiccomp/NI_Interfacecomp/ack2_sync,ACK2,NOT clk,rst,'0');

FDCPE_NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd1: FDCPE port map (NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd1,NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd1_D,clk,rst,'0');
NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd1_D <= (NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd3 AND
NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd2 AND NOT NIDAQLogiccomp/NI_Interfacecomp/ack2_sync);

FDCPE_NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd2: FDCPE port map (NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd2,NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd2_D,clk,rst,'0');
     NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd2_D <= ((NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd3 AND
      NIDAQLogiccomp/NI_Interfacecomp/ack2_sync)
      OR (NOT NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd3 AND
      NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd2));

FDCPE_NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd3: FDCPE port map (NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd3,NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd3_D,clk,rst,'0');
     NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd3_D <= ((NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd3 AND
      NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd2 AND NIDAQLogiccomp/NI_Interfacecomp/ack2_sync)
      OR (NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd3 AND
      NOT NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd2 AND NOT NIDAQLogiccomp/NI_Interfacecomp/ack2_sync)
      OR (NOT NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd3 AND
      NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd2 AND NOT NIDAQLogiccomp/NI_Interfacecomp/req2_cnt(0) AND
      NOT NIDAQLogiccomp/NI_Interfacecomp/req2_cnt(1))
      OR (NOT NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd3 AND
      NOT NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd2 AND NOT NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd1 AND
      NIDAQLogiccomp/wen));

FDCPE_NIDAQLogiccomp/NI_Interfacecomp/req2_cnt0: FDCPE port map (NIDAQLogiccomp/NI_Interfacecomp/req2_cnt(0),NIDAQLogiccomp/NI_Interfacecomp/req2_cnt_D(0),clk,rst,'0');
NIDAQLogiccomp/NI_Interfacecomp/req2_cnt_D(0) <= (NOT NIDAQLogiccomp/NI_Interfacecomp/req2_cnt(0) AND
NOT NIDAQLogiccomp/NI_Interfacecomp/req2_cnt_ld);

FDCPE_NIDAQLogiccomp/NI_Interfacecomp/req2_cnt1: FDCPE port map (NIDAQLogiccomp/NI_Interfacecomp/req2_cnt(1),NIDAQLogiccomp/NI_Interfacecomp/req2_cnt_D(1),clk,rst,'0');
     NIDAQLogiccomp/NI_Interfacecomp/req2_cnt_D(1) <= ((NIDAQLogiccomp/NI_Interfacecomp/req2_cnt(0) AND
      NOT NIDAQLogiccomp/NI_Interfacecomp/req2_cnt(1) AND NOT NIDAQLogiccomp/NI_Interfacecomp/req2_cnt_ld)
      OR (NOT NIDAQLogiccomp/NI_Interfacecomp/req2_cnt(0) AND
      NIDAQLogiccomp/NI_Interfacecomp/req2_cnt(1) AND NOT NIDAQLogiccomp/NI_Interfacecomp/req2_cnt_ld));

FDCPE_NIDAQLogiccomp/NI_Interfacecomp/req2_cnt_ld: FDCPE port map (NIDAQLogiccomp/NI_Interfacecomp/req2_cnt_ld,NOT NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd2,clk,'0',rst);

FDCPE_NIDAQLogiccomp/NumOfWordsSentCounter0: FDCPE port map (NIDAQLogiccomp/NumOfWordsSentCounter(0),NIDAQLogiccomp/NumOfWordsSentCounter_D(0),clk,rst,'0');
     NIDAQLogiccomp/NumOfWordsSentCounter_D(0) <= ((NIDAQLogiccomp/SendingPackageFlag AND
      NIDAQLogiccomp/NumOfWordsSentCounter(0) AND NOT NIDAQLogiccomp/wen)
      OR (NIDAQLogiccomp/SendingPackageFlag AND
      NOT NIDAQLogiccomp/NumOfWordsSentCounter(0) AND NIDAQLogiccomp/wen));

FTCPE_NIDAQLogiccomp/NumOfWordsSentCounter1: FTCPE port map (NIDAQLogiccomp/NumOfWordsSentCounter(1),NIDAQLogiccomp/NumOfWordsSentCounter_T(1),clk,rst,'0');
     NIDAQLogiccomp/NumOfWordsSentCounter_T(1) <= ((NOT NIDAQLogiccomp/SendingPackageFlag AND
      NIDAQLogiccomp/NumOfWordsSentCounter(1))
      OR (NIDAQLogiccomp/SendingPackageFlag AND
      NOT NIDAQLogiccomp/NumOfWordsSentCounter(0) AND NIDAQLogiccomp/wen));

FTCPE_NIDAQLogiccomp/NumOfWordsSentCounter2: FTCPE port map (NIDAQLogiccomp/NumOfWordsSentCounter(2),NIDAQLogiccomp/NumOfWordsSentCounter_T(2),clk,rst,'0');
     NIDAQLogiccomp/NumOfWordsSentCounter_T(2) <= ((NOT NIDAQLogiccomp/SendingPackageFlag AND
      NIDAQLogiccomp/NumOfWordsSentCounter(2))
      OR (NIDAQLogiccomp/SendingPackageFlag AND
      NOT NIDAQLogiccomp/NumOfWordsSentCounter(0) AND NOT NIDAQLogiccomp/NumOfWordsSentCounter(1) AND
      NIDAQLogiccomp/wen));

FTCPE_NIDAQLogiccomp/NumOfWordsSentCounter3: FTCPE port map (NIDAQLogiccomp/NumOfWordsSentCounter(3),NIDAQLogiccomp/NumOfWordsSentCounter_T(3),clk,rst,'0');
     NIDAQLogiccomp/NumOfWordsSentCounter_T(3) <= ((NOT NIDAQLogiccomp/SendingPackageFlag AND
      NIDAQLogiccomp/NumOfWordsSentCounter(3))
      OR (NIDAQLogiccomp/SendingPackageFlag AND
      NIDAQLogiccomp/wen AND
      NIDAQLogiccomp/Msub__addsub0000__or0001/NIDAQLogiccomp/Msub__addsub0000__or0001_D2));

FTCPE_NIDAQLogiccomp/NumOfWordsSentCounter4: FTCPE port map (NIDAQLogiccomp/NumOfWordsSentCounter(4),NIDAQLogiccomp/NumOfWordsSentCounter_T(4),clk,'0',rst);
     NIDAQLogiccomp/NumOfWordsSentCounter_T(4) <= ((NOT NIDAQLogiccomp/SendingPackageFlag AND
      NOT NIDAQLogiccomp/NumOfWordsSentCounter(4))
      OR (NIDAQLogiccomp/SendingPackageFlag AND
      NOT NIDAQLogiccomp/NumOfWordsSentCounter(3) AND NIDAQLogiccomp/wen AND
      NIDAQLogiccomp/Msub__addsub0000__or0001/NIDAQLogiccomp/Msub__addsub0000__or0001_D2));

FTCPE_NIDAQLogiccomp/NumOfWordsSentCounter5: FTCPE port map (NIDAQLogiccomp/NumOfWordsSentCounter(5),NIDAQLogiccomp/NumOfWordsSentCounter_T(5),clk,rst,'0');
     NIDAQLogiccomp/NumOfWordsSentCounter_T(5) <= ((NOT NIDAQLogiccomp/SendingPackageFlag AND
      NIDAQLogiccomp/NumOfWordsSentCounter(5))
      OR (NIDAQLogiccomp/SendingPackageFlag AND
      NIDAQLogiccomp/wen AND
      NIDAQLogiccomp/Msub__addsub0000__or0003/NIDAQLogiccomp/Msub__addsub0000__or0003_D2));

FTCPE_NIDAQLogiccomp/NumOfWordsSentCounter6: FTCPE port map (NIDAQLogiccomp/NumOfWordsSentCounter(6),NIDAQLogiccomp/NumOfWordsSentCounter_T(6),clk,rst,'0');
     NIDAQLogiccomp/NumOfWordsSentCounter_T(6) <= ((NOT NIDAQLogiccomp/SendingPackageFlag AND
      NIDAQLogiccomp/NumOfWordsSentCounter(6))
      OR (NIDAQLogiccomp/SendingPackageFlag AND
      NOT NIDAQLogiccomp/NumOfWordsSentCounter(5) AND NIDAQLogiccomp/wen AND
      NIDAQLogiccomp/Msub__addsub0000__or0003/NIDAQLogiccomp/Msub__addsub0000__or0003_D2));

FTCPE_NIDAQLogiccomp/NumOfWordsSentCounter7: FTCPE port map (NIDAQLogiccomp/NumOfWordsSentCounter(7),NIDAQLogiccomp/NumOfWordsSentCounter_T(7),clk,rst,'0');
     NIDAQLogiccomp/NumOfWordsSentCounter_T(7) <= ((NOT NIDAQLogiccomp/SendingPackageFlag AND
      NIDAQLogiccomp/NumOfWordsSentCounter(7))
      OR (NIDAQLogiccomp/SendingPackageFlag AND
      NOT NIDAQLogiccomp/NumOfWordsSentCounter(5) AND NOT NIDAQLogiccomp/NumOfWordsSentCounter(6) AND
      NIDAQLogiccomp/wen AND
      NIDAQLogiccomp/Msub__addsub0000__or0003/NIDAQLogiccomp/Msub__addsub0000__or0003_D2));

FDCPE_NIDAQLogiccomp/Readtimeout: FDCPE port map (NIDAQLogiccomp/Readtimeout,NIDAQLogiccomp/Readtimeout_D,clk,rst,'0');
     NIDAQLogiccomp/Readtimeout_D <= (NIDAQLogiccomp/Readtimeouten AND
      NOT NIDAQLogiccomp/Readtimeoutcounter_0_0 AND NOT NIDAQLogiccomp/Readtimeoutcounter_0_1 AND
      NOT NIDAQLogiccomp/Readtimeoutcounter_0_10 AND NOT NIDAQLogiccomp/Readtimeoutcounter_0_11 AND
      NIDAQLogiccomp/Readtimeoutcounter_0_12 AND NIDAQLogiccomp/Readtimeoutcounter_0_13 AND
      NIDAQLogiccomp/Readtimeoutcounter_0_14 AND NOT NIDAQLogiccomp/Readtimeoutcounter_0_2 AND
      NOT NIDAQLogiccomp/Readtimeoutcounter_0_3 AND NOT NIDAQLogiccomp/Readtimeoutcounter_0_4 AND
      NOT NIDAQLogiccomp/Readtimeoutcounter_0_5 AND NOT NIDAQLogiccomp/Readtimeoutcounter_0_6 AND
      NIDAQLogiccomp/Readtimeoutcounter_0_7 AND NOT NIDAQLogiccomp/Readtimeoutcounter_0_8 AND
      NOT NIDAQLogiccomp/Readtimeoutcounter_0_9 AND NIDAQLogiccomp/Readtimeoutcounter_0_15);

FDCPE_NIDAQLogiccomp/Readtimeoutcounter_0_0: FDCPE port map (NIDAQLogiccomp/Readtimeoutcounter_0_0,NIDAQLogiccomp/Readtimeoutcounter_0_0_D,clk,rst,'0');
NIDAQLogiccomp/Readtimeoutcounter_0_0_D <= (NIDAQLogiccomp/Readtimeouten AND
NOT NIDAQLogiccomp/Readtimeoutcounter_0_0);

FDCPE_NIDAQLogiccomp/Readtimeoutcounter_0_1: FDCPE port map (NIDAQLogiccomp/Readtimeoutcounter_0_1,NIDAQLogiccomp/Readtimeoutcounter_0_1_D,clk,rst,'0');
     NIDAQLogiccomp/Readtimeoutcounter_0_1_D <= ((NIDAQLogiccomp/Readtimeouten AND
      NIDAQLogiccomp/Readtimeoutcounter_0_0 AND NOT NIDAQLogiccomp/Readtimeoutcounter_0_1)
      OR (NIDAQLogiccomp/Readtimeouten AND
      NOT NIDAQLogiccomp/Readtimeoutcounter_0_0 AND NIDAQLogiccomp/Readtimeoutcounter_0_1));

FDCPE_NIDAQLogiccomp/Readtimeoutcounter_0_10: FDCPE port map (NIDAQLogiccomp/Readtimeoutcounter_0_10,NIDAQLogiccomp/Readtimeoutcounter_0_10_D,clk,rst,'0');
     NIDAQLogiccomp/Readtimeoutcounter_0_10_D <= ((NIDAQLogiccomp/Readtimeouten AND
      NIDAQLogiccomp/Readtimeoutcounter_0_10 AND
      NOT NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0008/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0008_D2)
      OR (NIDAQLogiccomp/Readtimeouten AND
      NOT NIDAQLogiccomp/Readtimeoutcounter_0_10 AND
      NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0008/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0008_D2));

FDCPE_NIDAQLogiccomp/Readtimeoutcounter_0_11: FDCPE port map (NIDAQLogiccomp/Readtimeoutcounter_0_11,NIDAQLogiccomp/Readtimeoutcounter_0_11_D,clk,rst,'0');
     NIDAQLogiccomp/Readtimeoutcounter_0_11_D <= ((NIDAQLogiccomp/Readtimeouten AND
      NIDAQLogiccomp/Readtimeoutcounter_0_11 AND
      NOT NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0010/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0010_D2)
      OR (NIDAQLogiccomp/Readtimeouten AND
      NIDAQLogiccomp/Readtimeoutcounter_0_10 AND
      NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0008/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0008_D2 AND
      NOT NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0010/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0010_D2));

FDCPE_NIDAQLogiccomp/Readtimeoutcounter_0_12: FDCPE port map (NIDAQLogiccomp/Readtimeoutcounter_0_12,NIDAQLogiccomp/Readtimeoutcounter_0_12_D,clk,rst,'0');
     NIDAQLogiccomp/Readtimeoutcounter_0_12_D <= ((NIDAQLogiccomp/Readtimeouten AND
      NIDAQLogiccomp/Readtimeoutcounter_0_12 AND
      NOT NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0010/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0010_D2)
      OR (NIDAQLogiccomp/Readtimeouten AND
      NOT NIDAQLogiccomp/Readtimeoutcounter_0_12 AND
      NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0010/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0010_D2));

FTCPE_NIDAQLogiccomp/Readtimeoutcounter_0_13: FTCPE port map (NIDAQLogiccomp/Readtimeoutcounter_0_13,NIDAQLogiccomp/Readtimeoutcounter_0_13_T,clk,rst,'0');
     NIDAQLogiccomp/Readtimeoutcounter_0_13_T <= ((NOT NIDAQLogiccomp/Readtimeouten AND
      NIDAQLogiccomp/Readtimeoutcounter_0_13)
      OR (NIDAQLogiccomp/Readtimeouten AND
      NIDAQLogiccomp/Readtimeoutcounter_0_12 AND
      NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0010/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0010_D2));

FDCPE_NIDAQLogiccomp/Readtimeoutcounter_0_14: FDCPE port map (NIDAQLogiccomp/Readtimeoutcounter_0_14,NIDAQLogiccomp/Readtimeoutcounter_0_14_D,clk,rst,'0');
     NIDAQLogiccomp/Readtimeoutcounter_0_14_D <= ((NIDAQLogiccomp/Readtimeouten AND
      NIDAQLogiccomp/Readtimeoutcounter_0_14 AND
      NOT NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0013/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0013_D2)
      OR (NIDAQLogiccomp/Readtimeouten AND
      NIDAQLogiccomp/Readtimeoutcounter_0_12 AND NIDAQLogiccomp/Readtimeoutcounter_0_13 AND
      NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0010/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0010_D2 AND
      NOT NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0013/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0013_D2));

FDCPE_NIDAQLogiccomp/Readtimeoutcounter_0_15: FDCPE port map (NIDAQLogiccomp/Readtimeoutcounter_0_15,NIDAQLogiccomp/Readtimeoutcounter_0_15_D,clk,rst,'0');
     NIDAQLogiccomp/Readtimeoutcounter_0_15_D <= ((NIDAQLogiccomp/Readtimeouten AND
      NIDAQLogiccomp/Readtimeoutcounter_0_15 AND
      NOT NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0013/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0013_D2)
      OR (NIDAQLogiccomp/Readtimeouten AND
      NOT NIDAQLogiccomp/Readtimeoutcounter_0_15 AND
      NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0013/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0013_D2));

FTCPE_NIDAQLogiccomp/Readtimeoutcounter_0_2: FTCPE port map (NIDAQLogiccomp/Readtimeoutcounter_0_2,NIDAQLogiccomp/Readtimeoutcounter_0_2_T,clk,rst,'0');
     NIDAQLogiccomp/Readtimeoutcounter_0_2_T <= ((NOT NIDAQLogiccomp/Readtimeouten AND
      NIDAQLogiccomp/Readtimeoutcounter_0_2)
      OR (NIDAQLogiccomp/Readtimeouten AND
      NIDAQLogiccomp/Readtimeoutcounter_0_0 AND NIDAQLogiccomp/Readtimeoutcounter_0_1));

FTCPE_NIDAQLogiccomp/Readtimeoutcounter_0_3: FTCPE port map (NIDAQLogiccomp/Readtimeoutcounter_0_3,NIDAQLogiccomp/Readtimeoutcounter_0_3_T,clk,rst,'0');
     NIDAQLogiccomp/Readtimeoutcounter_0_3_T <= ((NOT NIDAQLogiccomp/Readtimeouten AND
      NIDAQLogiccomp/Readtimeoutcounter_0_3)
      OR (NIDAQLogiccomp/Readtimeouten AND
      NIDAQLogiccomp/Readtimeoutcounter_0_0 AND NIDAQLogiccomp/Readtimeoutcounter_0_1 AND
      NIDAQLogiccomp/Readtimeoutcounter_0_2));

FDCPE_NIDAQLogiccomp/Readtimeoutcounter_0_4: FDCPE port map (NIDAQLogiccomp/Readtimeoutcounter_0_4,NIDAQLogiccomp/Readtimeoutcounter_0_4_D,clk,rst,'0');
     NIDAQLogiccomp/Readtimeoutcounter_0_4_D <= ((NIDAQLogiccomp/Readtimeouten AND
      NIDAQLogiccomp/Readtimeoutcounter_0_4 AND
      NOT NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0003/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0003_D2)
      OR (NIDAQLogiccomp/Readtimeouten AND
      NIDAQLogiccomp/Readtimeoutcounter_0_0 AND NIDAQLogiccomp/Readtimeoutcounter_0_1 AND
      NIDAQLogiccomp/Readtimeoutcounter_0_2 AND NIDAQLogiccomp/Readtimeoutcounter_0_3 AND
      NOT NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0003/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0003_D2));

FDCPE_NIDAQLogiccomp/Readtimeoutcounter_0_5: FDCPE port map (NIDAQLogiccomp/Readtimeoutcounter_0_5,NIDAQLogiccomp/Readtimeoutcounter_0_5_D,clk,rst,'0');
     NIDAQLogiccomp/Readtimeoutcounter_0_5_D <= ((NIDAQLogiccomp/Readtimeouten AND
      NIDAQLogiccomp/Readtimeoutcounter_0_5 AND
      NOT NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0003/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0003_D2)
      OR (NIDAQLogiccomp/Readtimeouten AND
      NOT NIDAQLogiccomp/Readtimeoutcounter_0_5 AND
      NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0003/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0003_D2));

FDCPE_NIDAQLogiccomp/Readtimeoutcounter_0_6: FDCPE port map (NIDAQLogiccomp/Readtimeoutcounter_0_6,NIDAQLogiccomp/Readtimeoutcounter_0_6_D,clk,rst,'0');
     NIDAQLogiccomp/Readtimeoutcounter_0_6_D <= ((NIDAQLogiccomp/Readtimeouten AND
      NIDAQLogiccomp/Readtimeoutcounter_0_6 AND
      NOT NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0005/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0005_D2)
      OR (NIDAQLogiccomp/Readtimeouten AND
      NIDAQLogiccomp/Readtimeoutcounter_0_5 AND
      NOT NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0005/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0005_D2 AND
      NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0003/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0003_D2));

FDCPE_NIDAQLogiccomp/Readtimeoutcounter_0_7: FDCPE port map (NIDAQLogiccomp/Readtimeoutcounter_0_7,NIDAQLogiccomp/Readtimeoutcounter_0_7_D,clk,rst,'0');
     NIDAQLogiccomp/Readtimeoutcounter_0_7_D <= ((NIDAQLogiccomp/Readtimeouten AND
      NIDAQLogiccomp/Readtimeoutcounter_0_7 AND
      NOT NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0005/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0005_D2)
      OR (NIDAQLogiccomp/Readtimeouten AND
      NOT NIDAQLogiccomp/Readtimeoutcounter_0_7 AND
      NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0005/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0005_D2));

FTCPE_NIDAQLogiccomp/Readtimeoutcounter_0_8: FTCPE port map (NIDAQLogiccomp/Readtimeoutcounter_0_8,NIDAQLogiccomp/Readtimeoutcounter_0_8_T,clk,rst,'0');
     NIDAQLogiccomp/Readtimeoutcounter_0_8_T <= ((NOT NIDAQLogiccomp/Readtimeouten AND
      NIDAQLogiccomp/Readtimeoutcounter_0_8)
      OR (NIDAQLogiccomp/Readtimeouten AND
      NIDAQLogiccomp/Readtimeoutcounter_0_7 AND
      NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0005/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0005_D2));

FDCPE_NIDAQLogiccomp/Readtimeoutcounter_0_9: FDCPE port map (NIDAQLogiccomp/Readtimeoutcounter_0_9,NIDAQLogiccomp/Readtimeoutcounter_0_9_D,clk,rst,'0');
     NIDAQLogiccomp/Readtimeoutcounter_0_9_D <= ((NIDAQLogiccomp/Readtimeouten AND
      NIDAQLogiccomp/Readtimeoutcounter_0_9 AND
      NOT NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0008/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0008_D2)
      OR (NIDAQLogiccomp/Readtimeouten AND
      NIDAQLogiccomp/Readtimeoutcounter_0_7 AND NIDAQLogiccomp/Readtimeoutcounter_0_8 AND
      NOT NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0008/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0008_D2 AND
      NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0005/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0005_D2));

NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0003/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0003_D2 <= (NIDAQLogiccomp/Readtimeoutcounter_0_0 AND
NIDAQLogiccomp/Readtimeoutcounter_0_1 AND NIDAQLogiccomp/Readtimeoutcounter_0_2 AND
NIDAQLogiccomp/Readtimeoutcounter_0_3 AND NIDAQLogiccomp/Readtimeoutcounter_0_4);

NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0005/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0005_D2 <= (NIDAQLogiccomp/Readtimeoutcounter_0_5 AND
NIDAQLogiccomp/Readtimeoutcounter_0_6 AND
NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0003/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0003_D2);

NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0008/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0008_D2 <= (NIDAQLogiccomp/Readtimeoutcounter_0_7 AND
NIDAQLogiccomp/Readtimeoutcounter_0_8 AND NIDAQLogiccomp/Readtimeoutcounter_0_9 AND
NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0005/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0005_D2);

NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0010/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0010_D2 <= (NIDAQLogiccomp/Readtimeoutcounter_0_10 AND
NIDAQLogiccomp/Readtimeoutcounter_0_11 AND
NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0008/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0008_D2);

NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0013/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0013_D2 <= (NIDAQLogiccomp/Readtimeoutcounter_0_12 AND
NIDAQLogiccomp/Readtimeoutcounter_0_13 AND NIDAQLogiccomp/Readtimeoutcounter_0_14 AND
NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0010/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0010_D2);

FDCPE_NIDAQLogiccomp/Readtimeouten: FDCPE port map (NIDAQLogiccomp/Readtimeouten,NIDAQLogiccomp/Readtimeouten_D,clk,rst,'0');
NIDAQLogiccomp/Readtimeouten_D <= (NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NIDAQLogiccomp/NIDAQSTATE_FFd3);

FTCPE_NIDAQLogiccomp/SendingPackageFlag: FTCPE port map (NIDAQLogiccomp/SendingPackageFlag,NIDAQLogiccomp/SendingPackageFlag_T,clk,rst,'0');
     NIDAQLogiccomp/SendingPackageFlag_T <= ((NOT NIDAQLogiccomp/SendingPackageFlag AND
      EventReadoutsig AND EFn)
      OR (NIDAQLogiccomp/SendingPackageFlag AND
      NOT NIDAQLogiccomp/NumOfWordsSentCounter(0) AND NOT NIDAQLogiccomp/NumOfWordsSentCounter(1) AND
      NOT NIDAQLogiccomp/NumOfWordsSentCounter(2) AND NOT NIDAQLogiccomp/NumOfWordsSentCounter(3) AND
      NOT NIDAQLogiccomp/NumOfWordsSentCounter(4) AND NOT NIDAQLogiccomp/NumOfWordsSentCounter(5) AND
      NOT NIDAQLogiccomp/NumOfWordsSentCounter(6) AND NOT NIDAQLogiccomp/NumOfWordsSentCounter(7) AND
      NOT EventReadoutsig)
      OR (NIDAQLogiccomp/SendingPackageFlag AND
      NOT NIDAQLogiccomp/NumOfWordsSentCounter(0) AND NOT NIDAQLogiccomp/NumOfWordsSentCounter(1) AND
      NOT NIDAQLogiccomp/NumOfWordsSentCounter(2) AND NOT NIDAQLogiccomp/NumOfWordsSentCounter(3) AND
      NOT NIDAQLogiccomp/NumOfWordsSentCounter(4) AND NOT NIDAQLogiccomp/NumOfWordsSentCounter(5) AND
      NOT NIDAQLogiccomp/NumOfWordsSentCounter(6) AND NOT NIDAQLogiccomp/NumOfWordsSentCounter(7) AND NOT EFn));

FDCPE_NIDAQLogiccomp/StatusDatasig0: FDCPE port map (NIDAQLogiccomp/StatusDatasig(0),StatusDatasig(0),clk,'0','0',NOT rst);

FDCPE_NIDAQLogiccomp/StatusDatasig1: FDCPE port map (NIDAQLogiccomp/StatusDatasig(1),StatusDatasig(1),clk,'0','0',NOT rst);

FDCPE_NIDAQLogiccomp/StatusDatasig2: FDCPE port map (NIDAQLogiccomp/StatusDatasig(2),StatusDatasig(2),clk,'0','0',NOT rst);

FDCPE_NIDAQLogiccomp/StatusDatasig3: FDCPE port map (NIDAQLogiccomp/StatusDatasig(3),StatusDatasig(3),clk,'0','0',NOT rst);

FDCPE_NIDAQLogiccomp/StatusDatasig4: FDCPE port map (NIDAQLogiccomp/StatusDatasig(4),StatusDatasig(4),clk,'0','0',NOT rst);

FDCPE_NIDAQLogiccomp/StatusDatasig5: FDCPE port map (NIDAQLogiccomp/StatusDatasig(5),StatusDatasig(5),clk,'0','0',NOT rst);

FDCPE_NIDAQLogiccomp/StatusDatasig6: FDCPE port map (NIDAQLogiccomp/StatusDatasig(6),StatusDatasig(6),clk,'0','0',NOT rst);

FDCPE_NIDAQLogiccomp/StatusDatasig7: FDCPE port map (NIDAQLogiccomp/StatusDatasig(7),StatusDatasig(7),clk,'0','0',NOT rst);

FDCPE_NIDAQLogiccomp/StatusDatasig8: FDCPE port map (NIDAQLogiccomp/StatusDatasig(8),StatusDatasig(8),clk,'0','0',NOT rst);

FDCPE_NIDAQLogiccomp/StatusDatasig9: FDCPE port map (NIDAQLogiccomp/StatusDatasig(9),StatusDatasig(9),clk,'0','0',NOT rst);

FDCPE_NIDAQLogiccomp/StatusDatasig10: FDCPE port map (NIDAQLogiccomp/StatusDatasig(10),StatusDatasig(10),clk,'0','0',NOT rst);

FDCPE_NIDAQLogiccomp/StatusDatasig11: FDCPE port map (NIDAQLogiccomp/StatusDatasig(11),StatusDatasig(11),clk,'0','0',NOT rst);

FDCPE_NIDAQLogiccomp/StatusDatasig12: FDCPE port map (NIDAQLogiccomp/StatusDatasig(12),StatusDatasig(12),clk,'0','0',NOT rst);

FDCPE_NIDAQLogiccomp/StatusDatasig13: FDCPE port map (NIDAQLogiccomp/StatusDatasig(13),StatusDatasig(13),clk,'0','0',NOT rst);

FDCPE_NIDAQLogiccomp/StatusDatasig14: FDCPE port map (NIDAQLogiccomp/StatusDatasig(14),StatusDatasig(14),clk,'0','0',NOT rst);

FDCPE_NIDAQLogiccomp/StatusDatasig15: FDCPE port map (NIDAQLogiccomp/StatusDatasig(15),StatusDatasig(15),clk,'0','0',NOT rst);

FDCPE_NIDAQLogiccomp/cav: FDCPE port map (NIDAQLogiccomp/cav,NIDAQLogiccomp/cav_D,NOT clk,rst,'0');
NIDAQLogiccomp/cav_D <= (NOT NIDAQLogiccomp/NI_Interfacecomp/ack1_sync(1) AND
NIDAQLogiccomp/NI_Interfacecomp/ack1_sync(2));

FDCPE_NIDAQLogiccomp/command_out0: FDCPE port map (NIDAQLogiccomp/command_out(0),DIOB(0),clk,rst,'0');

FDCPE_NIDAQLogiccomp/command_out1: FDCPE port map (NIDAQLogiccomp/command_out(1),DIOB(1),clk,rst,'0');

FDCPE_NIDAQLogiccomp/command_out2: FDCPE port map (NIDAQLogiccomp/command_out(2),DIOB(2),clk,rst,'0');

FDCPE_NIDAQLogiccomp/command_out3: FDCPE port map (NIDAQLogiccomp/command_out(3),DIOB(3),clk,rst,'0');

FDCPE_NIDAQLogiccomp/command_out4: FDCPE port map (NIDAQLogiccomp/command_out(4),DIOB(4),clk,rst,'0');

FDCPE_NIDAQLogiccomp/command_out5: FDCPE port map (NIDAQLogiccomp/command_out(5),DIOB(5),clk,rst,'0');

FDCPE_NIDAQLogiccomp/command_out6: FDCPE port map (NIDAQLogiccomp/command_out(6),DIOB(6),clk,rst,'0');

FDCPE_NIDAQLogiccomp/command_out7: FDCPE port map (NIDAQLogiccomp/command_out(7),DIOB(7),clk,rst,'0');

FDCPE_NIDAQLogiccomp/command_out8: FDCPE port map (NIDAQLogiccomp/command_out(8),DIOA(0),clk,rst,'0');

FDCPE_NIDAQLogiccomp/command_out9: FDCPE port map (NIDAQLogiccomp/command_out(9),DIOA(1),clk,rst,'0');

FDCPE_NIDAQLogiccomp/command_out10: FDCPE port map (NIDAQLogiccomp/command_out(10),DIOA(2),clk,rst,'0');

FDCPE_NIDAQLogiccomp/command_out11: FDCPE port map (NIDAQLogiccomp/command_out(11),DIOA(3),clk,rst,'0');

FDCPE_NIDAQLogiccomp/command_out12: FDCPE port map (NIDAQLogiccomp/command_out(12),DIOA(4),clk,rst,'0');

FDCPE_NIDAQLogiccomp/command_out13: FDCPE port map (NIDAQLogiccomp/command_out(13),DIOA(5),clk,rst,'0');

FDCPE_NIDAQLogiccomp/command_out14: FDCPE port map (NIDAQLogiccomp/command_out(14),DIOA(6),clk,rst,'0');

FDCPE_NIDAQLogiccomp/command_out15: FDCPE port map (NIDAQLogiccomp/command_out(15),DIOA(7),clk,rst,'0');

FDCPE_NIDAQLogiccomp/wdone: FDCPE port map (NIDAQLogiccomp/wdone,NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd1,clk,rst,'0');

FDCPE_NIDAQLogiccomp/wen: FDCPE port map (NIDAQLogiccomp/wen,BUF_NIDAQLogiccomp/wen,clk,rst,'0');

OEn <= '0';

FDCPE_OPTCMD_Argsig0: FDCPE port map (OPTCMD_Argsig(0),OPTCMD_Argsig_D(0),clk,rst,'0');
     OPTCMD_Argsig_D(0) <= ((NOT MainLogiccomp/MAINSTATE_FFd2 AND OPTCMD_Argsig(0))
      OR (NICMD_Argsig(0) AND MainLogiccomp/MAINSTATE_FFd2 AND
      MainLogiccomp/MAINSTATE_FFd3));

FDCPE_OPTCMD_Argsig1: FDCPE port map (OPTCMD_Argsig(1),OPTCMD_Argsig_D(1),clk,rst,'0');
     OPTCMD_Argsig_D(1) <= ((NOT MainLogiccomp/MAINSTATE_FFd2 AND OPTCMD_Argsig(1))
      OR (NICMD_Argsig(1) AND MainLogiccomp/MAINSTATE_FFd2 AND
      MainLogiccomp/MAINSTATE_FFd3));

FDCPE_OPTCMD_Argsig2: FDCPE port map (OPTCMD_Argsig(2),OPTCMD_Argsig_D(2),clk,rst,'0');
     OPTCMD_Argsig_D(2) <= ((NOT MainLogiccomp/MAINSTATE_FFd2 AND OPTCMD_Argsig(2))
      OR (NICMD_Argsig(2) AND MainLogiccomp/MAINSTATE_FFd2 AND
      MainLogiccomp/MAINSTATE_FFd3));

FDCPE_OPTCMD_Argsig3: FDCPE port map (OPTCMD_Argsig(3),OPTCMD_Argsig_D(3),clk,rst,'0');
     OPTCMD_Argsig_D(3) <= ((NOT MainLogiccomp/MAINSTATE_FFd2 AND OPTCMD_Argsig(3))
      OR (NICMD_Argsig(3) AND MainLogiccomp/MAINSTATE_FFd2 AND
      MainLogiccomp/MAINSTATE_FFd3));

FDCPE_OPTCMD_Argsig4: FDCPE port map (OPTCMD_Argsig(4),OPTCMD_Argsig_D(4),clk,rst,'0');
     OPTCMD_Argsig_D(4) <= ((NOT MainLogiccomp/MAINSTATE_FFd2 AND OPTCMD_Argsig(4))
      OR (NICMD_Argsig(4) AND MainLogiccomp/MAINSTATE_FFd2 AND
      MainLogiccomp/MAINSTATE_FFd3));

FDCPE_OPTCMD_Argsig5: FDCPE port map (OPTCMD_Argsig(5),OPTCMD_Argsig_D(5),clk,rst,'0');
     OPTCMD_Argsig_D(5) <= ((NOT MainLogiccomp/MAINSTATE_FFd2 AND OPTCMD_Argsig(5))
      OR (NICMD_Argsig(5) AND MainLogiccomp/MAINSTATE_FFd2 AND
      MainLogiccomp/MAINSTATE_FFd3));

FDCPE_OPTCMD_Argsig6: FDCPE port map (OPTCMD_Argsig(6),OPTCMD_Argsig_D(6),clk,rst,'0');
     OPTCMD_Argsig_D(6) <= ((NOT MainLogiccomp/MAINSTATE_FFd2 AND OPTCMD_Argsig(6))
      OR (NICMD_Argsig(6) AND MainLogiccomp/MAINSTATE_FFd2 AND
      MainLogiccomp/MAINSTATE_FFd3));

FDCPE_OPTCMD_Argsig7: FDCPE port map (OPTCMD_Argsig(7),OPTCMD_Argsig_D(7),clk,rst,'0');
     OPTCMD_Argsig_D(7) <= ((NOT MainLogiccomp/MAINSTATE_FFd2 AND OPTCMD_Argsig(7))
      OR (NICMD_Argsig(7) AND MainLogiccomp/MAINSTATE_FFd2 AND
      MainLogiccomp/MAINSTATE_FFd3));

FDCPE_OPTCMD_Readysig: FDCPE port map (OPTCMD_Readysig,MainLogiccomp/MAINSTATE_FFd2,clk,rst,'0');

FDCPE_OPTCMDsig0: FDCPE port map (OPTCMDsig(0),OPTCMDsig_D(0),clk,rst,'0');
     OPTCMDsig_D(0) <= ((NOT MainLogiccomp/MAINSTATE_FFd2 AND OPTCMDsig(0))
      OR (NICMDsig(0) AND MainLogiccomp/MAINSTATE_FFd2 AND
      MainLogiccomp/MAINSTATE_FFd3));

FDCPE_OPTCMDsig1: FDCPE port map (OPTCMDsig(1),OPTCMDsig_D(1),clk,rst,'0');
     OPTCMDsig_D(1) <= ((NOT MainLogiccomp/MAINSTATE_FFd2 AND NOT OPTCMDsig(1))
      OR (NOT NICMDsig(1) AND MainLogiccomp/MAINSTATE_FFd2 AND
      MainLogiccomp/MAINSTATE_FFd3));

FDCPE_OPTCMDsig2: FDCPE port map (OPTCMDsig(2),OPTCMDsig_D(2),clk,rst,'0');
     OPTCMDsig_D(2) <= ((NOT MainLogiccomp/MAINSTATE_FFd2 AND NOT OPTCMDsig(2))
      OR (NOT NICMDsig(2) AND MainLogiccomp/MAINSTATE_FFd2 AND
      MainLogiccomp/MAINSTATE_FFd3));

FDCPE_OPTCMDsig3: FDCPE port map (OPTCMDsig(3),OPTCMDsig_D(3),clk,rst,'0');
     OPTCMDsig_D(3) <= ((NOT MainLogiccomp/MAINSTATE_FFd2 AND OPTCMDsig(3))
      OR (NICMDsig(3) AND MainLogiccomp/MAINSTATE_FFd2 AND
      MainLogiccomp/MAINSTATE_FFd3));

FDCPE_OPTCMDsig4: FDCPE port map (OPTCMDsig(4),OPTCMDsig_D(4),clk,rst,'0');
     OPTCMDsig_D(4) <= ((NOT MainLogiccomp/MAINSTATE_FFd2 AND OPTCMDsig(4))
      OR (SPARE(9) AND MainLogiccomp/MAINSTATE_FFd2 AND
      MainLogiccomp/MAINSTATE_FFd3));

FDCPE_OPTCMDsig5: FDCPE port map (OPTCMDsig(5),OPTCMDsig_D(5),clk,rst,'0');
     OPTCMDsig_D(5) <= ((NOT MainLogiccomp/MAINSTATE_FFd2 AND NOT OPTCMDsig(5))
      OR (NOT SPARE(10) AND MainLogiccomp/MAINSTATE_FFd2 AND
      MainLogiccomp/MAINSTATE_FFd3));

FDCPE_OPTCMDsig6: FDCPE port map (OPTCMDsig(6),OPTCMDsig_D(6),clk,rst,'0');
     OPTCMDsig_D(6) <= ((NOT MainLogiccomp/MAINSTATE_FFd2 AND NOT OPTCMDsig(6))
      OR (NOT SPARE(11) AND MainLogiccomp/MAINSTATE_FFd2 AND
      MainLogiccomp/MAINSTATE_FFd3));

FDCPE_OPTCMDsig7: FDCPE port map (OPTCMDsig(7),OPTCMDsig_D(7),clk,rst,'0');
     OPTCMDsig_D(7) <= ((NOT MainLogiccomp/MAINSTATE_FFd2 AND OPTCMDsig(7))
      OR (SPARE(12) AND MainLogiccomp/MAINSTATE_FFd2 AND
      MainLogiccomp/MAINSTATE_FFd3));

FDCPE_OpticalLogiccomp/GenSimDatasig: FDCPE port map (OpticalLogiccomp/GenSimDatasig,OpticalLogiccomp/GenSimDatasig_D,clk,rst,'0');
OpticalLogiccomp/GenSimDatasig_D <= (NOT OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
OpticalLogiccomp/OPTICALLOGICSTATE_FFd2);

FTCPE_OpticalLogiccomp/OPTICALLOGICSTATE_FFd1: FTCPE port map (OpticalLogiccomp/OPTICALLOGICSTATE_FFd1,OpticalLogiccomp/OPTICALLOGICSTATE_FFd1_T,clk,rst,'0');
     OpticalLogiccomp/OPTICALLOGICSTATE_FFd1_T <= ((NOT OpticalLogiccomp/TransmitCommandcomp/sending AND
      OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND OpticalLogiccomp/OPTICALLOGICSTATE_FFd2)
      OR (NOT OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
      NOT OpticalLogiccomp/OPTICALLOGICSTATE_FFd2 AND NOT OPTCMDsig(6) AND NOT OPTCMDsig(7) AND OPTCMD_Readysig)
      OR (NOT OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
      NOT OpticalLogiccomp/OPTICALLOGICSTATE_FFd2 AND OPTCMDsig(0) AND NOT OPTCMDsig(7) AND OPTCMDsig(1) AND
      OPTCMDsig(2) AND NOT OPTCMDsig(3) AND NOT OPTCMDsig(4) AND OPTCMDsig(5) AND
      OPTCMD_Readysig));

FTCPE_OpticalLogiccomp/OPTICALLOGICSTATE_FFd2: FTCPE port map (OpticalLogiccomp/OPTICALLOGICSTATE_FFd2,OpticalLogiccomp/OPTICALLOGICSTATE_FFd2_T,clk,rst,'0');
     OpticalLogiccomp/OPTICALLOGICSTATE_FFd2_T <= ((NOT OpticalLogiccomp/TransmitCommandcomp/sending AND
      OpticalLogiccomp/OPTICALLOGICSTATE_FFd1)
      OR (NOT OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
      OpticalLogiccomp/OPTICALLOGICSTATE_FFd2)
      OR (NOT OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
      NOT OPTCMDsig(0) AND OPTCMDsig(6) AND NOT OPTCMDsig(7) AND OPTCMDsig(1) AND
      OPTCMDsig(2) AND NOT OPTCMDsig(3) AND NOT OPTCMDsig(4) AND OPTCMDsig(5) AND
      OPTCMD_Readysig));

FDCPE_OpticalLogiccomp/RxDataLogiccomp/Busy: FDCPE port map (OpticalLogiccomp/RxDataLogiccomp/Busy,OpticalLogiccomp/RxDataLogiccomp/Busy_D,clk,rst,'0');
     OpticalLogiccomp/RxDataLogiccomp/Busy_D <= (
      NOT OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd1 AND
      NOT OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd2);

FDCPE_OpticalLogiccomp/RxDataLogiccomp/EventReadyCmd: FDCPE port map (OpticalLogiccomp/RxDataLogiccomp/EventReadyCmd,OpticalLogiccomp/RxDataLogiccomp/EventReadyCmd_D,clk,rst,'0');
OpticalLogiccomp/RxDataLogiccomp/EventReadyCmd_D <= (
OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd2 AND OpticalLogiccomp/RxDataLogiccomp/GenDataDonesig);

FDCPE_OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig0: FDCPE port map (OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(0),D(0),clk,rst,'0');

FDCPE_OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig1: FDCPE port map (OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(1),D(1),clk,rst,'0');

FDCPE_OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig2: FDCPE port map (OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(2),D(2),clk,rst,'0');

FDCPE_OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig3: FDCPE port map (OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(3),D(3),clk,rst,'0');

FDCPE_OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig4: FDCPE port map (OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(4),D(4),clk,rst,'0');

FDCPE_OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig5: FDCPE port map (OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(5),D(5),clk,rst,'0');

FDCPE_OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig6: FDCPE port map (OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(6),D(6),clk,rst,'0');

FDCPE_OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig7: FDCPE port map (OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(7),D(7),clk,rst,'0');

FDCPE_OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig8: FDCPE port map (OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(8),D(8),clk,rst,'0');

FDCPE_OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig9: FDCPE port map (OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(9),D(9),clk,rst,'0');

FDCPE_OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig10: FDCPE port map (OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(10),D(10),clk,rst,'0');

FDCPE_OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig11: FDCPE port map (OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(11),D(11),clk,rst,'0');

FDCPE_OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig12: FDCPE port map (OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(12),D(12),clk,rst,'0');

FDCPE_OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig13: FDCPE port map (OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(13),D(13),clk,rst,'0');

FDCPE_OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig14: FDCPE port map (OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(14),D(14),clk,rst,'0');

FDCPE_OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig15: FDCPE port map (OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(15),D(15),clk,rst,'0');

FDCPE_OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_0: FDCPE port map (OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_0,OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_0_D,clk,rst,'0');
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_0_D <= (OpticalLogiccomp/RxDataLogiccomp/Busy AND
NOT OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_0);

FDCPE_OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_1: FDCPE port map (OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_1,OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_1_D,clk,rst,'0');
     OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_1_D <= ((OpticalLogiccomp/RxDataLogiccomp/Busy AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_0 AND
      NOT OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_1)
      OR (OpticalLogiccomp/RxDataLogiccomp/Busy AND
      NOT OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_0 AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_1));

FTCPE_OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_10: FTCPE port map (OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_10,OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_10_T,clk,rst,'0');
     OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_10_T <= ((NOT OpticalLogiccomp/RxDataLogiccomp/Busy AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_10)
      OR (OpticalLogiccomp/RxDataLogiccomp/Busy AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_9 AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0007/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0007_D2));

FTCPE_OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_11: FTCPE port map (OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_11,OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_11_T,clk,rst,'0');
     OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_11_T <= ((NOT OpticalLogiccomp/RxDataLogiccomp/Busy AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_11)
      OR (OpticalLogiccomp/RxDataLogiccomp/Busy AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_10 AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_9 AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0007/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0007_D2));

FDCPE_OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_12: FDCPE port map (OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_12,OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_12_D,clk,rst,'0');
     OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_12_D <= ((OpticalLogiccomp/RxDataLogiccomp/Busy AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_12 AND
      NOT OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0011/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0011_D2)
      OR (OpticalLogiccomp/RxDataLogiccomp/Busy AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_10 AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_11 AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_9 AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0007/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0007_D2 AND
      NOT OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0011/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0011_D2));

FDCPE_OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_13: FDCPE port map (OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_13,OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_13_D,clk,rst,'0');
     OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_13_D <= ((OpticalLogiccomp/RxDataLogiccomp/Busy AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_13 AND
      NOT OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0011/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0011_D2)
      OR (OpticalLogiccomp/RxDataLogiccomp/Busy AND
      NOT OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_13 AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0011/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0011_D2));

FTCPE_OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_14: FTCPE port map (OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_14,OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_14_T,clk,rst,'0');
     OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_14_T <= ((NOT OpticalLogiccomp/RxDataLogiccomp/Busy AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_14)
      OR (OpticalLogiccomp/RxDataLogiccomp/Busy AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_13 AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0011/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0011_D2));

FTCPE_OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_15: FTCPE port map (OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_15,OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_15_T,clk,rst,'0');
     OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_15_T <= ((NOT OpticalLogiccomp/RxDataLogiccomp/Busy AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_15)
      OR (OpticalLogiccomp/RxDataLogiccomp/Busy AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_13 AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_14 AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0011/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0011_D2));

FTCPE_OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_2: FTCPE port map (OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_2,OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_2_T,clk,rst,'0');
     OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_2_T <= ((NOT OpticalLogiccomp/RxDataLogiccomp/Busy AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_2)
      OR (OpticalLogiccomp/RxDataLogiccomp/Busy AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_0 AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_1));

FTCPE_OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_3: FTCPE port map (OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_3,OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_3_T,clk,rst,'0');
     OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_3_T <= ((NOT OpticalLogiccomp/RxDataLogiccomp/Busy AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_3)
      OR (OpticalLogiccomp/RxDataLogiccomp/Busy AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_0 AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_1 AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_2));

FDCPE_OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_4: FDCPE port map (OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_4,OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_4_D,clk,rst,'0');
     OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_4_D <= ((OpticalLogiccomp/RxDataLogiccomp/Busy AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_4 AND
      NOT OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0003/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0003_D2)
      OR (OpticalLogiccomp/RxDataLogiccomp/Busy AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_0 AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_1 AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_2 AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_3 AND
      NOT OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0003/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0003_D2));

FDCPE_OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_5: FDCPE port map (OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_5,OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_5_D,clk,rst,'0');
     OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_5_D <= ((OpticalLogiccomp/RxDataLogiccomp/Busy AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_5 AND
      NOT OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0003/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0003_D2)
      OR (OpticalLogiccomp/RxDataLogiccomp/Busy AND
      NOT OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_5 AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0003/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0003_D2));

FTCPE_OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_6: FTCPE port map (OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_6,OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_6_T,clk,rst,'0');
     OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_6_T <= ((NOT OpticalLogiccomp/RxDataLogiccomp/Busy AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_6)
      OR (OpticalLogiccomp/RxDataLogiccomp/Busy AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_5 AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0003/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0003_D2));

FTCPE_OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_7: FTCPE port map (OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_7,OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_7_T,clk,rst,'0');
     OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_7_T <= ((NOT OpticalLogiccomp/RxDataLogiccomp/Busy AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_7)
      OR (OpticalLogiccomp/RxDataLogiccomp/Busy AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_5 AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_6 AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0003/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0003_D2));

FDCPE_OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_8: FDCPE port map (OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_8,OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_8_D,clk,rst,'0');
     OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_8_D <= ((OpticalLogiccomp/RxDataLogiccomp/Busy AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_8 AND
      NOT OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0007/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0007_D2)
      OR (OpticalLogiccomp/RxDataLogiccomp/Busy AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_5 AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_6 AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_7 AND
      NOT OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0007/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0007_D2 AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0003/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0003_D2));

FDCPE_OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_9: FDCPE port map (OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_9,OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_9_D,clk,rst,'0');
     OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_9_D <= ((OpticalLogiccomp/RxDataLogiccomp/Busy AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_9 AND
      NOT OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0007/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0007_D2)
      OR (OpticalLogiccomp/RxDataLogiccomp/Busy AND
      NOT OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_9 AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0007/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0007_D2));

OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0003/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0003_D2 <= (
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_0 AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_1 AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_2 AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_3 AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_4);

OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0007/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0007_D2 <= (
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_5 AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_6 AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_7 AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_8 AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0003/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0003_D2);

OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0011/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0011_D2 <= (
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_10 AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_11 AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_12 AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_9 AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0007/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0007_D2);

FDCPE_OpticalLogiccomp/RxDataLogiccomp/GenDataDonesig: FDCPE port map (OpticalLogiccomp/RxDataLogiccomp/GenDataDonesig,OpticalLogiccomp/RxDataLogiccomp/GenDataDonesig_D,clk,rst,'0');
     OpticalLogiccomp/RxDataLogiccomp/GenDataDonesig_D <= (
      NOT OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_0 AND
      NOT OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_1 AND
      NOT OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_10 AND
      NOT OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_11 AND
      OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_12 AND
      NOT OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_13 AND
      NOT OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_14 AND
      NOT OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_2 AND
      NOT OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_3 AND
      NOT OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_4 AND
      NOT OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_5 AND
      NOT OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_6 AND
      NOT OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_7 AND
      NOT OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_8 AND
      NOT OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_9 AND
      NOT OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_15);

FTCPE_OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd1: FTCPE port map (OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd1,OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd1_T,clk,rst,'0');
     OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd1_T <= ((
      OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd1 AND
      OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd2 AND OpticalLogiccomp/RxDataLogiccomp/GenDataDonesig)
      OR (
      NOT OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd1 AND
      NOT OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd2 AND OpticalLogiccomp/GenSimDatasig));

FTCPE_OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd2: FTCPE port map (OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd2,OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd2_T,clk,rst,'0');
     OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd2_T <= ((
      OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd1 AND
      NOT OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd2)
      OR (
      OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd2 AND OpticalLogiccomp/RxDataLogiccomp/GenDataDonesig)
      OR (
      NOT OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd2 AND NOT OpticalLogiccomp/GenSimDatasig AND
      NOT OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(0) AND NOT OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(10) AND
      OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(11) AND NOT OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(12) AND
      OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(13) AND NOT OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(14) AND
      OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(15) AND OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(1) AND
      NOT OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(2) AND OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(3) AND
      NOT OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(4) AND OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(5) AND
      NOT OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(6) AND OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(7) AND
      NOT OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(8) AND OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(9) AND
      DATAOK AND NOT RXERROR));

FDCPE_OpticalLogiccomp/TransmitCommandcomp/cnt0: FDCPE port map (OpticalLogiccomp/TransmitCommandcomp/cnt(0),OpticalLogiccomp/TransmitCommandcomp/cnt_D(0),clk,rst,'0');
OpticalLogiccomp/TransmitCommandcomp/cnt_D(0) <= (OpticalLogiccomp/TransmitCommandcomp/sending AND
OpticalLogiccomp/TransmitCommandcomp/cnt(0));

FDCPE_OpticalLogiccomp/TransmitCommandcomp/cnt1: FDCPE port map (OpticalLogiccomp/TransmitCommandcomp/cnt(1),OpticalLogiccomp/TransmitCommandcomp/cnt_D(1),clk,rst,'0');
     OpticalLogiccomp/TransmitCommandcomp/cnt_D(1) <= ((OpticalLogiccomp/TransmitCommandcomp/sending AND
      OpticalLogiccomp/TransmitCommandcomp/cnt(0) AND NOT OpticalLogiccomp/TransmitCommandcomp/cnt(1))
      OR (OpticalLogiccomp/TransmitCommandcomp/sending AND
      NOT OpticalLogiccomp/TransmitCommandcomp/cnt(0) AND OpticalLogiccomp/TransmitCommandcomp/cnt(1)));

FTCPE_OpticalLogiccomp/TransmitCommandcomp/cnt2: FTCPE port map (OpticalLogiccomp/TransmitCommandcomp/cnt(2),OpticalLogiccomp/TransmitCommandcomp/cnt_T(2),clk,rst,'0');
     OpticalLogiccomp/TransmitCommandcomp/cnt_T(2) <= ((NOT OpticalLogiccomp/TransmitCommandcomp/sending AND
      OpticalLogiccomp/TransmitCommandcomp/cnt(2))
      OR (OpticalLogiccomp/TransmitCommandcomp/sending AND
      NOT OpticalLogiccomp/TransmitCommandcomp/cnt(0) AND NOT OpticalLogiccomp/TransmitCommandcomp/cnt(1)));

FDCPE_OpticalLogiccomp/TransmitCommandcomp/cnt3: FDCPE port map (OpticalLogiccomp/TransmitCommandcomp/cnt(3),OpticalLogiccomp/TransmitCommandcomp/cnt_D(3),clk,rst,'0');
     OpticalLogiccomp/TransmitCommandcomp/cnt_D(3) <= ((OpticalLogiccomp/TransmitCommandcomp/sending AND
      OpticalLogiccomp/TransmitCommandcomp/cnt(3) AND
      NOT OpticalLogiccomp/TransmitCommandcomp/cnt_Msub__sub0000__or0001/OpticalLogiccomp/TransmitCommandcomp/cnt_Msub__sub0000__or0001_D2)
      OR (OpticalLogiccomp/TransmitCommandcomp/sending AND
      NOT OpticalLogiccomp/TransmitCommandcomp/cnt(3) AND
      OpticalLogiccomp/TransmitCommandcomp/cnt_Msub__sub0000__or0001/OpticalLogiccomp/TransmitCommandcomp/cnt_Msub__sub0000__or0001_D2));

FTCPE_OpticalLogiccomp/TransmitCommandcomp/cnt4: FTCPE port map (OpticalLogiccomp/TransmitCommandcomp/cnt(4),OpticalLogiccomp/TransmitCommandcomp/cnt_T(4),clk,rst,'0');
     OpticalLogiccomp/TransmitCommandcomp/cnt_T(4) <= ((NOT OpticalLogiccomp/TransmitCommandcomp/sending AND
      NOT OpticalLogiccomp/TransmitCommandcomp/cnt(4))
      OR (OpticalLogiccomp/TransmitCommandcomp/sending AND
      NOT OpticalLogiccomp/TransmitCommandcomp/cnt(3) AND
      OpticalLogiccomp/TransmitCommandcomp/cnt_Msub__sub0000__or0001/OpticalLogiccomp/TransmitCommandcomp/cnt_Msub__sub0000__or0001_D2));

OpticalLogiccomp/TransmitCommandcomp/cnt_Msub__sub0000__or0001/OpticalLogiccomp/TransmitCommandcomp/cnt_Msub__sub0000__or0001_D2 <= (NOT OpticalLogiccomp/TransmitCommandcomp/cnt(0) AND
NOT OpticalLogiccomp/TransmitCommandcomp/cnt(1) AND NOT OpticalLogiccomp/TransmitCommandcomp/cnt(2));

FDCPE_OpticalLogiccomp/TransmitCommandcomp/sending: FDCPE port map (OpticalLogiccomp/TransmitCommandcomp/sending,OpticalLogiccomp/TransmitCommandcomp/sending_D,clk,rst,'0');
     OpticalLogiccomp/TransmitCommandcomp/sending_D <= (NOT OpticalLogiccomp/TransmitCommandcomp/cnt(0) AND
      NOT OpticalLogiccomp/TransmitCommandcomp/cnt(1) AND NOT OpticalLogiccomp/TransmitCommandcomp/cnt(2) AND
      NOT OpticalLogiccomp/TransmitCommandcomp/cnt(3) AND NOT OpticalLogiccomp/TransmitCommandcomp/cnt(4));

FDCPE_OpticalLogiccomp/TransmitCommandcomp/sr0: FDCPE port map (OpticalLogiccomp/TransmitCommandcomp/sr(0),OpticalLogiccomp/TransmitCommandcomp/sr_D(0),clk,rst,'0');
OpticalLogiccomp/TransmitCommandcomp/sr_D(0) <= (OpticalLogiccomp/TransmitCommandcomp/sending AND
NOT OpticalLogiccomp/TransmitCommandcomp/sr(1));

FDCPE_OpticalLogiccomp/TransmitCommandcomp/sr1: FDCPE port map (OpticalLogiccomp/TransmitCommandcomp/sr(1),OpticalLogiccomp/TransmitCommandcomp/sr_D(1),clk,rst,'0');
OpticalLogiccomp/TransmitCommandcomp/sr_D(1) <= (OpticalLogiccomp/TransmitCommandcomp/sending AND
NOT OpticalLogiccomp/TransmitCommandcomp/sr(2));

FDCPE_OpticalLogiccomp/TransmitCommandcomp/sr2: FDCPE port map (OpticalLogiccomp/TransmitCommandcomp/sr(2),OpticalLogiccomp/TransmitCommandcomp/sr_D(2),clk,rst,'0');
OpticalLogiccomp/TransmitCommandcomp/sr_D(2) <= (OpticalLogiccomp/TransmitCommandcomp/sending AND
OpticalLogiccomp/TransmitCommandcomp/sr(3));

FDCPE_OpticalLogiccomp/TransmitCommandcomp/sr3: FDCPE port map (OpticalLogiccomp/TransmitCommandcomp/sr(3),OpticalLogiccomp/TransmitCommandcomp/sr_D(3),clk,rst,'0');
OpticalLogiccomp/TransmitCommandcomp/sr_D(3) <= (OpticalLogiccomp/TransmitCommandcomp/sending AND
NOT OpticalLogiccomp/TransmitCommandcomp/sr(4));

FDCPE_OpticalLogiccomp/TransmitCommandcomp/sr4: FDCPE port map (OpticalLogiccomp/TransmitCommandcomp/sr(4),OpticalLogiccomp/TransmitCommandcomp/sr_D(4),clk,rst,'0');
     OpticalLogiccomp/TransmitCommandcomp/sr_D(4) <= ((OpticalLogiccomp/TransmitCommandcomp/sending AND
      OpticalLogiccomp/TransmitCommandcomp/sr(5))
      OR (NOT OpticalLogiccomp/TransmitCommandcomp/sending AND
      OpticalLogiccomp/command_insig(0)));

FDCPE_OpticalLogiccomp/TransmitCommandcomp/sr5: FDCPE port map (OpticalLogiccomp/TransmitCommandcomp/sr(5),OpticalLogiccomp/TransmitCommandcomp/sr_D(5),clk,rst,'0');
     OpticalLogiccomp/TransmitCommandcomp/sr_D(5) <= ((OpticalLogiccomp/TransmitCommandcomp/sending AND
      OpticalLogiccomp/TransmitCommandcomp/sr(6))
      OR (NOT OpticalLogiccomp/TransmitCommandcomp/sending AND
      OpticalLogiccomp/command_insig(1)));

FDCPE_OpticalLogiccomp/TransmitCommandcomp/sr6: FDCPE port map (OpticalLogiccomp/TransmitCommandcomp/sr(6),OpticalLogiccomp/TransmitCommandcomp/sr_D(6),clk,rst,'0');
     OpticalLogiccomp/TransmitCommandcomp/sr_D(6) <= ((OpticalLogiccomp/TransmitCommandcomp/sending AND
      OpticalLogiccomp/TransmitCommandcomp/sr(7))
      OR (NOT OpticalLogiccomp/TransmitCommandcomp/sending AND
      OpticalLogiccomp/command_insig(2)));

FDCPE_OpticalLogiccomp/TransmitCommandcomp/sr7: FDCPE port map (OpticalLogiccomp/TransmitCommandcomp/sr(7),OpticalLogiccomp/TransmitCommandcomp/sr_D(7),clk,rst,'0');
     OpticalLogiccomp/TransmitCommandcomp/sr_D(7) <= ((OpticalLogiccomp/TransmitCommandcomp/sending AND
      OpticalLogiccomp/TransmitCommandcomp/sr(8))
      OR (NOT OpticalLogiccomp/TransmitCommandcomp/sending AND
      OpticalLogiccomp/command_insig(3)));

FDCPE_OpticalLogiccomp/TransmitCommandcomp/sr8: FDCPE port map (OpticalLogiccomp/TransmitCommandcomp/sr(8),OpticalLogiccomp/TransmitCommandcomp/sr_D(8),clk,rst,'0');
     OpticalLogiccomp/TransmitCommandcomp/sr_D(8) <= ((OpticalLogiccomp/TransmitCommandcomp/sending AND
      OpticalLogiccomp/TransmitCommandcomp/sr(9))
      OR (NOT OpticalLogiccomp/TransmitCommandcomp/sending AND
      OpticalLogiccomp/command_insig(4)));

FDCPE_OpticalLogiccomp/TransmitCommandcomp/sr9: FDCPE port map (OpticalLogiccomp/TransmitCommandcomp/sr(9),OpticalLogiccomp/TransmitCommandcomp/sr_D(9),clk,rst,'0');
     OpticalLogiccomp/TransmitCommandcomp/sr_D(9) <= ((OpticalLogiccomp/TransmitCommandcomp/sending AND
      OpticalLogiccomp/TransmitCommandcomp/sr(10))
      OR (NOT OpticalLogiccomp/TransmitCommandcomp/sending AND
      OpticalLogiccomp/command_insig(5)));

FDCPE_OpticalLogiccomp/TransmitCommandcomp/sr10: FDCPE port map (OpticalLogiccomp/TransmitCommandcomp/sr(10),OpticalLogiccomp/TransmitCommandcomp/sr_D(10),clk,rst,'0');
     OpticalLogiccomp/TransmitCommandcomp/sr_D(10) <= ((OpticalLogiccomp/TransmitCommandcomp/sending AND
      OpticalLogiccomp/TransmitCommandcomp/sr(11))
      OR (NOT OpticalLogiccomp/TransmitCommandcomp/sending AND
      OpticalLogiccomp/command_insig(6)));

FDCPE_OpticalLogiccomp/TransmitCommandcomp/sr11: FDCPE port map (OpticalLogiccomp/TransmitCommandcomp/sr(11),OpticalLogiccomp/TransmitCommandcomp/sr_D(11),clk,rst,'0');
     OpticalLogiccomp/TransmitCommandcomp/sr_D(11) <= ((OpticalLogiccomp/TransmitCommandcomp/sending AND
      OpticalLogiccomp/TransmitCommandcomp/sr(12))
      OR (NOT OpticalLogiccomp/TransmitCommandcomp/sending AND
      OpticalLogiccomp/command_insig(7)));

FDCPE_OpticalLogiccomp/TransmitCommandcomp/sr12: FDCPE port map (OpticalLogiccomp/TransmitCommandcomp/sr(12),OpticalLogiccomp/TransmitCommandcomp/sr_D(12),clk,rst,'0');
     OpticalLogiccomp/TransmitCommandcomp/sr_D(12) <= ((OpticalLogiccomp/TransmitCommandcomp/sending AND
      OpticalLogiccomp/TransmitCommandcomp/sr(13))
      OR (NOT OpticalLogiccomp/TransmitCommandcomp/sending AND
      OpticalLogiccomp/command_insig(8)));

FDCPE_OpticalLogiccomp/TransmitCommandcomp/sr13: FDCPE port map (OpticalLogiccomp/TransmitCommandcomp/sr(13),OpticalLogiccomp/TransmitCommandcomp/sr_D(13),clk,rst,'0');
     OpticalLogiccomp/TransmitCommandcomp/sr_D(13) <= ((OpticalLogiccomp/TransmitCommandcomp/sending AND
      OpticalLogiccomp/TransmitCommandcomp/sr(14))
      OR (NOT OpticalLogiccomp/TransmitCommandcomp/sending AND
      OpticalLogiccomp/command_insig(9)));

FDCPE_OpticalLogiccomp/TransmitCommandcomp/sr14: FDCPE port map (OpticalLogiccomp/TransmitCommandcomp/sr(14),OpticalLogiccomp/TransmitCommandcomp/sr_D(14),clk,rst,'0');
     OpticalLogiccomp/TransmitCommandcomp/sr_D(14) <= ((OpticalLogiccomp/TransmitCommandcomp/sending AND
      OpticalLogiccomp/TransmitCommandcomp/sr(15))
      OR (NOT OpticalLogiccomp/TransmitCommandcomp/sending AND
      OpticalLogiccomp/command_insig(10)));

FDCPE_OpticalLogiccomp/TransmitCommandcomp/sr15: FDCPE port map (OpticalLogiccomp/TransmitCommandcomp/sr(15),OpticalLogiccomp/TransmitCommandcomp/sr_D(15),clk,rst,'0');
     OpticalLogiccomp/TransmitCommandcomp/sr_D(15) <= ((OpticalLogiccomp/TransmitCommandcomp/sending AND
      OpticalLogiccomp/TransmitCommandcomp/sr(16))
      OR (NOT OpticalLogiccomp/TransmitCommandcomp/sending AND
      OpticalLogiccomp/command_insig(11)));

FDCPE_OpticalLogiccomp/TransmitCommandcomp/sr16: FDCPE port map (OpticalLogiccomp/TransmitCommandcomp/sr(16),OpticalLogiccomp/TransmitCommandcomp/sr_D(16),clk,rst,'0');
     OpticalLogiccomp/TransmitCommandcomp/sr_D(16) <= ((OpticalLogiccomp/TransmitCommandcomp/sending AND
      OpticalLogiccomp/TransmitCommandcomp/sr(17))
      OR (NOT OpticalLogiccomp/TransmitCommandcomp/sending AND
      OpticalLogiccomp/command_insig(12)));

FDCPE_OpticalLogiccomp/TransmitCommandcomp/sr17: FDCPE port map (OpticalLogiccomp/TransmitCommandcomp/sr(17),OpticalLogiccomp/TransmitCommandcomp/sr_D(17),clk,rst,'0');
     OpticalLogiccomp/TransmitCommandcomp/sr_D(17) <= ((OpticalLogiccomp/TransmitCommandcomp/sending AND
      OpticalLogiccomp/TransmitCommandcomp/sr(18))
      OR (NOT OpticalLogiccomp/TransmitCommandcomp/sending AND
      OpticalLogiccomp/command_insig(13)));

FDCPE_OpticalLogiccomp/TransmitCommandcomp/sr18: FDCPE port map (OpticalLogiccomp/TransmitCommandcomp/sr(18),OpticalLogiccomp/TransmitCommandcomp/sr_D(18),clk,rst,'0');
     OpticalLogiccomp/TransmitCommandcomp/sr_D(18) <= ((OpticalLogiccomp/TransmitCommandcomp/sr(19) AND
      OpticalLogiccomp/TransmitCommandcomp/sending)
      OR (NOT OpticalLogiccomp/TransmitCommandcomp/sending AND
      OpticalLogiccomp/command_insig(14)));

FDCPE_OpticalLogiccomp/TransmitCommandcomp/sr19: FDCPE port map (OpticalLogiccomp/TransmitCommandcomp/sr(19),OpticalLogiccomp/command_insig(15),clk,rst,'0',NOT OpticalLogiccomp/TransmitCommandcomp/sending);

FDCPE_OpticalLogiccomp/command_insig0: FDCPE port map (OpticalLogiccomp/command_insig(0),OpticalLogiccomp/command_insig_D(0),clk,rst,'0');
     OpticalLogiccomp/command_insig_D(0) <= ((OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
      OPTCMD_Argsig(0))
      OR (NOT OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
      OpticalLogiccomp/OPTICALLOGICSTATE_FFd2 AND OpticalLogiccomp/command_insig(0))
      OR (NOT OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
      NOT OpticalLogiccomp/OPTICALLOGICSTATE_FFd2 AND HFn));

FDCPE_OpticalLogiccomp/command_insig1: FDCPE port map (OpticalLogiccomp/command_insig(1),OpticalLogiccomp/command_insig_D(1),clk,rst,'0');
     OpticalLogiccomp/command_insig_D(1) <= ((OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
      OPTCMD_Argsig(1))
      OR (NOT OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
      OpticalLogiccomp/OPTICALLOGICSTATE_FFd2 AND OpticalLogiccomp/command_insig(1)));

FDCPE_OpticalLogiccomp/command_insig2: FDCPE port map (OpticalLogiccomp/command_insig(2),OpticalLogiccomp/command_insig_D(2),clk,rst,'0');
     OpticalLogiccomp/command_insig_D(2) <= ((OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
      OPTCMD_Argsig(2))
      OR (NOT OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
      OpticalLogiccomp/OPTICALLOGICSTATE_FFd2 AND OpticalLogiccomp/command_insig(2)));

FDCPE_OpticalLogiccomp/command_insig3: FDCPE port map (OpticalLogiccomp/command_insig(3),OpticalLogiccomp/command_insig_D(3),clk,rst,'0');
     OpticalLogiccomp/command_insig_D(3) <= ((OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
      OPTCMD_Argsig(3))
      OR (NOT OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
      OpticalLogiccomp/OPTICALLOGICSTATE_FFd2 AND OpticalLogiccomp/command_insig(3)));

FDCPE_OpticalLogiccomp/command_insig4: FDCPE port map (OpticalLogiccomp/command_insig(4),OpticalLogiccomp/command_insig_D(4),clk,rst,'0');
     OpticalLogiccomp/command_insig_D(4) <= ((OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
      OPTCMD_Argsig(4))
      OR (NOT OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
      OpticalLogiccomp/OPTICALLOGICSTATE_FFd2 AND OpticalLogiccomp/command_insig(4)));

FDCPE_OpticalLogiccomp/command_insig5: FDCPE port map (OpticalLogiccomp/command_insig(5),OpticalLogiccomp/command_insig_D(5),clk,rst,'0');
     OpticalLogiccomp/command_insig_D(5) <= ((OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
      OPTCMD_Argsig(5))
      OR (NOT OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
      OpticalLogiccomp/OPTICALLOGICSTATE_FFd2 AND OpticalLogiccomp/command_insig(5)));

FDCPE_OpticalLogiccomp/command_insig6: FDCPE port map (OpticalLogiccomp/command_insig(6),OpticalLogiccomp/command_insig_D(6),clk,rst,'0');
     OpticalLogiccomp/command_insig_D(6) <= ((OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
      OPTCMD_Argsig(6))
      OR (NOT OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
      OpticalLogiccomp/OPTICALLOGICSTATE_FFd2 AND OpticalLogiccomp/command_insig(6)));

FDCPE_OpticalLogiccomp/command_insig7: FDCPE port map (OpticalLogiccomp/command_insig(7),OpticalLogiccomp/command_insig_D(7),clk,rst,'0');
     OpticalLogiccomp/command_insig_D(7) <= ((OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
      OPTCMD_Argsig(7))
      OR (NOT OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
      OpticalLogiccomp/OPTICALLOGICSTATE_FFd2 AND OpticalLogiccomp/command_insig(7)));

FDCPE_OpticalLogiccomp/command_insig8: FDCPE port map (OpticalLogiccomp/command_insig(8),OpticalLogiccomp/command_insig_D(8),clk,rst,'0');
     OpticalLogiccomp/command_insig_D(8) <= ((OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
      NOT OPTCMDsig(0))
      OR (NOT OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
      OpticalLogiccomp/OPTICALLOGICSTATE_FFd2 AND NOT OpticalLogiccomp/command_insig(8)));

FDCPE_OpticalLogiccomp/command_insig9: FDCPE port map (OpticalLogiccomp/command_insig(9),OpticalLogiccomp/command_insig_D(9),clk,rst,'0');
     OpticalLogiccomp/command_insig_D(9) <= ((OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
      OPTCMDsig(1))
      OR (NOT OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
      OpticalLogiccomp/OPTICALLOGICSTATE_FFd2 AND OpticalLogiccomp/command_insig(9)));

FDCPE_OpticalLogiccomp/command_insig10: FDCPE port map (OpticalLogiccomp/command_insig(10),OpticalLogiccomp/command_insig_D(10),clk,rst,'0');
     OpticalLogiccomp/command_insig_D(10) <= ((OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
      OPTCMDsig(2))
      OR (NOT OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
      OpticalLogiccomp/OPTICALLOGICSTATE_FFd2 AND OpticalLogiccomp/command_insig(10)));

FDCPE_OpticalLogiccomp/command_insig11: FDCPE port map (OpticalLogiccomp/command_insig(11),OpticalLogiccomp/command_insig_D(11),clk,rst,'0');
     OpticalLogiccomp/command_insig_D(11) <= ((OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
      NOT OPTCMDsig(3))
      OR (NOT OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
      OpticalLogiccomp/OPTICALLOGICSTATE_FFd2 AND NOT OpticalLogiccomp/command_insig(11)));

FDCPE_OpticalLogiccomp/command_insig12: FDCPE port map (OpticalLogiccomp/command_insig(12),OpticalLogiccomp/command_insig_D(12),clk,rst,'0');
     OpticalLogiccomp/command_insig_D(12) <= ((OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
      OPTCMDsig(4))
      OR (NOT OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
      OpticalLogiccomp/OPTICALLOGICSTATE_FFd2 AND OpticalLogiccomp/command_insig(12)));

FDCPE_OpticalLogiccomp/command_insig13: FDCPE port map (OpticalLogiccomp/command_insig(13),OpticalLogiccomp/command_insig_D(13),clk,rst,'0');
     OpticalLogiccomp/command_insig_D(13) <= ((OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
      NOT OPTCMDsig(5))
      OR (NOT OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
      OpticalLogiccomp/OPTICALLOGICSTATE_FFd2 AND NOT OpticalLogiccomp/command_insig(13)));

FDCPE_OpticalLogiccomp/command_insig14: FDCPE port map (OpticalLogiccomp/command_insig(14),OpticalLogiccomp/command_insig_D(14),clk,rst,'0');
     OpticalLogiccomp/command_insig_D(14) <= ((OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
      NOT OPTCMDsig(6))
      OR (NOT OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
      OpticalLogiccomp/OPTICALLOGICSTATE_FFd2 AND NOT OpticalLogiccomp/command_insig(14)));

FDCPE_OpticalLogiccomp/command_insig15: FDCPE port map (OpticalLogiccomp/command_insig(15),OpticalLogiccomp/command_insig_D(15),clk,rst,'0');
     OpticalLogiccomp/command_insig_D(15) <= ((OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
      OPTCMDsig(7))
      OR (NOT OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
      OpticalLogiccomp/OPTICALLOGICSTATE_FFd2 AND OpticalLogiccomp/command_insig(15)));

RCLK <= clk;

FDCPE_RENn: FDCPE port map (RENn,RENn_D,clk,'0',rst);
RENn_D <= (NOT NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NIDAQLogiccomp/NIDAQSTATE_FFd3 AND NIDAQLogiccomp/NIDAQSTATE_FFd2);

FDCPE_REQ1: FDCPE port map (REQ1,NIDAQLogiccomp/NI_Interfacecomp/ack1_sync(2),NOT clk,rst,'0');

FDCPE_REQ2: FDCPE port map (REQ2,NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd3,clk,rst,'0');

FDCPE_RSTn: FDCPE port map (RSTn,'1',clk,rst,'0');

FDCPE_SPARE0: FDCPE port map (SPARE(0),SPARE_D(0),clk,rst,'0');
     SPARE_D(0) <= ((NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
      NOT NIDAQLogiccomp/NIDAQSTATE_FFd3 AND NIDAQLogiccomp/NIDAQSTATE_FFd2)
      OR (NOT NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
      NIDAQLogiccomp/NIDAQSTATE_FFd3 AND NIDAQLogiccomp/NIDAQSTATE_FFd2)
      OR (NOT NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
      NOT NIDAQLogiccomp/NIDAQSTATE_FFd3 AND NOT NIDAQLogiccomp/NIDAQSTATE_FFd2));

FDCPE_SPARE1: FDCPE port map (SPARE(1),SPARE_D(1),clk,rst,'0');
     SPARE_D(1) <= ((NIDAQLogiccomp/NIDAQSTATE_FFd3 AND
      NOT NIDAQLogiccomp/NIDAQSTATE_FFd2)
      OR (NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
      NOT NIDAQLogiccomp/NIDAQSTATE_FFd3 AND NIDAQLogiccomp/NIDAQSTATE_FFd2));

FDCPE_SPARE2: FDCPE port map (SPARE(2),SPARE_D(2),clk,rst,'0');
     SPARE_D(2) <= ((NOT NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
      NIDAQLogiccomp/NIDAQSTATE_FFd3)
      OR (NOT NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
      NIDAQLogiccomp/NIDAQSTATE_FFd2));

FDCPE_SPARE3: FDCPE port map (SPARE(3),NIDAQLogiccomp/cav,clk,rst,'0');

FDCPE_SPARE4: FDCPE port map (SPARE(4),SPARE_D(4),clk,rst,'0');
SPARE_D(4) <= (NOT NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NOT NIDAQLogiccomp/NIDAQSTATE_FFd3 AND NOT NIDAQLogiccomp/NIDAQSTATE_FFd2);

FDCPE_SPARE5: FDCPE port map (SPARE(5),NIDAQLogiccomp/NI_Interfacecomp/ack1_sync(2),NOT clk,rst,'0');

SPARE(6) <= ACK1;

FDCPE_SPARE7: FDCPE port map (SPARE(7),NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd3,clk,rst,'0');

SPARE(8) <= ACK2;

FDCPE_SPARE9: FDCPE port map (SPARE(9),NIDAQLogiccomp/command_out(12),clk,rst,'0',SPARE_CE(9));
SPARE_CE(9) <= (NOT NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NIDAQLogiccomp/NIDAQSTATE_FFd3 AND NOT NIDAQLogiccomp/NIDAQSTATE_FFd2);

FDCPE_SPARE10: FDCPE port map (SPARE(10),NIDAQLogiccomp/command_out(13),clk,rst,'0',SPARE_CE(10));
SPARE_CE(10) <= (NOT NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NIDAQLogiccomp/NIDAQSTATE_FFd3 AND NOT NIDAQLogiccomp/NIDAQSTATE_FFd2);

FDCPE_SPARE11: FDCPE port map (SPARE(11),NIDAQLogiccomp/command_out(14),clk,rst,'0',SPARE_CE(11));
SPARE_CE(11) <= (NOT NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NIDAQLogiccomp/NIDAQSTATE_FFd3 AND NOT NIDAQLogiccomp/NIDAQSTATE_FFd2);

FDCPE_SPARE12: FDCPE port map (SPARE(12),NIDAQLogiccomp/command_out(15),clk,rst,'0',SPARE_CE(12));
SPARE_CE(12) <= (NOT NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NIDAQLogiccomp/NIDAQSTATE_FFd3 AND NOT NIDAQLogiccomp/NIDAQSTATE_FFd2);

STOPTRIG1 <= '1';

STOPTRIG2 <= '1';

FDCPE_SendDataCmdsig: FDCPE port map (SendDataCmdsig,MainLogiccomp/MAINSTATE_FFd1,clk,rst,'0');

FDCPE_StatusDatasig0: FDCPE port map (StatusDatasig(0),StatusDatasig_D(0),clk,rst,'0');
     StatusDatasig_D(0) <= ((NOT MainLogiccomp/MAINSTATE_FFd1 AND StatusDatasig(0))
      OR (MainLogiccomp/MAINSTATE_FFd1 AND
      MainLogiccomp/MAINSTATE_FFd3 AND D(0))
      OR (MainLogiccomp/MAINSTATE_FFd1 AND
      NOT MainLogiccomp/MAINSTATE_FFd3 AND NOT EFn));

FDCPE_StatusDatasig1: FDCPE port map (StatusDatasig(1),StatusDatasig_D(1),clk,rst,'0');
     StatusDatasig_D(1) <= ((NOT MainLogiccomp/MAINSTATE_FFd1 AND StatusDatasig(1))
      OR (MainLogiccomp/MAINSTATE_FFd1 AND
      MainLogiccomp/MAINSTATE_FFd3 AND D(1))
      OR (MainLogiccomp/MAINSTATE_FFd1 AND
      NOT MainLogiccomp/MAINSTATE_FFd3 AND NOT FFn));

FDCPE_StatusDatasig2: FDCPE port map (StatusDatasig(2),StatusDatasig_D(2),clk,rst,'0');
     StatusDatasig_D(2) <= ((NOT MainLogiccomp/MAINSTATE_FFd1 AND StatusDatasig(2))
      OR (MainLogiccomp/MAINSTATE_FFd1 AND
      MainLogiccomp/MAINSTATE_FFd3 AND D(2))
      OR (MainLogiccomp/MAINSTATE_FFd1 AND
      NOT MainLogiccomp/MAINSTATE_FFd3 AND NOT HFn));

FDCPE_StatusDatasig3: FDCPE port map (StatusDatasig(3),StatusDatasig_D(3),clk,rst,'0');
     StatusDatasig_D(3) <= ((NOT MainLogiccomp/MAINSTATE_FFd1 AND StatusDatasig(3))
      OR (MainLogiccomp/MAINSTATE_FFd1 AND
      MainLogiccomp/MAINSTATE_FFd3 AND D(3))
      OR (MainLogiccomp/MAINSTATE_FFd1 AND
      NOT MainLogiccomp/MAINSTATE_FFd3 AND DATAOK));

FDCPE_StatusDatasig4: FDCPE port map (StatusDatasig(4),StatusDatasig_D(4),clk,rst,'0');
     StatusDatasig_D(4) <= ((NOT MainLogiccomp/MAINSTATE_FFd1 AND StatusDatasig(4))
      OR (MainLogiccomp/MAINSTATE_FFd1 AND
      MainLogiccomp/MAINSTATE_FFd3 AND D(4))
      OR (MainLogiccomp/MAINSTATE_FFd1 AND
      NOT MainLogiccomp/MAINSTATE_FFd3 AND RXREADY));

FDCPE_StatusDatasig5: FDCPE port map (StatusDatasig(5),StatusDatasig_D(5),clk,rst,'0');
     StatusDatasig_D(5) <= ((NOT MainLogiccomp/MAINSTATE_FFd1 AND StatusDatasig(5))
      OR (MainLogiccomp/MAINSTATE_FFd1 AND
      MainLogiccomp/MAINSTATE_FFd3 AND D(5))
      OR (MainLogiccomp/MAINSTATE_FFd1 AND
      NOT MainLogiccomp/MAINSTATE_FFd3 AND RXDATA));

FDCPE_StatusDatasig6: FDCPE port map (StatusDatasig(6),StatusDatasig_D(6),clk,rst,'0');
     StatusDatasig_D(6) <= ((NOT MainLogiccomp/MAINSTATE_FFd1 AND StatusDatasig(6))
      OR (MainLogiccomp/MAINSTATE_FFd1 AND
      MainLogiccomp/MAINSTATE_FFd3 AND D(6))
      OR (MainLogiccomp/MAINSTATE_FFd1 AND
      NOT MainLogiccomp/MAINSTATE_FFd3 AND RXERROR));

FDCPE_StatusDatasig7: FDCPE port map (StatusDatasig(7),StatusDatasig_D(7),clk,rst,'0');
     StatusDatasig_D(7) <= ((NOT MainLogiccomp/MAINSTATE_FFd1 AND StatusDatasig(7))
      OR (MainLogiccomp/MAINSTATE_FFd1 AND
      MainLogiccomp/MAINSTATE_FFd3 AND D(7))
      OR (MainLogiccomp/MAINSTATE_FFd1 AND
      NOT MainLogiccomp/MAINSTATE_FFd3 AND EventReadysig));

FDCPE_StatusDatasig8: FDCPE port map (StatusDatasig(8),StatusDatasig_D(8),clk,rst,'0');
     StatusDatasig_D(8) <= ((NOT MainLogiccomp/MAINSTATE_FFd1 AND StatusDatasig(8))
      OR (MainLogiccomp/MAINSTATE_FFd1 AND
      MainLogiccomp/MAINSTATE_FFd3 AND D(8)));

FDCPE_StatusDatasig9: FDCPE port map (StatusDatasig(9),StatusDatasig_D(9),clk,rst,'0');
     StatusDatasig_D(9) <= ((NOT MainLogiccomp/MAINSTATE_FFd1 AND StatusDatasig(9))
      OR (MainLogiccomp/MAINSTATE_FFd1 AND
      MainLogiccomp/MAINSTATE_FFd3 AND D(9)));

FDCPE_StatusDatasig10: FDCPE port map (StatusDatasig(10),StatusDatasig_D(10),clk,rst,'0');
     StatusDatasig_D(10) <= ((NOT MainLogiccomp/MAINSTATE_FFd1 AND StatusDatasig(10))
      OR (MainLogiccomp/MAINSTATE_FFd1 AND
      MainLogiccomp/MAINSTATE_FFd3 AND D(10)));

FDCPE_StatusDatasig11: FDCPE port map (StatusDatasig(11),StatusDatasig_D(11),clk,rst,'0');
     StatusDatasig_D(11) <= ((NOT MainLogiccomp/MAINSTATE_FFd1 AND StatusDatasig(11))
      OR (MainLogiccomp/MAINSTATE_FFd1 AND
      MainLogiccomp/MAINSTATE_FFd3 AND D(11)));

FDCPE_StatusDatasig12: FDCPE port map (StatusDatasig(12),StatusDatasig_D(12),clk,rst,'0');
     StatusDatasig_D(12) <= ((NOT MainLogiccomp/MAINSTATE_FFd1 AND StatusDatasig(12))
      OR (MainLogiccomp/MAINSTATE_FFd1 AND
      MainLogiccomp/MAINSTATE_FFd3 AND D(12)));

FDCPE_StatusDatasig13: FDCPE port map (StatusDatasig(13),StatusDatasig_D(13),clk,rst,'0');
     StatusDatasig_D(13) <= ((NOT MainLogiccomp/MAINSTATE_FFd1 AND StatusDatasig(13))
      OR (MainLogiccomp/MAINSTATE_FFd1 AND
      MainLogiccomp/MAINSTATE_FFd3 AND D(13)));

FDCPE_StatusDatasig14: FDCPE port map (StatusDatasig(14),StatusDatasig_D(14),clk,rst,'0');
     StatusDatasig_D(14) <= ((NOT MainLogiccomp/MAINSTATE_FFd1 AND StatusDatasig(14))
      OR (MainLogiccomp/MAINSTATE_FFd1 AND
      MainLogiccomp/MAINSTATE_FFd3 AND D(14)));

FDCPE_StatusDatasig15: FDCPE port map (StatusDatasig(15),StatusDatasig_D(15),clk,rst,'0');
     StatusDatasig_D(15) <= ((NOT MainLogiccomp/MAINSTATE_FFd1 AND StatusDatasig(15))
      OR (MainLogiccomp/MAINSTATE_FFd1 AND
      MainLogiccomp/MAINSTATE_FFd3 AND D(15)));

WCLK <= clk;

FDCPE_WENn: FDCPE port map (WENn,WENn_D,clk,'0',rst);
WENn_D <= (
OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd2 AND NOT OpticalLogiccomp/RxDataLogiccomp/GenDataDonesig);