cpldfit: version I.31 Xilinx Inc.
Fitter Report
Design Name: top Date: 2-20-2007, 4:06PM
Device Used: XC95288XL-6-TQ144
Fitting Status: Successful
************************* Mapped Resource Summary **************************
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
280/288 ( 97%) 489 /1440 ( 34%) 481/864 ( 56%) 241/288 ( 84%) 115/117 ( 98%)
** Function Block Resources **
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 30/54 34/90 0/ 8
FB2 18/18* 37/54 28/90 6/10
FB3 18/18* 36/54 41/90 1/ 5
FB4 18/18* 29/54 28/90 6/ 6*
FB5 18/18* 30/54 31/90 1/ 8
FB6 18/18* 32/54 32/90 7/ 8
FB7 18/18* 35/54 32/90 0/ 4
FB8 18/18* 26/54 33/90 3/ 5
FB9 18/18* 29/54 26/90 0/ 9
FB10 18/18* 28/54 26/90 9/10
FB11 18/18* 32/54 35/90 4/ 7
FB12 18/18* 32/54 32/90 3/ 6
FB13 18/18* 19/54 18/90 0/ 6
FB14 17/18 35/54 43/90 8/ 8*
FB15 16/18 16/54 16/90 0/ 9
FB16 13/18 35/54 34/90 8/ 8*
----- ----- ----- -----
280/288 481/864 489/1440 56/117
* - Resource is exhausted
** Global Control Resources **
Signal 'clk' mapped onto global clock net GCK1.
Global output enable net(s) unused.
Signal 'rst' mapped onto global set/reset net GSR.
** Pin Resources **
Signal Type Required Mapped | Pin Type Used Total
------------------------------------|------------------------------------
Input : 57 57 | I/O : 107 109
Output : 56 56 | GCK/IO : 3 3
Bidirectional : 0 0 | GTS/IO : 4 4
GCK : 1 1 | GSR/IO : 1 1
GTS : 0 0 |
GSR : 1 1 |
---- ----
Total 115 115
** Power Data **
There are 280 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
************************* Summary of Mapped Logic ************************
** 56 Outputs **
Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
Name Pts Inps No. Type Use Mode Rate State
FIFO_D<14> 1 2 FB2_2 9 I/O O STD FAST
FIFO_D<15> 1 2 FB2_3 10 I/O O STD FAST
RCLK 1 1 FB2_5 11 I/O O STD FAST
RENn 1 3 FB2_6 12 I/O O STD FAST SET
OEn 0 0 FB2_8 13 I/O O STD FAST
RSTn 0 0 FB2_10 14 I/O O STD FAST RESET
SPARE<12> 2 4 FB3_14 32 GCK/I/O O STD FAST RESET
FIFO_D<8> 1 2 FB4_2 2 GTS/I/O O STD FAST
FIFO_D<9> 1 2 FB4_5 3 GTS/I/O O STD FAST
FIFO_D<10> 1 2 FB4_6 4 I/O O STD FAST
FIFO_D<11> 1 2 FB4_8 5 GTS/I/O O STD FAST
FIFO_D<12> 1 2 FB4_12 6 GTS/I/O O STD FAST
FIFO_D<13> 1 2 FB4_14 7 I/O O STD FAST
SPARE<11> 2 4 FB5_8 38 GCK/I/O O STD FAST RESET
FIFO_D<1> 1 2 FB6_2 135 I/O O STD FAST
FIFO_D<2> 1 2 FB6_3 136 I/O O STD FAST
FIFO_D<3> 1 2 FB6_5 137 I/O O STD FAST
FIFO_D<4> 1 2 FB6_6 138 I/O O STD FAST
FIFO_D<5> 1 2 FB6_8 139 I/O O STD FAST
FIFO_D<6> 1 2 FB6_10 140 I/O O STD FAST
FIFO_D<7> 1 2 FB6_14 142 I/O O STD FAST
WENn 1 2 FB8_5 132 I/O O STD FAST SET
WCLK 1 1 FB8_8 133 I/O O STD FAST
FIFO_D<0> 1 2 FB8_10 134 I/O O STD FAST
STOPTRIG2 0 0 FB10_2 117 I/O O STD FAST
SPARE<7> 1 1 FB10_5 119 I/O O STD FAST RESET
SPARE<6> 1 1 FB10_6 120 I/O O STD FAST
SPARE<5> 1 1 FB10_8 121 I/O O STD FAST RESET
SPARE<4> 1 3 FB10_10 124 I/O O STD FAST RESET
SPARE<3> 1 1 FB10_11 125 I/O O STD FAST RESET
SPARE<2> 2 3 FB10_12 126 I/O O STD FAST RESET
SPARE<1> 2 3 FB10_14 128 I/O O STD FAST RESET
SPARE<0> 3 3 FB10_17 129 I/O O STD FAST RESET
CTRL 1 2 FB11_10 64 I/O O STD FAST
SPARE<10> 2 4 FB11_11 66 I/O O STD FAST RESET
SPARE<9> 2 4 FB11_12 68 I/O O STD FAST RESET
SPARE<8> 1 1 FB11_14 69 I/O O STD FAST
REQ2 1 1 FB12_3 111 I/O O STD FAST RESET
STOPTRIG1 0 0 FB12_5 112 I/O O STD FAST
REQ1 1 1 FB12_12 116 I/O O STD FAST RESET
Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
Name Pts Inps No. Type Use Mode Rate State
DIOD<7> 3 8 FB14_3 100 I/O O STD FAST RESET
DIOD<6> 3 8 FB14_5 101 I/O O STD FAST RESET
DIOD<5> 3 8 FB14_6 102 I/O O STD FAST RESET
DIOD<4> 3 8 FB14_8 103 I/O O STD FAST RESET
DIOD<3> 3 8 FB14_10 104 I/O O STD FAST RESET
DIOD<2> 3 8 FB14_11 105 I/O O STD FAST RESET
DIOD<1> 3 8 FB14_14 106 I/O O STD FAST RESET
DIOD<0> 3 8 FB14_15 107 I/O O STD FAST RESET
DIOC<7> 3 8 FB16_2 91 I/O O STD FAST RESET
DIOC<6> 3 8 FB16_3 92 I/O O STD FAST RESET
DIOC<5> 3 8 FB16_5 93 I/O O STD FAST RESET
DIOC<4> 3 8 FB16_6 94 I/O O STD FAST RESET
DIOC<3> 3 8 FB16_8 95 I/O O STD FAST RESET
DIOC<2> 3 8 FB16_10 96 I/O O STD FAST RESET
DIOC<1> 3 8 FB16_11 97 I/O O STD FAST RESET
DIOC<0> 3 8 FB16_12 98 I/O O STD FAST RESET
** 224 Buried Nodes **
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
OpticalLogiccomp/TransmitCommandcomp/cnt<0> 1 2 FB1_1 STD RESET
OpticalLogiccomp/GenSimDatasig 1 2 FB1_2 STD RESET
OpticalLogiccomp/command_insig<9> 2 4 FB1_3 STD RESET
OpticalLogiccomp/command_insig<8> 2 4 FB1_4 STD RESET
OpticalLogiccomp/command_insig<7> 2 4 FB1_5 STD RESET
OpticalLogiccomp/command_insig<5> 2 4 FB1_6 STD RESET
OpticalLogiccomp/command_insig<4> 2 4 FB1_7 STD RESET
OpticalLogiccomp/TransmitCommandcomp/sr<9> 2 3 FB1_8 STD RESET
OpticalLogiccomp/TransmitCommandcomp/sr<8> 2 3 FB1_9 STD RESET
OpticalLogiccomp/TransmitCommandcomp/sr<16> 2 3 FB1_10 STD RESET
OpticalLogiccomp/TransmitCommandcomp/sr<15> 2 3 FB1_11 STD RESET
OpticalLogiccomp/TransmitCommandcomp/sr<14> 2 3 FB1_12 STD RESET
OpticalLogiccomp/TransmitCommandcomp/sr<13> 2 3 FB1_13 STD RESET
OpticalLogiccomp/TransmitCommandcomp/sr<12> 2 3 FB1_14 STD RESET
OpticalLogiccomp/TransmitCommandcomp/sr<11> 2 3 FB1_15 STD RESET
OpticalLogiccomp/TransmitCommandcomp/sr<10> 2 3 FB1_16 STD RESET
OpticalLogiccomp/TransmitCommandcomp/cnt<3> 2 3 FB1_17 STD RESET
OpticalLogiccomp/TransmitCommandcomp/cnt<1> 2 3 FB1_18 STD RESET
OpticalLogiccomp/RxDataLogiccomp/EventReadyCmd 1 2 FB2_1 STD RESET
OpticalLogiccomp/RxDataLogiccomp/Busy 1 2 FB2_4 STD RESET
OPTCMD_Readysig 1 1 FB2_7 STD RESET
EventReadoutsig 1 3 FB2_9 STD RESET
OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd1 2 4 FB2_11 STD RESET
NIDAQLogiccomp/StatusDatasig<6> 2 2 FB2_12 STD RESET
NIDAQLogiccomp/StatusDatasig<3> 2 2 FB2_13 STD RESET
NIDAQLogiccomp/StatusDatasig<0> 2 2 FB2_14 STD RESET
StatusDatasig<6> 3 5 FB2_15 STD RESET
StatusDatasig<3> 3 5 FB2_16 STD RESET
StatusDatasig<0> 3 5 FB2_17 STD RESET
OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd2 3 22 FB2_18 STD RESET
StatusDatasig<8> 2 4 FB3_1 STD RESET
StatusDatasig<15> 2 4 FB3_2 STD RESET
StatusDatasig<14> 2 4 FB3_3 STD RESET
StatusDatasig<13> 2 4 FB3_4 STD RESET
StatusDatasig<12> 2 4 FB3_5 STD RESET
StatusDatasig<11> 2 4 FB3_6 STD RESET
StatusDatasig<10> 2 4 FB3_7 STD RESET
NIDAQLogiccomp/StatusDatasig<14> 2 2 FB3_8 STD RESET
NIDAQLogiccomp/StatusDatasig<13> 2 2 FB3_9 STD RESET
NIDAQLogiccomp/StatusDatasig<12> 2 2 FB3_10 STD RESET
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
NIDAQLogiccomp/StatusDatasig<11> 2 2 FB3_11 STD RESET
NIDAQLogiccomp/StatusDatasig<10> 2 2 FB3_12 STD RESET
StatusDatasig<7> 3 5 FB3_13 STD RESET
StatusDatasig<5> 3 5 FB3_15 STD RESET
StatusDatasig<4> 3 5 FB3_16 STD RESET
StatusDatasig<2> 3 5 FB3_17 STD RESET
StatusDatasig<1> 3 5 FB3_18 STD RESET
NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0003/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0003_D2 1 5 FB4_1 STD
NIDAQLogiccomp/Readtimeout 1 17 FB4_3 STD RESET
NIDAQLogiccomp/Readtimeoutcounter_0_9 2 6 FB4_4 STD RESET
NIDAQLogiccomp/Readtimeoutcounter_0_8 2 4 FB4_7 STD RESET
NIDAQLogiccomp/Readtimeoutcounter_0_6 2 5 FB4_9 STD RESET
NIDAQLogiccomp/Readtimeoutcounter_0_4 2 7 FB4_10 STD RESET
NIDAQLogiccomp/Readtimeoutcounter_0_3 2 5 FB4_11 STD RESET
NIDAQLogiccomp/Readtimeoutcounter_0_2 2 4 FB4_13 STD RESET
NIDAQLogiccomp/Readtimeoutcounter_0_14 2 6 FB4_15 STD RESET
NIDAQLogiccomp/Readtimeoutcounter_0_13 2 4 FB4_16 STD RESET
NIDAQLogiccomp/Readtimeoutcounter_0_11 2 5 FB4_17 STD RESET
NIDAQLogiccomp/Readtimeoutcounter_0_1 2 3 FB4_18 STD RESET
OpticalLogiccomp/TransmitCommandcomp/sending 1 5 FB5_1 STD RESET
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0011/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0011_D2 1 5 FB5_2 STD
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0007/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0007_D2 1 5 FB5_3 STD
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0003/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0003_D2 1 5 FB5_4 STD
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_0 1 2 FB5_5 STD RESET
OpticalLogiccomp/TransmitCommandcomp/cnt<4> 2 4 FB5_6 STD RESET
OpticalLogiccomp/TransmitCommandcomp/cnt<2> 2 4 FB5_7 STD RESET
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_9 2 3 FB5_9 STD RESET
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_7 2 5 FB5_10 STD RESET
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_6 2 4 FB5_11 STD RESET
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_5 2 3 FB5_12 STD RESET
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_3 2 5 FB5_13 STD RESET
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_2 2 4 FB5_14 STD RESET
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_14 2 4 FB5_15 STD RESET
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_13 2 3 FB5_16 STD RESET
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_10 2 4 FB5_17 STD RESET
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_1 2 3 FB5_18 STD RESET
SendDataCmdsig 1 1 FB6_1 STD RESET
OPTCMDsig<4> 2 4 FB6_4 STD RESET
OPTCMDsig<3> 2 4 FB6_7 STD RESET
OPTCMDsig<2> 2 4 FB6_9 STD RESET
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
OPTCMDsig<1> 2 4 FB6_11 STD RESET
OPTCMDsig<0> 2 4 FB6_12 STD RESET
MainLogiccomp/MAINSTATE_FFd2 2 11 FB6_13 STD RESET
MainLogiccomp/MAINSTATE_FFd1 2 12 FB6_15 STD RESET
OpticalLogiccomp/OPTICALLOGICSTATE_FFd2 3 12 FB6_16 STD RESET
OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 3 12 FB6_17 STD RESET
MainLogiccomp/MAINSTATE_FFd3 4 12 FB6_18 STD RESET
OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<9> 1 1 FB7_1 STD RESET
NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0013/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0013_D2 1 4 FB7_2 STD
NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0008/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0008_D2 1 4 FB7_3 STD
NIDAQLogiccomp/Readtimeoutcounter_0_0 1 2 FB7_4 STD RESET
StatusDatasig<9> 2 4 FB7_5 STD RESET
OpticalLogiccomp/TransmitCommandcomp/sr<7> 2 3 FB7_6 STD RESET
OpticalLogiccomp/TransmitCommandcomp/sr<6> 2 3 FB7_7 STD RESET
OpticalLogiccomp/TransmitCommandcomp/sr<5> 2 3 FB7_8 STD RESET
OpticalLogiccomp/TransmitCommandcomp/sr<4> 2 3 FB7_9 STD RESET
OpticalLogiccomp/TransmitCommandcomp/sr<19> 2 2 FB7_10 STD RESET
OpticalLogiccomp/TransmitCommandcomp/sr<18> 2 3 FB7_11 STD RESET
OpticalLogiccomp/TransmitCommandcomp/sr<17> 2 3 FB7_12 STD RESET
NIDAQLogiccomp/StatusDatasig<9> 2 2 FB7_13 STD RESET
NIDAQLogiccomp/Readtimeoutcounter_0_7 2 3 FB7_14 STD RESET
NIDAQLogiccomp/Readtimeoutcounter_0_5 2 3 FB7_15 STD RESET
NIDAQLogiccomp/Readtimeoutcounter_0_15 2 3 FB7_16 STD RESET
NIDAQLogiccomp/Readtimeoutcounter_0_12 2 3 FB7_17 STD RESET
NIDAQLogiccomp/Readtimeoutcounter_0_10 2 3 FB7_18 STD RESET
NIDAQLogiccomp/NI_Interfacecomp/req2_cnt<0> 1 2 FB8_1 STD RESET
NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd1 1 3 FB8_2 STD RESET
NIDAQLogiccomp/Msub__addsub0000__or0001/NIDAQLogiccomp/Msub__addsub0000__or0001_D2 1 3 FB8_3 STD
NIDAQLogiccomp/NumOfWordsSentCounter<7> 2 6 FB8_4 STD RESET
NIDAQLogiccomp/NumOfWordsSentCounter<6> 2 5 FB8_6 STD RESET
NIDAQLogiccomp/NumOfWordsSentCounter<5> 2 4 FB8_7 STD RESET
NIDAQLogiccomp/NumOfWordsSentCounter<4> 2 5 FB8_9 STD RESET
NIDAQLogiccomp/NumOfWordsSentCounter<3> 2 4 FB8_11 STD RESET
NIDAQLogiccomp/NumOfWordsSentCounter<2> 2 5 FB8_12 STD RESET
NIDAQLogiccomp/NumOfWordsSentCounter<1> 2 4 FB8_13 STD RESET
NIDAQLogiccomp/NumOfWordsSentCounter<0> 2 3 FB8_14 STD RESET
NIDAQLogiccomp/NI_Interfacecomp/req2_cnt<1> 2 3 FB8_15 STD RESET
NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd2 2 3 FB8_16 STD RESET
NIDAQLogiccomp/SendingPackageFlag 3 11 FB8_17 STD RESET
NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd3 4 7 FB8_18 STD RESET
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
OpticalLogiccomp/TransmitCommandcomp/sr<3> 1 2 FB9_1 STD RESET
OpticalLogiccomp/TransmitCommandcomp/sr<2> 1 2 FB9_2 STD RESET
OpticalLogiccomp/TransmitCommandcomp/sr<1> 1 2 FB9_3 STD RESET
OpticalLogiccomp/TransmitCommandcomp/sr<0> 1 2 FB9_4 STD RESET
OpticalLogiccomp/TransmitCommandcomp/cnt_Msub__sub0000__or0001/OpticalLogiccomp/TransmitCommandcomp/cnt_Msub__sub0000__or0001_D2 1 3 FB9_5 STD
NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0010/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0010_D2 1 3 FB9_6 STD
NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0005/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0005_D2 1 3 FB9_7 STD
NIDAQLogiccomp/NI_Interfacecomp/ack2_sync 1 1 FB9_8 STD RESET
NIDAQLogiccomp/NI_Interfacecomp/ack1_sync<1> 1 1 FB9_9 STD RESET
NIDAQLogiccomp/Msub__addsub0000__or0003/NIDAQLogiccomp/Msub__addsub0000__or0003_D2 1 3 FB9_10 STD
NIDAQLogiccomp/StatusDatasig<8> 2 2 FB9_11 STD RESET
NIDAQLogiccomp/StatusDatasig<7> 2 2 FB9_12 STD RESET
NIDAQLogiccomp/StatusDatasig<5> 2 2 FB9_13 STD RESET
NIDAQLogiccomp/StatusDatasig<4> 2 2 FB9_14 STD RESET
NIDAQLogiccomp/StatusDatasig<2> 2 2 FB9_15 STD RESET
NIDAQLogiccomp/StatusDatasig<1> 2 2 FB9_16 STD RESET
NIDAQLogiccomp/StatusDatasig<15> 2 2 FB9_17 STD RESET
EventReadysig 2 2 FB9_18 STD RESET
OpticalLogiccomp/RxDataLogiccomp/GenDataDonesig 1 16 FB10_1 STD RESET
NIDAQLogiccomp/cav 1 2 FB10_3 STD RESET
NIDAQLogiccomp/NI_Interfacecomp/ack1_sync<2> 1 1 FB10_4 STD RESET
NIDAQLogiccomp/NI_Interfacecomp/ack1_sync<0> 1 1 FB10_7 STD RESET
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_8 2 7 FB10_9 STD RESET
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_4 2 7 FB10_13 STD RESET
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_15 2 5 FB10_15 STD RESET
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_12 2 7 FB10_16 STD RESET
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_11 2 5 FB10_18 STD RESET
OpticalLogiccomp/command_insig<6> 2 4 FB11_1 STD RESET
OpticalLogiccomp/command_insig<14> 2 4 FB11_2 STD RESET
OpticalLogiccomp/command_insig<13> 2 4 FB11_3 STD RESET
OpticalLogiccomp/command_insig<12> 2 4 FB11_4 STD RESET
OpticalLogiccomp/command_insig<11> 2 4 FB11_5 STD RESET
OpticalLogiccomp/command_insig<10> 2 4 FB11_6 STD RESET
NICMDsig<3> 2 4 FB11_7 STD RESET
NICMDsig<2> 2 4 FB11_8 STD RESET
NICMDsig<1> 2 4 FB11_9 STD RESET
NICMDsig<0> 2 4 FB11_13 STD RESET
NICMD_Argsig<7> 2 4 FB11_15 STD RESET
NICMD_Argsig<6> 2 4 FB11_16 STD RESET
NICMD_Argsig<5> 2 4 FB11_17 STD RESET
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
OpticalLogiccomp/command_insig<0> 3 5 FB11_18 STD RESET
OpticalLogiccomp/command_insig<3> 2 4 FB12_1 STD RESET
OpticalLogiccomp/command_insig<2> 2 4 FB12_2 STD RESET
OpticalLogiccomp/command_insig<1> 2 4 FB12_4 STD RESET
OpticalLogiccomp/command_insig<15> 2 4 FB12_6 STD RESET
OPTCMDsig<7> 2 4 FB12_7 STD RESET
OPTCMDsig<6> 2 4 FB12_8 STD RESET
OPTCMDsig<5> 2 4 FB12_9 STD RESET
OPTCMD_Argsig<7> 2 4 FB12_10 STD RESET
OPTCMD_Argsig<6> 2 4 FB12_11 STD RESET
OPTCMD_Argsig<5> 2 4 FB12_13 STD RESET
OPTCMD_Argsig<4> 2 4 FB12_14 STD RESET
OPTCMD_Argsig<3> 2 4 FB12_15 STD RESET
OPTCMD_Argsig<2> 2 4 FB12_16 STD RESET
OPTCMD_Argsig<1> 2 4 FB12_17 STD RESET
OPTCMD_Argsig<0> 2 4 FB12_18 STD RESET
NIDAQLogiccomp/command_out<9> 1 1 FB13_1 STD RESET
NIDAQLogiccomp/command_out<8> 1 1 FB13_2 STD RESET
NIDAQLogiccomp/command_out<7> 1 1 FB13_3 STD RESET
NIDAQLogiccomp/command_out<6> 1 1 FB13_4 STD RESET
NIDAQLogiccomp/command_out<5> 1 1 FB13_5 STD RESET
NIDAQLogiccomp/command_out<4> 1 1 FB13_6 STD RESET
NIDAQLogiccomp/command_out<3> 1 1 FB13_7 STD RESET
NIDAQLogiccomp/command_out<2> 1 1 FB13_8 STD RESET
NIDAQLogiccomp/command_out<1> 1 1 FB13_9 STD RESET
NIDAQLogiccomp/command_out<15> 1 1 FB13_10 STD RESET
NIDAQLogiccomp/command_out<14> 1 1 FB13_11 STD RESET
NIDAQLogiccomp/command_out<13> 1 1 FB13_12 STD RESET
NIDAQLogiccomp/command_out<12> 1 1 FB13_13 STD RESET
NIDAQLogiccomp/command_out<11> 1 1 FB13_14 STD RESET
NIDAQLogiccomp/command_out<10> 1 1 FB13_15 STD RESET
NIDAQLogiccomp/command_out<0> 1 1 FB13_16 STD RESET
NIDAQLogiccomp/NI_Interfacecomp/req2_cnt_ld 1 1 FB13_17 STD SET
EventReadysig/EventReadysig_RSTF 1 2 FB13_18 STD
NIDAQLogiccomp/wen 1 1 FB14_2 STD RESET
NIDAQLogiccomp/Readtimeouten 1 2 FB14_4 STD RESET
NICMD_Readysig 1 3 FB14_7 STD RESET
$OpTx$FX_SC$69 1 2 FB14_9 STD
NIDAQLogiccomp/N8/NIDAQLogiccomp/N8_D2 2 3 FB14_12 STD
BUF_NIDAQLogiccomp/wen 2 3 FB14_13 STD
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
NIDAQLogiccomp/NIDAQSTATE_FFd2 3 6 FB14_16 STD RESET
NIDAQLogiccomp/NIDAQSTATE_FFd3 4 7 FB14_17 STD RESET
NIDAQLogiccomp/NIDAQSTATE_FFd1 4 9 FB14_18 STD RESET
OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<8> 1 1 FB15_3 STD RESET
OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<7> 1 1 FB15_4 STD RESET
OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<6> 1 1 FB15_5 STD RESET
OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<5> 1 1 FB15_6 STD RESET
OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<4> 1 1 FB15_7 STD RESET
OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<3> 1 1 FB15_8 STD RESET
OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<2> 1 1 FB15_9 STD RESET
OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<1> 1 1 FB15_10 STD RESET
OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<15> 1 1 FB15_11 STD RESET
OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<14> 1 1 FB15_12 STD RESET
OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<13> 1 1 FB15_13 STD RESET
OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<12> 1 1 FB15_14 STD RESET
OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<11> 1 1 FB15_15 STD RESET
OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<10> 1 1 FB15_16 STD RESET
OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<0> 1 1 FB15_17 STD RESET
NIDAQLogiccomp/wdone 1 1 FB15_18 STD RESET
NICMD_Argsig<4> 2 4 FB16_14 STD RESET
NICMD_Argsig<3> 2 4 FB16_15 STD RESET
NICMD_Argsig<2> 2 4 FB16_16 STD RESET
NICMD_Argsig<1> 2 4 FB16_17 STD RESET
NICMD_Argsig<0> 2 4 FB16_18 STD RESET
** 59 Inputs **
Signal Loc Pin Pin Pin
Name No. Type Use
FIFO_Q<12> FB1_5 20 I/O I
FIFO_Q<11> FB1_6 21 I/O I
FIFO_Q<10> FB1_8 22 I/O I
FIFO_Q<9> FB1_10 23 I/O I
FIFO_Q<8> FB1_12 24 I/O I
FIFO_Q<7> FB1_14 25 I/O I
FIFO_Q<6> FB1_15 26 I/O I
FIFO_Q<5> FB1_17 27 I/O I
EFn FB2_12 15 I/O I
FIFO_Q<15> FB2_14 16 I/O I
FIFO_Q<14> FB2_15 17 I/O I
FIFO_Q<13> FB2_17 19 I/O I
FIFO_Q<4> FB3_2 28 I/O I
clk FB3_10 30 GCK/I/O GCK/I
FIFO_Q<3> FB3_12 31 I/O I
FIFO_Q<2> FB3_15 33 I/O I
FIFO_Q<1> FB5_2 34 I/O I
FIFO_Q<0> FB5_5 35 I/O I
D<15> FB5_10 39 I/O I
D<14> FB5_12 40 I/O I
D<13> FB5_14 41 I/O I
D<12> FB5_15 43 I/O I
D<11> FB5_17 44 I/O I
rst FB6_15 143 GSR/I/O GSR/I
D<10> FB7_3 45 I/O I
D<9> FB7_5 46 I/O I
D<8> FB7_12 48 I/O I
D<7> FB7_15 49 I/O I
HFn FB8_2 130 I/O I
FFn FB8_3 131 I/O I
D<6> FB9_2 50 I/O I
D<5> FB9_3 51 I/O I
D<4> FB9_5 52 I/O I
D<3> FB9_6 53 I/O I
D<2> FB9_8 54 I/O I
D<1> FB9_11 56 I/O I
D<0> FB9_12 57 I/O I
DATAOK FB9_14 58 I/O I
RXREADY FB9_17 59 I/O I
RXDATA FB11_3 60 I/O I
Signal Loc Pin Pin Pin
Name No. Type Use
RXERROR FB11_5 61 I/O I
DIOA<7> FB11_17 70 I/O I
ACK2 FB12_2 110 I/O I
ACK1 FB12_10 115 I/O I
DIOA<6> FB13_2 71 I/O I
DIOA<5> FB13_8 74 I/O I
DIOA<4> FB13_11 75 I/O I
DIOA<3> FB13_14 76 I/O I
DIOA<2> FB13_15 77 I/O I
DIOA<1> FB13_17 78 I/O I
DIOA<0> FB15_2 79 I/O I
DIOB<7> FB15_3 80 I/O I
DIOB<6> FB15_8 81 I/O I
DIOB<5> FB15_10 82 I/O I
DIOB<4> FB15_11 83 I/O I
DIOB<3> FB15_12 85 I/O I
DIOB<2> FB15_14 86 I/O I
DIOB<1> FB15_15 87 I/O I
DIOB<0> FB15_17 88 I/O I
Legend:
Pin No. - ~ - User Assigned
************************** Function Block Details ************************
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X - Signal used as input to the macrocell logic.
Pin No. - ~ - User Assigned
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 30/24
Number of signals used by logic mapping into function block: 30
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
OpticalLogiccomp/TransmitCommandcomp/cnt<0>
1 0 0 4 FB1_1 (b) (b)
OpticalLogiccomp/GenSimDatasig
1 0 0 4 FB1_2 (b) (b)
OpticalLogiccomp/command_insig<9>
2 0 0 3 FB1_3 (b) (b)
OpticalLogiccomp/command_insig<8>
2 0 0 3 FB1_4 (b) (b)
OpticalLogiccomp/command_insig<7>
2 0 0 3 FB1_5 20 I/O I
OpticalLogiccomp/command_insig<5>
2 0 0 3 FB1_6 21 I/O I
OpticalLogiccomp/command_insig<4>
2 0 0 3 FB1_7 (b) (b)
OpticalLogiccomp/TransmitCommandcomp/sr<9>
2 0 0 3 FB1_8 22 I/O I
OpticalLogiccomp/TransmitCommandcomp/sr<8>
2 0 0 3 FB1_9 (b) (b)
OpticalLogiccomp/TransmitCommandcomp/sr<16>
2 0 0 3 FB1_10 23 I/O I
OpticalLogiccomp/TransmitCommandcomp/sr<15>
2 0 0 3 FB1_11 (b) (b)
OpticalLogiccomp/TransmitCommandcomp/sr<14>
2 0 0 3 FB1_12 24 I/O I
OpticalLogiccomp/TransmitCommandcomp/sr<13>
2 0 0 3 FB1_13 (b) (b)
OpticalLogiccomp/TransmitCommandcomp/sr<12>
2 0 0 3 FB1_14 25 I/O I
OpticalLogiccomp/TransmitCommandcomp/sr<11>
2 0 0 3 FB1_15 26 I/O I
OpticalLogiccomp/TransmitCommandcomp/sr<10>
2 0 0 3 FB1_16 (b) (b)
OpticalLogiccomp/TransmitCommandcomp/cnt<3>
2 0 0 3 FB1_17 27 I/O I
OpticalLogiccomp/TransmitCommandcomp/cnt<1>
2 0 0 3 FB1_18 (b) (b)
Signals Used by Logic in Function Block
1: OPTCMD_Argsig<4> 11: OpticalLogiccomp/TransmitCommandcomp/cnt_Msub__sub0000__or0001/OpticalLogiccomp/TransmitCommandcomp/cnt_Msub__sub0000__or0001_D2 21: OpticalLogiccomp/TransmitCommandcomp/sr<9>
2: OPTCMD_Argsig<5> 12: OpticalLogiccomp/TransmitCommandcomp/sending 22: OpticalLogiccomp/command_insig<10>
3: OPTCMD_Argsig<7> 13: OpticalLogiccomp/TransmitCommandcomp/sr<10> 23: OpticalLogiccomp/command_insig<11>
4: OPTCMDsig<0> 14: OpticalLogiccomp/TransmitCommandcomp/sr<11> 24: OpticalLogiccomp/command_insig<12>
5: OPTCMDsig<1> 15: OpticalLogiccomp/TransmitCommandcomp/sr<12> 25: OpticalLogiccomp/command_insig<4>
6: OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 16: OpticalLogiccomp/TransmitCommandcomp/sr<13> 26: OpticalLogiccomp/command_insig<5>
7: OpticalLogiccomp/OPTICALLOGICSTATE_FFd2 17: OpticalLogiccomp/TransmitCommandcomp/sr<14> 27: OpticalLogiccomp/command_insig<6>
8: OpticalLogiccomp/TransmitCommandcomp/cnt<0> 18: OpticalLogiccomp/TransmitCommandcomp/sr<15> 28: OpticalLogiccomp/command_insig<7>
9: OpticalLogiccomp/TransmitCommandcomp/cnt<1> 19: OpticalLogiccomp/TransmitCommandcomp/sr<16> 29: OpticalLogiccomp/command_insig<8>
10: OpticalLogiccomp/TransmitCommandcomp/cnt<3> 20: OpticalLogiccomp/TransmitCommandcomp/sr<17> 30: OpticalLogiccomp/command_insig<9>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
OpticalLogiccomp/TransmitCommandcomp/cnt<0>
.......X...X............................ 2
OpticalLogiccomp/GenSimDatasig
.....XX................................. 2
OpticalLogiccomp/command_insig<9>
....XXX......................X.......... 4
OpticalLogiccomp/command_insig<8>
...X.XX.....................X........... 4
OpticalLogiccomp/command_insig<7>
..X..XX....................X............ 4
OpticalLogiccomp/command_insig<5>
.X...XX..................X.............. 4
OpticalLogiccomp/command_insig<4>
X....XX.................X............... 4
OpticalLogiccomp/TransmitCommandcomp/sr<9>
...........XX............X.............. 3
OpticalLogiccomp/TransmitCommandcomp/sr<8>
...........X........X...X............... 3
OpticalLogiccomp/TransmitCommandcomp/sr<16>
...........X.......X...X................ 3
OpticalLogiccomp/TransmitCommandcomp/sr<15>
...........X......X...X................. 3
OpticalLogiccomp/TransmitCommandcomp/sr<14>
...........X.....X...X.................. 3
OpticalLogiccomp/TransmitCommandcomp/sr<13>
...........X....X............X.......... 3
OpticalLogiccomp/TransmitCommandcomp/sr<12>
...........X...X............X........... 3
OpticalLogiccomp/TransmitCommandcomp/sr<11>
...........X..X............X............ 3
OpticalLogiccomp/TransmitCommandcomp/sr<10>
...........X.X............X............. 3
OpticalLogiccomp/TransmitCommandcomp/cnt<3>
.........XXX............................ 3
OpticalLogiccomp/TransmitCommandcomp/cnt<1>
.......XX..X............................ 3
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 37/17
Number of signals used by logic mapping into function block: 37
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
OpticalLogiccomp/RxDataLogiccomp/EventReadyCmd
1 0 0 4 FB2_1 (b) (b)
FIFO_D<14> 1 0 0 4 FB2_2 9 I/O O
FIFO_D<15> 1 0 0 4 FB2_3 10 I/O O
OpticalLogiccomp/RxDataLogiccomp/Busy
1 0 0 4 FB2_4 (b) (b)
RCLK 1 0 0 4 FB2_5 11 I/O O
RENn 1 0 0 4 FB2_6 12 I/O O
OPTCMD_Readysig 1 0 0 4 FB2_7 (b) (b)
OEn 0 0 0 5 FB2_8 13 I/O O
EventReadoutsig 1 0 0 4 FB2_9 (b) (b)
RSTn 0 0 0 5 FB2_10 14 I/O O
OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd1
2 0 0 3 FB2_11 (b) (b)
NIDAQLogiccomp/StatusDatasig<6>
2 0 0 3 FB2_12 15 I/O I
NIDAQLogiccomp/StatusDatasig<3>
2 0 0 3 FB2_13 (b) (b)
NIDAQLogiccomp/StatusDatasig<0>
2 0 0 3 FB2_14 16 I/O I
StatusDatasig<6> 3 0 0 2 FB2_15 17 I/O I
StatusDatasig<3> 3 0 0 2 FB2_16 (b) (b)
StatusDatasig<0> 3 0 0 2 FB2_17 19 I/O I
OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd2
3 0 0 2 FB2_18 (b) (b)
Signals Used by Logic in Function Block
1: DATAOK 14: OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<10> 26: OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<7>
2: D<0> 15: OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<11> 27: OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<8>
3: D<3> 16: OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<12> 28: OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<9>
4: D<6> 17: OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<13> 29: OpticalLogiccomp/RxDataLogiccomp/GenDataDonesig
5: EFn 18: OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<14> 30: OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd1
6: MainLogiccomp/MAINSTATE_FFd1 19: OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<15> 31: OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd2
7: MainLogiccomp/MAINSTATE_FFd2 20: OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<1> 32: clk
8: MainLogiccomp/MAINSTATE_FFd3 21: OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<2> 33: RXERROR
9: NIDAQLogiccomp/NIDAQSTATE_FFd1 22: OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<3> 34: StatusDatasig<0>
10: NIDAQLogiccomp/NIDAQSTATE_FFd2 23: OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<4> 35: StatusDatasig<3>
11: NIDAQLogiccomp/NIDAQSTATE_FFd3 24: OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<5> 36: StatusDatasig<6>
12: OpticalLogiccomp/GenSimDatasig 25: OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<6> 37: rst
13: OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<0>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
OpticalLogiccomp/RxDataLogiccomp/EventReadyCmd
............................X.X......... 2
FIFO_D<14> .................X...........X.......... 2
FIFO_D<15> ..................X..........X.......... 2
OpticalLogiccomp/RxDataLogiccomp/Busy
.............................XX......... 2
RCLK ...............................X........ 1
RENn ........XXX............................. 3
OPTCMD_Readysig ......X................................. 1
OEn ........................................ 0
EventReadoutsig .....XXX................................ 3
RSTn ........................................ 0
OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd1
...........X................XXX......... 4
NIDAQLogiccomp/StatusDatasig<6>
...................................XX... 2
NIDAQLogiccomp/StatusDatasig<3>
..................................X.X... 2
NIDAQLogiccomp/StatusDatasig<0>
.................................X..X... 2
StatusDatasig<6> ...X.X.X........................X..X.... 5
StatusDatasig<3> X.X..X.X..........................X..... 5
StatusDatasig<0> .X..XX.X.........................X...... 5
OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd2
X..........XXXXXXXXXXXXXXXXXXXX.X....... 22
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 36/18
Number of signals used by logic mapping into function block: 36
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
StatusDatasig<8> 2 0 0 3 FB3_1 (b) (b)
StatusDatasig<15> 2 0 0 3 FB3_2 28 I/O I
StatusDatasig<14> 2 0 0 3 FB3_3 (b) (b)
StatusDatasig<13> 2 0 0 3 FB3_4 (b) (b)
StatusDatasig<12> 2 0 0 3 FB3_5 (b) (b)
StatusDatasig<11> 2 0 0 3 FB3_6 (b) (b)
StatusDatasig<10> 2 0 0 3 FB3_7 (b) (b)
NIDAQLogiccomp/StatusDatasig<14>
2 0 0 3 FB3_8 (b) (b)
NIDAQLogiccomp/StatusDatasig<13>
2 0 0 3 FB3_9 (b) (b)
NIDAQLogiccomp/StatusDatasig<12>
2 0 0 3 FB3_10 30 GCK/I/O GCK/I
NIDAQLogiccomp/StatusDatasig<11>
2 0 0 3 FB3_11 (b) (b)
NIDAQLogiccomp/StatusDatasig<10>
2 0 0 3 FB3_12 31 I/O I
StatusDatasig<7> 3 0 0 2 FB3_13 (b) (b)
SPARE<12> 2 0 0 3 FB3_14 32 GCK/I/O O
StatusDatasig<5> 3 0 0 2 FB3_15 33 I/O I
StatusDatasig<4> 3 0 0 2 FB3_16 (b) (b)
StatusDatasig<2> 3 0 0 2 FB3_17 (b) (b)
StatusDatasig<1> 3 0 0 2 FB3_18 (b) (b)
Signals Used by Logic in Function Block
1: D<10> 13: EventReadysig 25: StatusDatasig<11>
2: D<11> 14: FFn 26: StatusDatasig<12>
3: D<12> 15: HFn 27: StatusDatasig<13>
4: D<13> 16: MainLogiccomp/MAINSTATE_FFd1 28: StatusDatasig<14>
5: D<14> 17: MainLogiccomp/MAINSTATE_FFd3 29: StatusDatasig<15>
6: D<15> 18: NIDAQLogiccomp/NIDAQSTATE_FFd1 30: StatusDatasig<1>
7: D<1> 19: NIDAQLogiccomp/NIDAQSTATE_FFd2 31: StatusDatasig<2>
8: D<2> 20: NIDAQLogiccomp/NIDAQSTATE_FFd3 32: StatusDatasig<4>
9: D<4> 21: NIDAQLogiccomp/command_out<15> 33: StatusDatasig<5>
10: D<5> 22: RXDATA 34: StatusDatasig<7>
11: D<7> 23: RXREADY 35: StatusDatasig<8>
12: D<8> 24: StatusDatasig<10> 36: rst
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
StatusDatasig<8> ...........X...XX.................X..... 4
StatusDatasig<15> .....X.........XX...........X........... 4
StatusDatasig<14> ....X..........XX..........X............ 4
StatusDatasig<13> ...X...........XX.........X............. 4
StatusDatasig<12> ..X............XX........X.............. 4
StatusDatasig<11> .X.............XX.......X............... 4
StatusDatasig<10> X..............XX......X................ 4
NIDAQLogiccomp/StatusDatasig<14>
...........................X.......X.... 2
NIDAQLogiccomp/StatusDatasig<13>
..........................X........X.... 2
NIDAQLogiccomp/StatusDatasig<12>
.........................X.........X.... 2
NIDAQLogiccomp/StatusDatasig<11>
........................X..........X.... 2
NIDAQLogiccomp/StatusDatasig<10>
.......................X...........X.... 2
StatusDatasig<7> ..........X.X..XX................X...... 5
SPARE<12> .................XXXX................... 4
StatusDatasig<5> .........X.....XX....X..........X....... 5
StatusDatasig<4> ........X......XX.....X........X........ 5
StatusDatasig<2> .......X......XXX.............X......... 5
StatusDatasig<1> ......X......X.XX............X.......... 5
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 29/25
Number of signals used by logic mapping into function block: 29
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0003/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0003_D2
1 0 0 4 FB4_1 (b) (b)
FIFO_D<8> 1 0 0 4 FB4_2 2 GTS/I/O O
NIDAQLogiccomp/Readtimeout
1 0 0 4 FB4_3 (b) (b)
NIDAQLogiccomp/Readtimeoutcounter_0_9
2 0 0 3 FB4_4 (b) (b)
FIFO_D<9> 1 0 0 4 FB4_5 3 GTS/I/O O
FIFO_D<10> 1 0 0 4 FB4_6 4 I/O O
NIDAQLogiccomp/Readtimeoutcounter_0_8
2 0 0 3 FB4_7 (b) (b)
FIFO_D<11> 1 0 0 4 FB4_8 5 GTS/I/O O
NIDAQLogiccomp/Readtimeoutcounter_0_6
2 0 0 3 FB4_9 (b) (b)
NIDAQLogiccomp/Readtimeoutcounter_0_4
2 0 0 3 FB4_10 (b) (b)
NIDAQLogiccomp/Readtimeoutcounter_0_3
2 0 0 3 FB4_11 (b) (b)
FIFO_D<12> 1 0 0 4 FB4_12 6 GTS/I/O O
NIDAQLogiccomp/Readtimeoutcounter_0_2
2 0 0 3 FB4_13 (b) (b)
FIFO_D<13> 1 0 0 4 FB4_14 7 I/O O
NIDAQLogiccomp/Readtimeoutcounter_0_14
2 0 0 3 FB4_15 (b) (b)
NIDAQLogiccomp/Readtimeoutcounter_0_13
2 0 0 3 FB4_16 (b) (b)
NIDAQLogiccomp/Readtimeoutcounter_0_11
2 0 0 3 FB4_17 (b) (b)
NIDAQLogiccomp/Readtimeoutcounter_0_1
2 0 0 3 FB4_18 (b) (b)
Signals Used by Logic in Function Block
1: NIDAQLogiccomp/Readtimeoutcounter_0_0 11: NIDAQLogiccomp/Readtimeoutcounter_0_4 21: NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0013/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0013_D2
2: NIDAQLogiccomp/Readtimeoutcounter_0_1 12: NIDAQLogiccomp/Readtimeoutcounter_0_5 22: NIDAQLogiccomp/Readtimeouten
3: NIDAQLogiccomp/Readtimeoutcounter_0_10 13: NIDAQLogiccomp/Readtimeoutcounter_0_6 23: OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<10>
4: NIDAQLogiccomp/Readtimeoutcounter_0_11 14: NIDAQLogiccomp/Readtimeoutcounter_0_7 24: OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<11>
5: NIDAQLogiccomp/Readtimeoutcounter_0_12 15: NIDAQLogiccomp/Readtimeoutcounter_0_8 25: OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<12>
6: NIDAQLogiccomp/Readtimeoutcounter_0_13 16: NIDAQLogiccomp/Readtimeoutcounter_0_9 26: OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<13>
7: NIDAQLogiccomp/Readtimeoutcounter_0_14 17: NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0003/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0003_D2 27: OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<8>
8: NIDAQLogiccomp/Readtimeoutcounter_0_15 18: NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0005/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0005_D2 28: OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<9>
9: NIDAQLogiccomp/Readtimeoutcounter_0_2 19: NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0008/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0008_D2 29: OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd1
10: NIDAQLogiccomp/Readtimeoutcounter_0_3 20: NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0010/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0010_D2
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0003/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0003_D2
XX......XXX............................. 5
FIFO_D<8> ..........................X.X........... 2
NIDAQLogiccomp/Readtimeout
XXXXXXXXXXXXXXXX.....X.................. 17
NIDAQLogiccomp/Readtimeoutcounter_0_9
.............XXX.XX..X.................. 6
FIFO_D<9> ...........................XX........... 2
FIFO_D<10> ......................X.....X........... 2
NIDAQLogiccomp/Readtimeoutcounter_0_8
.............XX..X...X.................. 4
FIFO_D<11> .......................X....X........... 2
NIDAQLogiccomp/Readtimeoutcounter_0_6
...........XX...XX...X.................. 5
NIDAQLogiccomp/Readtimeoutcounter_0_4
XX......XXX.....X....X.................. 7
NIDAQLogiccomp/Readtimeoutcounter_0_3
XX......XX...........X.................. 5
FIFO_D<12> ........................X...X........... 2
NIDAQLogiccomp/Readtimeoutcounter_0_2
XX......X............X.................. 4
FIFO_D<13> .........................X..X........... 2
NIDAQLogiccomp/Readtimeoutcounter_0_14
....XXX............XXX.................. 6
NIDAQLogiccomp/Readtimeoutcounter_0_13
....XX.............X.X.................. 4
NIDAQLogiccomp/Readtimeoutcounter_0_11
..XX..............XX.X.................. 5
NIDAQLogiccomp/Readtimeoutcounter_0_1
XX...................X.................. 3
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB5 ***********************************
Number of function block inputs used/remaining: 30/24
Number of signals used by logic mapping into function block: 30
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
OpticalLogiccomp/TransmitCommandcomp/sending
1 0 0 4 FB5_1 (b) (b)
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0011/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0011_D2
1 0 0 4 FB5_2 34 I/O I
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0007/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0007_D2
1 0 0 4 FB5_3 (b) (b)
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0003/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0003_D2
1 0 0 4 FB5_4 (b) (b)
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_0
1 0 0 4 FB5_5 35 I/O I
OpticalLogiccomp/TransmitCommandcomp/cnt<4>
2 0 0 3 FB5_6 (b) (b)
OpticalLogiccomp/TransmitCommandcomp/cnt<2>
2 0 0 3 FB5_7 (b) (b)
SPARE<11> 2 0 0 3 FB5_8 38 GCK/I/O O
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_9
2 0 0 3 FB5_9 (b) (b)
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_7
2 0 0 3 FB5_10 39 I/O I
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_6
2 0 0 3 FB5_11 (b) (b)
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_5
2 0 0 3 FB5_12 40 I/O I
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_3
2 0 0 3 FB5_13 (b) (b)
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_2
2 0 0 3 FB5_14 41 I/O I
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_14
2 0 0 3 FB5_15 43 I/O I
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_13
2 0 0 3 FB5_16 (b) (b)
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_10
2 0 0 3 FB5_17 44 I/O I
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_1
2 0 0 3 FB5_18 (b) (b)
Signals Used by Logic in Function Block
1: NIDAQLogiccomp/NIDAQSTATE_FFd1 11: OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_13 21: OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0003/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0003_D2
2: NIDAQLogiccomp/NIDAQSTATE_FFd2 12: OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_14 22: OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0007/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0007_D2
3: NIDAQLogiccomp/NIDAQSTATE_FFd3 13: OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_2 23: OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0011/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0011_D2
4: NIDAQLogiccomp/command_out<14> 14: OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_3 24: OpticalLogiccomp/TransmitCommandcomp/cnt<0>
5: OpticalLogiccomp/RxDataLogiccomp/Busy 15: OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_4 25: OpticalLogiccomp/TransmitCommandcomp/cnt<1>
6: OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_0 16: OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_5 26: OpticalLogiccomp/TransmitCommandcomp/cnt<2>
7: OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_1 17: OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_6 27: OpticalLogiccomp/TransmitCommandcomp/cnt<3>
8: OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_10 18: OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_7 28: OpticalLogiccomp/TransmitCommandcomp/cnt<4>
9: OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_11 19: OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_8 29: OpticalLogiccomp/TransmitCommandcomp/cnt_Msub__sub0000__or0001/OpticalLogiccomp/TransmitCommandcomp/cnt_Msub__sub0000__or0001_D2
10: OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_12 20: OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_9 30: OpticalLogiccomp/TransmitCommandcomp/sending
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
OpticalLogiccomp/TransmitCommandcomp/sending
.......................XXXXX............ 5
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0011/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0011_D2
.......XXX.........X.X.................. 5
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0007/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0007_D2
...............XXXX.X................... 5
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0003/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0003_D2
.....XX.....XXX......................... 5
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_0
....XX.................................. 2
OpticalLogiccomp/TransmitCommandcomp/cnt<4>
..........................XXXX.......... 4
OpticalLogiccomp/TransmitCommandcomp/cnt<2>
.......................XXX...X.......... 4
SPARE<11> XXXX.................................... 4
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_9
....X..............X.X.................. 3
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_7
....X..........XXX..X................... 5
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_6
....X..........XX...X................... 4
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_5
....X..........X....X................... 3
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_3
....XXX.....XX.......................... 5
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_2
....XXX.....X........................... 4
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_14
....X.....XX..........X................. 4
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_13
....X.....X...........X................. 3
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_10
....X..X...........X.X.................. 4
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_1
....XXX................................. 3
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB6 ***********************************
Number of function block inputs used/remaining: 32/22
Number of signals used by logic mapping into function block: 32
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
SendDataCmdsig 1 0 0 4 FB6_1 (b) (b)
FIFO_D<1> 1 0 0 4 FB6_2 135 I/O O
FIFO_D<2> 1 0 0 4 FB6_3 136 I/O O
OPTCMDsig<4> 2 0 0 3 FB6_4 (b) (b)
FIFO_D<3> 1 0 0 4 FB6_5 137 I/O O
FIFO_D<4> 1 0 0 4 FB6_6 138 I/O O
OPTCMDsig<3> 2 0 0 3 FB6_7 (b) (b)
FIFO_D<5> 1 0 0 4 FB6_8 139 I/O O
OPTCMDsig<2> 2 0 0 3 FB6_9 (b) (b)
FIFO_D<6> 1 0 0 4 FB6_10 140 I/O O
OPTCMDsig<1> 2 0 0 3 FB6_11 (b) (b)
OPTCMDsig<0> 2 0 0 3 FB6_12 (b) (b)
MainLogiccomp/MAINSTATE_FFd2
2 0 0 3 FB6_13 (b) (b)
FIFO_D<7> 1 0 0 4 FB6_14 142 I/O O
MainLogiccomp/MAINSTATE_FFd1
2 0 0 3 FB6_15 143 GSR/I/O GSR/I
OpticalLogiccomp/OPTICALLOGICSTATE_FFd2
3 0 0 2 FB6_16 (b) (b)
OpticalLogiccomp/OPTICALLOGICSTATE_FFd1
3 0 0 2 FB6_17 (b) (b)
MainLogiccomp/MAINSTATE_FFd3
4 0 0 1 FB6_18 (b) (b)
Signals Used by Logic in Function Block
1: MainLogiccomp/MAINSTATE_FFd1 12: OPTCMDsig<2> 23: OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<4>
2: MainLogiccomp/MAINSTATE_FFd2 13: OPTCMDsig<3> 24: OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<5>
3: MainLogiccomp/MAINSTATE_FFd3 14: OPTCMDsig<4> 25: OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<6>
4: NICMD_Readysig 15: OPTCMDsig<5> 26: OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<7>
5: NICMDsig<0> 16: OPTCMDsig<6> 27: OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd1
6: NICMDsig<1> 17: OPTCMDsig<7> 28: OpticalLogiccomp/TransmitCommandcomp/sending
7: NICMDsig<2> 18: OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 29: SPARE<10>
8: NICMDsig<3> 19: OpticalLogiccomp/OPTICALLOGICSTATE_FFd2 30: SPARE<11>
9: OPTCMD_Readysig 20: OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<1> 31: SPARE<12>
10: OPTCMDsig<0> 21: OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<2> 32: SPARE<9>
11: OPTCMDsig<1> 22: OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<3>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
SendDataCmdsig X....................................... 1
FIFO_D<1> ...................X......X............. 2
FIFO_D<2> ....................X.....X............. 2
OPTCMDsig<4> .XX..........X.................X........ 4
FIFO_D<3> .....................X....X............. 2
FIFO_D<4> ......................X...X............. 2
OPTCMDsig<3> .XX....X....X........................... 4
FIFO_D<5> .......................X..X............. 2
OPTCMDsig<2> .XX...X....X............................ 4
FIFO_D<6> ........................X.X............. 2
OPTCMDsig<1> .XX..X....X............................. 4
OPTCMDsig<0> .XX.X....X.............................. 4
MainLogiccomp/MAINSTATE_FFd2
XXXX.XXX....................XXXX........ 11
FIFO_D<7> .........................XX............. 2
MainLogiccomp/MAINSTATE_FFd1
XXXXXXXX....................XXXX........ 12
OpticalLogiccomp/OPTICALLOGICSTATE_FFd2
........XXXXXXXXXXX........X............ 12
OpticalLogiccomp/OPTICALLOGICSTATE_FFd1
........XXXXXXXXXXX........X............ 12
MainLogiccomp/MAINSTATE_FFd3
XXXXXXXX....................XXXX........ 12
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB7 ***********************************
Number of function block inputs used/remaining: 35/19
Number of signals used by logic mapping into function block: 35
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<9>
1 0 0 4 FB7_1 (b) (b)
NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0013/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0013_D2
1 0 0 4 FB7_2 (b) (b)
NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0008/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0008_D2
1 0 0 4 FB7_3 45 I/O I
NIDAQLogiccomp/Readtimeoutcounter_0_0
1 0 0 4 FB7_4 (b) (b)
StatusDatasig<9> 2 0 0 3 FB7_5 46 I/O I
OpticalLogiccomp/TransmitCommandcomp/sr<7>
2 0 0 3 FB7_6 (b) (b)
OpticalLogiccomp/TransmitCommandcomp/sr<6>
2 0 0 3 FB7_7 (b) (b)
OpticalLogiccomp/TransmitCommandcomp/sr<5>
2 0 0 3 FB7_8 (b) (b)
OpticalLogiccomp/TransmitCommandcomp/sr<4>
2 0 0 3 FB7_9 (b) (b)
OpticalLogiccomp/TransmitCommandcomp/sr<19>
2 0 0 3 FB7_10 (b) (b)
OpticalLogiccomp/TransmitCommandcomp/sr<18>
2 0 0 3 FB7_11 (b) (b)
OpticalLogiccomp/TransmitCommandcomp/sr<17>
2 0 0 3 FB7_12 48 I/O I
NIDAQLogiccomp/StatusDatasig<9>
2 0 0 3 FB7_13 (b) (b)
NIDAQLogiccomp/Readtimeoutcounter_0_7
2 0 0 3 FB7_14 (b) (b)
NIDAQLogiccomp/Readtimeoutcounter_0_5
2 0 0 3 FB7_15 49 I/O I
NIDAQLogiccomp/Readtimeoutcounter_0_15
2 0 0 3 FB7_16 (b) (b)
NIDAQLogiccomp/Readtimeoutcounter_0_12
2 0 0 3 FB7_17 (b) (b)
NIDAQLogiccomp/Readtimeoutcounter_0_10
2 0 0 3 FB7_18 (b) (b)
Signals Used by Logic in Function Block
1: D<9> 13: NIDAQLogiccomp/Readtimeoutcounter_0_9 25: OpticalLogiccomp/TransmitCommandcomp/sr<7>
2: MainLogiccomp/MAINSTATE_FFd1 14: NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0003/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0003_D2 26: OpticalLogiccomp/TransmitCommandcomp/sr<8>
3: MainLogiccomp/MAINSTATE_FFd3 15: NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0005/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0005_D2 27: OpticalLogiccomp/command_insig<0>
4: NIDAQLogiccomp/Readtimeoutcounter_0_0 16: NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0008/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0008_D2 28: OpticalLogiccomp/command_insig<13>
5: NIDAQLogiccomp/Readtimeoutcounter_0_10 17: NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0010/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0010_D2 29: OpticalLogiccomp/command_insig<14>
6: NIDAQLogiccomp/Readtimeoutcounter_0_12 18: NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0013/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0013_D2 30: OpticalLogiccomp/command_insig<15>
7: NIDAQLogiccomp/Readtimeoutcounter_0_13 19: NIDAQLogiccomp/Readtimeouten 31: OpticalLogiccomp/command_insig<1>
8: NIDAQLogiccomp/Readtimeoutcounter_0_14 20: OpticalLogiccomp/TransmitCommandcomp/sending 32: OpticalLogiccomp/command_insig<2>
9: NIDAQLogiccomp/Readtimeoutcounter_0_15 21: OpticalLogiccomp/TransmitCommandcomp/sr<18> 33: OpticalLogiccomp/command_insig<3>
10: NIDAQLogiccomp/Readtimeoutcounter_0_5 22: OpticalLogiccomp/TransmitCommandcomp/sr<19> 34: StatusDatasig<9>
11: NIDAQLogiccomp/Readtimeoutcounter_0_7 23: OpticalLogiccomp/TransmitCommandcomp/sr<5> 35: rst
12: NIDAQLogiccomp/Readtimeoutcounter_0_8 24: OpticalLogiccomp/TransmitCommandcomp/sr<6>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<9>
X....................................... 1
NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0013/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0013_D2
.....XXX........X....................... 4
NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0008/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0008_D2
..........XXX.X......................... 4
NIDAQLogiccomp/Readtimeoutcounter_0_0
...X..............X..................... 2
StatusDatasig<9> XXX..............................X...... 4
OpticalLogiccomp/TransmitCommandcomp/sr<7>
...................X.....X......X....... 3
OpticalLogiccomp/TransmitCommandcomp/sr<6>
...................X....X......X........ 3
OpticalLogiccomp/TransmitCommandcomp/sr<5>
...................X...X......X......... 3
OpticalLogiccomp/TransmitCommandcomp/sr<4>
...................X..X...X............. 3
OpticalLogiccomp/TransmitCommandcomp/sr<19>
...................X.........X.......... 2
OpticalLogiccomp/TransmitCommandcomp/sr<18>
...................X.X......X........... 3
OpticalLogiccomp/TransmitCommandcomp/sr<17>
...................XX......X............ 3
NIDAQLogiccomp/StatusDatasig<9>
.................................XX..... 2
NIDAQLogiccomp/Readtimeoutcounter_0_7
..........X...X...X..................... 3
NIDAQLogiccomp/Readtimeoutcounter_0_5
.........X...X....X..................... 3
NIDAQLogiccomp/Readtimeoutcounter_0_15
........X........XX..................... 3
NIDAQLogiccomp/Readtimeoutcounter_0_12
.....X..........X.X..................... 3
NIDAQLogiccomp/Readtimeoutcounter_0_10
....X..........X..X..................... 3
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB8 ***********************************
Number of function block inputs used/remaining: 26/28
Number of signals used by logic mapping into function block: 26
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
NIDAQLogiccomp/NI_Interfacecomp/req2_cnt<0>
1 0 0 4 FB8_1 (b) (b)
NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd1
1 0 0 4 FB8_2 130 I/O I
NIDAQLogiccomp/Msub__addsub0000__or0001/NIDAQLogiccomp/Msub__addsub0000__or0001_D2
1 0 0 4 FB8_3 131 I/O I
NIDAQLogiccomp/NumOfWordsSentCounter<7>
2 0 0 3 FB8_4 (b) (b)
WENn 1 0 0 4 FB8_5 132 I/O O
NIDAQLogiccomp/NumOfWordsSentCounter<6>
2 0 0 3 FB8_6 (b) (b)
NIDAQLogiccomp/NumOfWordsSentCounter<5>
2 0 0 3 FB8_7 (b) (b)
WCLK 1 0 0 4 FB8_8 133 I/O O
NIDAQLogiccomp/NumOfWordsSentCounter<4>
2 0 0 3 FB8_9 (b) (b)
FIFO_D<0> 1 0 0 4 FB8_10 134 I/O O
NIDAQLogiccomp/NumOfWordsSentCounter<3>
2 0 0 3 FB8_11 (b) (b)
NIDAQLogiccomp/NumOfWordsSentCounter<2>
2 0 0 3 FB8_12 (b) (b)
NIDAQLogiccomp/NumOfWordsSentCounter<1>
2 0 0 3 FB8_13 (b) (b)
NIDAQLogiccomp/NumOfWordsSentCounter<0>
2 0 0 3 FB8_14 (b) (b)
NIDAQLogiccomp/NI_Interfacecomp/req2_cnt<1>
2 0 0 3 FB8_15 (b) (b)
NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd2
2 0 0 3 FB8_16 (b) (b)
NIDAQLogiccomp/SendingPackageFlag
3 0 0 2 FB8_17 (b) (b)
NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd3
4 0 0 1 FB8_18 (b) (b)
Signals Used by Logic in Function Block
1: EFn 10: NIDAQLogiccomp/NI_Interfacecomp/req2_cnt<1> 19: NIDAQLogiccomp/NumOfWordsSentCounter<7>
2: EventReadoutsig 11: NIDAQLogiccomp/NI_Interfacecomp/req2_cnt_ld 20: NIDAQLogiccomp/SendingPackageFlag
3: NIDAQLogiccomp/Msub__addsub0000__or0001/NIDAQLogiccomp/Msub__addsub0000__or0001_D2 12: NIDAQLogiccomp/NumOfWordsSentCounter<0> 21: NIDAQLogiccomp/wen
4: NIDAQLogiccomp/Msub__addsub0000__or0003/NIDAQLogiccomp/Msub__addsub0000__or0003_D2 13: NIDAQLogiccomp/NumOfWordsSentCounter<1> 22: OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<0>
5: NIDAQLogiccomp/NI_Interfacecomp/ack2_sync 14: NIDAQLogiccomp/NumOfWordsSentCounter<2> 23: OpticalLogiccomp/RxDataLogiccomp/GenDataDonesig
6: NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd1 15: NIDAQLogiccomp/NumOfWordsSentCounter<3> 24: OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd1
7: NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd2 16: NIDAQLogiccomp/NumOfWordsSentCounter<4> 25: OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd2
8: NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd3 17: NIDAQLogiccomp/NumOfWordsSentCounter<5> 26: clk
9: NIDAQLogiccomp/NI_Interfacecomp/req2_cnt<0> 18: NIDAQLogiccomp/NumOfWordsSentCounter<6>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
NIDAQLogiccomp/NI_Interfacecomp/req2_cnt<0>
........X.X............................. 2
NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd1
....X.XX................................ 3
NIDAQLogiccomp/Msub__addsub0000__or0001/NIDAQLogiccomp/Msub__addsub0000__or0001_D2
...........XXX.......................... 3
NIDAQLogiccomp/NumOfWordsSentCounter<7>
...X............XXXXX................... 6
WENn ......................X.X............... 2
NIDAQLogiccomp/NumOfWordsSentCounter<6>
...X............XX.XX................... 5
NIDAQLogiccomp/NumOfWordsSentCounter<5>
...X............X..XX................... 4
WCLK .........................X.............. 1
NIDAQLogiccomp/NumOfWordsSentCounter<4>
..X...........XX...XX................... 5
FIFO_D<0> .....................X.X................ 2
NIDAQLogiccomp/NumOfWordsSentCounter<3>
..X...........X....XX................... 4
NIDAQLogiccomp/NumOfWordsSentCounter<2>
...........XXX.....XX................... 5
NIDAQLogiccomp/NumOfWordsSentCounter<1>
...........XX......XX................... 4
NIDAQLogiccomp/NumOfWordsSentCounter<0>
...........X.......XX................... 3
NIDAQLogiccomp/NI_Interfacecomp/req2_cnt<1>
........XXX............................. 3
NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd2
....X.XX................................ 3
NIDAQLogiccomp/SendingPackageFlag
XX.........XXXXXXXXX.................... 11
NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd3
....XXXXXX..........X................... 7
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB9 ***********************************
Number of function block inputs used/remaining: 29/25
Number of signals used by logic mapping into function block: 29
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
OpticalLogiccomp/TransmitCommandcomp/sr<3>
1 0 0 4 FB9_1 (b) (b)
OpticalLogiccomp/TransmitCommandcomp/sr<2>
1 0 0 4 FB9_2 50 I/O I
OpticalLogiccomp/TransmitCommandcomp/sr<1>
1 0 0 4 FB9_3 51 I/O I
OpticalLogiccomp/TransmitCommandcomp/sr<0>
1 0 0 4 FB9_4 (b) (b)
OpticalLogiccomp/TransmitCommandcomp/cnt_Msub__sub0000__or0001/OpticalLogiccomp/TransmitCommandcomp/cnt_Msub__sub0000__or0001_D2
1 0 0 4 FB9_5 52 I/O I
NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0010/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0010_D2
1 0 0 4 FB9_6 53 I/O I
NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0005/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0005_D2
1 0 0 4 FB9_7 (b) (b)
NIDAQLogiccomp/NI_Interfacecomp/ack2_sync
1 0 0 4 FB9_8 54 I/O I
NIDAQLogiccomp/NI_Interfacecomp/ack1_sync<1>
1 0 0 4 FB9_9 (b) (b)
NIDAQLogiccomp/Msub__addsub0000__or0003/NIDAQLogiccomp/Msub__addsub0000__or0003_D2
1 0 0 4 FB9_10 (b) (b)
NIDAQLogiccomp/StatusDatasig<8>
2 0 0 3 FB9_11 56 I/O I
NIDAQLogiccomp/StatusDatasig<7>
2 0 0 3 FB9_12 57 I/O I
NIDAQLogiccomp/StatusDatasig<5>
2 0 0 3 FB9_13 (b) (b)
NIDAQLogiccomp/StatusDatasig<4>
2 0 0 3 FB9_14 58 I/O I
NIDAQLogiccomp/StatusDatasig<2>
2 0 0 3 FB9_15 (b) (b)
NIDAQLogiccomp/StatusDatasig<1>
2 0 0 3 FB9_16 (b) (b)
NIDAQLogiccomp/StatusDatasig<15>
2 0 0 3 FB9_17 59 I/O I
EventReadysig 2 0 0 3 FB9_18 (b) (b)
Signals Used by Logic in Function Block
1: ACK2 11: NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0003/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0003_D2 21: OpticalLogiccomp/TransmitCommandcomp/sr<4>
2: EventReadysig/EventReadysig_RSTF 12: NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0008/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0008_D2 22: StatusDatasig<15>
3: NIDAQLogiccomp/Msub__addsub0000__or0001/NIDAQLogiccomp/Msub__addsub0000__or0001_D2 13: OpticalLogiccomp/RxDataLogiccomp/EventReadyCmd 23: StatusDatasig<1>
4: NIDAQLogiccomp/NI_Interfacecomp/ack1_sync<0> 14: OpticalLogiccomp/TransmitCommandcomp/cnt<0> 24: StatusDatasig<2>
5: NIDAQLogiccomp/NumOfWordsSentCounter<3> 15: OpticalLogiccomp/TransmitCommandcomp/cnt<1> 25: StatusDatasig<4>
6: NIDAQLogiccomp/NumOfWordsSentCounter<4> 16: OpticalLogiccomp/TransmitCommandcomp/cnt<2> 26: StatusDatasig<5>
7: NIDAQLogiccomp/Readtimeoutcounter_0_10 17: OpticalLogiccomp/TransmitCommandcomp/sending 27: StatusDatasig<7>
8: NIDAQLogiccomp/Readtimeoutcounter_0_11 18: OpticalLogiccomp/TransmitCommandcomp/sr<1> 28: StatusDatasig<8>
9: NIDAQLogiccomp/Readtimeoutcounter_0_5 19: OpticalLogiccomp/TransmitCommandcomp/sr<2> 29: rst
10: NIDAQLogiccomp/Readtimeoutcounter_0_6 20: OpticalLogiccomp/TransmitCommandcomp/sr<3>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
OpticalLogiccomp/TransmitCommandcomp/sr<3>
................X...X................... 2
OpticalLogiccomp/TransmitCommandcomp/sr<2>
................X..X.................... 2
OpticalLogiccomp/TransmitCommandcomp/sr<1>
................X.X..................... 2
OpticalLogiccomp/TransmitCommandcomp/sr<0>
................XX...................... 2
OpticalLogiccomp/TransmitCommandcomp/cnt_Msub__sub0000__or0001/OpticalLogiccomp/TransmitCommandcomp/cnt_Msub__sub0000__or0001_D2
.............XXX........................ 3
NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0010/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0010_D2
......XX...X............................ 3
NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0005/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0005_D2
........XXX............................. 3
NIDAQLogiccomp/NI_Interfacecomp/ack2_sync
X....................................... 1
NIDAQLogiccomp/NI_Interfacecomp/ack1_sync<1>
...X.................................... 1
NIDAQLogiccomp/Msub__addsub0000__or0003/NIDAQLogiccomp/Msub__addsub0000__or0003_D2
..X.XX.................................. 3
NIDAQLogiccomp/StatusDatasig<8>
...........................XX........... 2
NIDAQLogiccomp/StatusDatasig<7>
..........................X.X........... 2
NIDAQLogiccomp/StatusDatasig<5>
.........................X..X........... 2
NIDAQLogiccomp/StatusDatasig<4>
........................X...X........... 2
NIDAQLogiccomp/StatusDatasig<2>
.......................X....X........... 2
NIDAQLogiccomp/StatusDatasig<1>
......................X.....X........... 2
NIDAQLogiccomp/StatusDatasig<15>
.....................X......X........... 2
EventReadysig .X..........X........................... 2
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB10 ***********************************
Number of function block inputs used/remaining: 28/26
Number of signals used by logic mapping into function block: 28
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
OpticalLogiccomp/RxDataLogiccomp/GenDataDonesig
1 0 0 4 FB10_1 (b) (b)
STOPTRIG2 0 0 0 5 FB10_2 117 I/O O
NIDAQLogiccomp/cav 1 0 0 4 FB10_3 118 I/O (b)
NIDAQLogiccomp/NI_Interfacecomp/ack1_sync<2>
1 0 0 4 FB10_4 (b) (b)
SPARE<7> 1 0 0 4 FB10_5 119 I/O O
SPARE<6> 1 0 0 4 FB10_6 120 I/O O
NIDAQLogiccomp/NI_Interfacecomp/ack1_sync<0>
1 0 0 4 FB10_7 (b) (b)
SPARE<5> 1 0 0 4 FB10_8 121 I/O O
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_8
2 0 0 3 FB10_9 (b) (b)
SPARE<4> 1 0 0 4 FB10_10 124 I/O O
SPARE<3> 1 0 0 4 FB10_11 125 I/O O
SPARE<2> 2 0 0 3 FB10_12 126 I/O O
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_4
2 0 0 3 FB10_13 (b) (b)
SPARE<1> 2 0 0 3 FB10_14 128 I/O O
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_15
2 0 0 3 FB10_15 (b) (b)
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_12
2 0 0 3 FB10_16 (b) (b)
SPARE<0> 3 0 0 2 FB10_17 129 I/O O
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_11
2 0 0 3 FB10_18 (b) (b)
Signals Used by Logic in Function Block
1: ACK1 11: OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_1 20: OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_4
2: NIDAQLogiccomp/NIDAQSTATE_FFd1 12: OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_10 21: OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_5
3: NIDAQLogiccomp/NIDAQSTATE_FFd2 13: OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_11 22: OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_6
4: NIDAQLogiccomp/NIDAQSTATE_FFd3 14: OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_12 23: OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_7
5: NIDAQLogiccomp/NI_Interfacecomp/ack1_sync<1> 15: OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_13 24: OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_8
6: NIDAQLogiccomp/NI_Interfacecomp/ack1_sync<2> 16: OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_14 25: OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_9
7: NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd3 17: OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_15 26: OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0003/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0003_D2
8: NIDAQLogiccomp/cav 18: OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_2 27: OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0007/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0007_D2
9: OpticalLogiccomp/RxDataLogiccomp/Busy 19: OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_3 28: OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0011/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0011_D2
10: OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_0
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
OpticalLogiccomp/RxDataLogiccomp/GenDataDonesig
.........XXXXXXXXXXXXXXXX............... 16
STOPTRIG2 ........................................ 0
NIDAQLogiccomp/cav ....XX.................................. 2
NIDAQLogiccomp/NI_Interfacecomp/ack1_sync<2>
....X................................... 1
SPARE<7> ......X................................. 1
SPARE<6> X....................................... 1
NIDAQLogiccomp/NI_Interfacecomp/ack1_sync<0>
X....................................... 1
SPARE<5> .....X.................................. 1
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_8
........X...........XXXX.XX............. 7
SPARE<4> .XXX.................................... 3
SPARE<3> .......X................................ 1
SPARE<2> .XXX.................................... 3
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_4
........XXX......XXX.....X.............. 7
SPARE<1> .XXX.................................... 3
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_15
........X.....XXX..........X............ 5
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_12
........X..XXX..........X.XX............ 7
SPARE<0> .XXX.................................... 3
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_11
........X..XX...........X.X............. 5
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB11 ***********************************
Number of function block inputs used/remaining: 32/22
Number of signals used by logic mapping into function block: 32
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
OpticalLogiccomp/command_insig<6>
2 0 0 3 FB11_1 (b) (b)
OpticalLogiccomp/command_insig<14>
2 0 0 3 FB11_2 (b) (b)
OpticalLogiccomp/command_insig<13>
2 0 0 3 FB11_3 60 I/O I
OpticalLogiccomp/command_insig<12>
2 0 0 3 FB11_4 (b) (b)
OpticalLogiccomp/command_insig<11>
2 0 0 3 FB11_5 61 I/O I
OpticalLogiccomp/command_insig<10>
2 0 0 3 FB11_6 (b) (b)
NICMDsig<3> 2 0 0 3 FB11_7 (b) (b)
NICMDsig<2> 2 0 0 3 FB11_8 (b) (b)
NICMDsig<1> 2 0 0 3 FB11_9 (b) (b)
CTRL 1 0 0 4 FB11_10 64 I/O O
SPARE<10> 2 0 0 3 FB11_11 66 I/O O
SPARE<9> 2 0 0 3 FB11_12 68 I/O O
NICMDsig<0> 2 0 0 3 FB11_13 (b) (b)
SPARE<8> 1 0 0 4 FB11_14 69 I/O O
NICMD_Argsig<7> 2 0 0 3 FB11_15 (b) (b)
NICMD_Argsig<6> 2 0 0 3 FB11_16 (b) (b)
NICMD_Argsig<5> 2 0 0 3 FB11_17 70 I/O I
OpticalLogiccomp/command_insig<0>
3 0 0 2 FB11_18 (b) (b)
Signals Used by Logic in Function Block
1: ACK2 12: NIDAQLogiccomp/command_out<7> 23: OpticalLogiccomp/OPTICALLOGICSTATE_FFd2
2: HFn 13: NIDAQLogiccomp/command_out<8> 24: OpticalLogiccomp/TransmitCommandcomp/sending
3: NIDAQLogiccomp/NIDAQSTATE_FFd1 14: NIDAQLogiccomp/command_out<9> 25: OpticalLogiccomp/TransmitCommandcomp/sr<0>
4: NIDAQLogiccomp/NIDAQSTATE_FFd2 15: OPTCMD_Argsig<0> 26: OpticalLogiccomp/command_insig<0>
5: NIDAQLogiccomp/NIDAQSTATE_FFd3 16: OPTCMD_Argsig<6> 27: OpticalLogiccomp/command_insig<10>
6: NIDAQLogiccomp/command_out<10> 17: OPTCMDsig<2> 28: OpticalLogiccomp/command_insig<11>
7: NIDAQLogiccomp/command_out<11> 18: OPTCMDsig<3> 29: OpticalLogiccomp/command_insig<12>
8: NIDAQLogiccomp/command_out<12> 19: OPTCMDsig<4> 30: OpticalLogiccomp/command_insig<13>
9: NIDAQLogiccomp/command_out<13> 20: OPTCMDsig<5> 31: OpticalLogiccomp/command_insig<14>
10: NIDAQLogiccomp/command_out<5> 21: OPTCMDsig<6> 32: OpticalLogiccomp/command_insig<6>
11: NIDAQLogiccomp/command_out<6> 22: OpticalLogiccomp/OPTICALLOGICSTATE_FFd1
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
OpticalLogiccomp/command_insig<6>
...............X.....XX........X........ 4
OpticalLogiccomp/command_insig<14>
....................XXX.......X......... 4
OpticalLogiccomp/command_insig<13>
...................X.XX......X.......... 4
OpticalLogiccomp/command_insig<12>
..................X..XX.....X........... 4
OpticalLogiccomp/command_insig<11>
.................X...XX....X............ 4
OpticalLogiccomp/command_insig<10>
................X....XX...X............. 4
NICMDsig<3> ..XXX.X................................. 4
NICMDsig<2> ..XXXX.................................. 4
NICMDsig<1> ..XXX........X.......................... 4
CTRL .......................XX............... 2
SPARE<10> ..XXX...X............................... 4
SPARE<9> ..XXX..X................................ 4
NICMDsig<0> ..XXX.......X........................... 4
SPARE<8> X....................................... 1
NICMD_Argsig<7> ..XXX......X............................ 4
NICMD_Argsig<6> ..XXX.....X............................. 4
NICMD_Argsig<5> ..XXX....X.............................. 4
OpticalLogiccomp/command_insig<0>
.X............X......XX..X.............. 5
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB12 ***********************************
Number of function block inputs used/remaining: 32/22
Number of signals used by logic mapping into function block: 32
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
OpticalLogiccomp/command_insig<3>
2 0 0 3 FB12_1 (b) (b)
OpticalLogiccomp/command_insig<2>
2 0 0 3 FB12_2 110 I/O I
REQ2 1 0 0 4 FB12_3 111 I/O O
OpticalLogiccomp/command_insig<1>
2 0 0 3 FB12_4 (b) (b)
STOPTRIG1 0 0 0 5 FB12_5 112 I/O O
OpticalLogiccomp/command_insig<15>
2 0 0 3 FB12_6 (b) (b)
OPTCMDsig<7> 2 0 0 3 FB12_7 (b) (b)
OPTCMDsig<6> 2 0 0 3 FB12_8 113 I/O (b)
OPTCMDsig<5> 2 0 0 3 FB12_9 (b) (b)
OPTCMD_Argsig<7> 2 0 0 3 FB12_10 115 I/O I
OPTCMD_Argsig<6> 2 0 0 3 FB12_11 (b) (b)
REQ1 1 0 0 4 FB12_12 116 I/O O
OPTCMD_Argsig<5> 2 0 0 3 FB12_13 (b) (b)
OPTCMD_Argsig<4> 2 0 0 3 FB12_14 (b) (b)
OPTCMD_Argsig<3> 2 0 0 3 FB12_15 (b) (b)
OPTCMD_Argsig<2> 2 0 0 3 FB12_16 (b) (b)
OPTCMD_Argsig<1> 2 0 0 3 FB12_17 (b) (b)
OPTCMD_Argsig<0> 2 0 0 3 FB12_18 (b) (b)
Signals Used by Logic in Function Block
1: MainLogiccomp/MAINSTATE_FFd2 12: NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd3 23: OPTCMDsig<7>
2: MainLogiccomp/MAINSTATE_FFd3 13: OPTCMD_Argsig<0> 24: OpticalLogiccomp/OPTICALLOGICSTATE_FFd1
3: NICMD_Argsig<0> 14: OPTCMD_Argsig<1> 25: OpticalLogiccomp/OPTICALLOGICSTATE_FFd2
4: NICMD_Argsig<1> 15: OPTCMD_Argsig<2> 26: OpticalLogiccomp/command_insig<15>
5: NICMD_Argsig<2> 16: OPTCMD_Argsig<3> 27: OpticalLogiccomp/command_insig<1>
6: NICMD_Argsig<3> 17: OPTCMD_Argsig<4> 28: OpticalLogiccomp/command_insig<2>
7: NICMD_Argsig<4> 18: OPTCMD_Argsig<5> 29: OpticalLogiccomp/command_insig<3>
8: NICMD_Argsig<5> 19: OPTCMD_Argsig<6> 30: SPARE<10>
9: NICMD_Argsig<6> 20: OPTCMD_Argsig<7> 31: SPARE<11>
10: NICMD_Argsig<7> 21: OPTCMDsig<5> 32: SPARE<12>
11: NIDAQLogiccomp/NI_Interfacecomp/ack1_sync<2> 22: OPTCMDsig<6>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
OpticalLogiccomp/command_insig<3>
...............X.......XX...X........... 4
OpticalLogiccomp/command_insig<2>
..............X........XX..X............ 4
REQ2 ...........X............................ 1
OpticalLogiccomp/command_insig<1>
.............X.........XX.X............. 4
STOPTRIG1 ........................................ 0
OpticalLogiccomp/command_insig<15>
......................XXXX.............. 4
OPTCMDsig<7> XX....................X........X........ 4
OPTCMDsig<6> XX...................X........X......... 4
OPTCMDsig<5> XX..................X........X.......... 4
OPTCMD_Argsig<7> XX.......X.........X.................... 4
OPTCMD_Argsig<6> XX......X.........X..................... 4
REQ1 ..........X............................. 1
OPTCMD_Argsig<5> XX.....X.........X...................... 4
OPTCMD_Argsig<4> XX....X.........X....................... 4
OPTCMD_Argsig<3> XX...X.........X........................ 4
OPTCMD_Argsig<2> XX..X.........X......................... 4
OPTCMD_Argsig<1> XX.X.........X.......................... 4
OPTCMD_Argsig<0> XXX.........X........................... 4
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB13 ***********************************
Number of function block inputs used/remaining: 19/35
Number of signals used by logic mapping into function block: 19
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
NIDAQLogiccomp/command_out<9>
1 0 0 4 FB13_1 (b) (b)
NIDAQLogiccomp/command_out<8>
1 0 0 4 FB13_2 71 I/O I
NIDAQLogiccomp/command_out<7>
1 0 0 4 FB13_3 (b) (b)
NIDAQLogiccomp/command_out<6>
1 0 0 4 FB13_4 (b) (b)
NIDAQLogiccomp/command_out<5>
1 0 0 4 FB13_5 (b) (b)
NIDAQLogiccomp/command_out<4>
1 0 0 4 FB13_6 (b) (b)
NIDAQLogiccomp/command_out<3>
1 0 0 4 FB13_7 (b) (b)
NIDAQLogiccomp/command_out<2>
1 0 0 4 FB13_8 74 I/O I
NIDAQLogiccomp/command_out<1>
1 0 0 4 FB13_9 (b) (b)
NIDAQLogiccomp/command_out<15>
1 0 0 4 FB13_10 (b) (b)
NIDAQLogiccomp/command_out<14>
1 0 0 4 FB13_11 75 I/O I
NIDAQLogiccomp/command_out<13>
1 0 0 4 FB13_12 (b) (b)
NIDAQLogiccomp/command_out<12>
1 0 0 4 FB13_13 (b) (b)
NIDAQLogiccomp/command_out<11>
1 0 0 4 FB13_14 76 I/O I
NIDAQLogiccomp/command_out<10>
1 0 0 4 FB13_15 77 I/O I
NIDAQLogiccomp/command_out<0>
1 0 0 4 FB13_16 (b) (b)
NIDAQLogiccomp/NI_Interfacecomp/req2_cnt_ld
1 0 0 4 FB13_17 78 I/O I
EventReadysig/EventReadysig_RSTF
1 0 0 4 FB13_18 (b) (b)
Signals Used by Logic in Function Block
1: DIOA<0> 8: DIOA<7> 14: DIOB<5>
2: DIOA<1> 9: DIOB<0> 15: DIOB<6>
3: DIOA<2> 10: DIOB<1> 16: DIOB<7>
4: DIOA<3> 11: DIOB<2> 17: EventReadoutsig
5: DIOA<4> 12: DIOB<3> 18: NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd2
6: DIOA<5> 13: DIOB<4> 19: rst
7: DIOA<6>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
NIDAQLogiccomp/command_out<9>
.X...................................... 1
NIDAQLogiccomp/command_out<8>
X....................................... 1
NIDAQLogiccomp/command_out<7>
...............X........................ 1
NIDAQLogiccomp/command_out<6>
..............X......................... 1
NIDAQLogiccomp/command_out<5>
.............X.......................... 1
NIDAQLogiccomp/command_out<4>
............X........................... 1
NIDAQLogiccomp/command_out<3>
...........X............................ 1
NIDAQLogiccomp/command_out<2>
..........X............................. 1
NIDAQLogiccomp/command_out<1>
.........X.............................. 1
NIDAQLogiccomp/command_out<15>
.......X................................ 1
NIDAQLogiccomp/command_out<14>
......X................................. 1
NIDAQLogiccomp/command_out<13>
.....X.................................. 1
NIDAQLogiccomp/command_out<12>
....X................................... 1
NIDAQLogiccomp/command_out<11>
...X.................................... 1
NIDAQLogiccomp/command_out<10>
..X..................................... 1
NIDAQLogiccomp/command_out<0>
........X............................... 1
NIDAQLogiccomp/NI_Interfacecomp/req2_cnt_ld
.................X...................... 1
EventReadysig/EventReadysig_RSTF
................X.X..................... 2
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB14 ***********************************
Number of function block inputs used/remaining: 35/19
Number of signals used by logic mapping into function block: 35
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB14_1 (b)
NIDAQLogiccomp/wen 1 0 0 4 FB14_2 (b) (b)
DIOD<7> 3 0 0 2 FB14_3 100 I/O O
NIDAQLogiccomp/Readtimeouten
1 0 0 4 FB14_4 (b) (b)
DIOD<6> 3 0 0 2 FB14_5 101 I/O O
DIOD<5> 3 0 0 2 FB14_6 102 I/O O
NICMD_Readysig 1 0 0 4 FB14_7 (b) (b)
DIOD<4> 3 0 0 2 FB14_8 103 I/O O
$OpTx$FX_SC$69 1 0 0 4 FB14_9 (b) (b)
DIOD<3> 3 0 0 2 FB14_10 104 I/O O
DIOD<2> 3 0 0 2 FB14_11 105 I/O O
NIDAQLogiccomp/N8/NIDAQLogiccomp/N8_D2
2 0 0 3 FB14_12 (b) (b)
BUF_NIDAQLogiccomp/wen
2 0 0 3 FB14_13 (b) (b)
DIOD<1> 3 0 0 2 FB14_14 106 I/O O
DIOD<0> 3 0 0 2 FB14_15 107 I/O O
NIDAQLogiccomp/NIDAQSTATE_FFd2
3 0 0 2 FB14_16 (b) (b)
NIDAQLogiccomp/NIDAQSTATE_FFd3
4 0 0 1 FB14_17 (b) (b)
NIDAQLogiccomp/NIDAQSTATE_FFd1
4 0 0 1 FB14_18 (b) (b)
Signals Used by Logic in Function Block
1: $OpTx$FX_SC$69 13: FIFO_Q<12> 25: NIDAQLogiccomp/StatusDatasig<10>
2: BUF_NIDAQLogiccomp/wen 14: FIFO_Q<13> 26: NIDAQLogiccomp/StatusDatasig<11>
3: DIOD<0> 15: FIFO_Q<14> 27: NIDAQLogiccomp/StatusDatasig<12>
4: DIOD<1> 16: FIFO_Q<15> 28: NIDAQLogiccomp/StatusDatasig<13>
5: DIOD<2> 17: FIFO_Q<8> 29: NIDAQLogiccomp/StatusDatasig<14>
6: DIOD<3> 18: FIFO_Q<9> 30: NIDAQLogiccomp/StatusDatasig<15>
7: DIOD<4> 19: NIDAQLogiccomp/N8/NIDAQLogiccomp/N8_D2 31: NIDAQLogiccomp/StatusDatasig<8>
8: DIOD<5> 20: NIDAQLogiccomp/NIDAQSTATE_FFd1 32: NIDAQLogiccomp/StatusDatasig<9>
9: DIOD<6> 21: NIDAQLogiccomp/NIDAQSTATE_FFd2 33: NIDAQLogiccomp/cav
10: DIOD<7> 22: NIDAQLogiccomp/NIDAQSTATE_FFd3 34: NIDAQLogiccomp/wdone
11: FIFO_Q<10> 23: NIDAQLogiccomp/Readtimeout 35: SendDataCmdsig
12: FIFO_Q<11> 24: NIDAQLogiccomp/SendingPackageFlag
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
NIDAQLogiccomp/wen .X...................................... 1
DIOD<7> XX.......X.....X..XXX........X.......... 8
NIDAQLogiccomp/Readtimeouten
...................X.X.................. 2
DIOD<6> XX......X.....X...XXX.......X........... 8
DIOD<5> XX.....X.....X....XXX......X............ 8
NICMD_Readysig ...................XXX.................. 3
DIOD<4> XX....X.....X.....XXX.....X............. 8
$OpTx$FX_SC$69 ....................XX.................. 2
DIOD<3> XX...X.....X......XXX....X.............. 8
DIOD<2> XX..X.....X.......XXX...X............... 8
NIDAQLogiccomp/N8/NIDAQLogiccomp/N8_D2
...................XXX.................. 3
BUF_NIDAQLogiccomp/wen
...................XXX.................. 3
DIOD<1> XX.X.............XXXX..........X........ 8
DIOD<0> XXX.............X.XXX.........X......... 8
NIDAQLogiccomp/NIDAQSTATE_FFd2
...................XXX.X........X.X..... 6
NIDAQLogiccomp/NIDAQSTATE_FFd3
...................XXXXX........XX...... 7
NIDAQLogiccomp/NIDAQSTATE_FFd1
XX.................X.XXX........XXX..... 9
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB15 ***********************************
Number of function block inputs used/remaining: 16/38
Number of signals used by logic mapping into function block: 16
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB15_1 (b)
(unused) 0 0 0 5 FB15_2 79 I/O I
OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<8>
1 0 0 4 FB15_3 80 I/O I
OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<7>
1 0 0 4 FB15_4 (b) (b)
OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<6>
1 0 0 4 FB15_5 (b) (b)
OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<5>
1 0 0 4 FB15_6 (b) (b)
OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<4>
1 0 0 4 FB15_7 (b) (b)
OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<3>
1 0 0 4 FB15_8 81 I/O I
OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<2>
1 0 0 4 FB15_9 (b) (b)
OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<1>
1 0 0 4 FB15_10 82 I/O I
OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<15>
1 0 0 4 FB15_11 83 I/O I
OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<14>
1 0 0 4 FB15_12 85 I/O I
OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<13>
1 0 0 4 FB15_13 (b) (b)
OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<12>
1 0 0 4 FB15_14 86 I/O I
OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<11>
1 0 0 4 FB15_15 87 I/O I
OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<10>
1 0 0 4 FB15_16 (b) (b)
OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<0>
1 0 0 4 FB15_17 88 I/O I
NIDAQLogiccomp/wdone
1 0 0 4 FB15_18 (b) (b)
Signals Used by Logic in Function Block
1: D<0> 7: D<15> 12: D<5>
2: D<10> 8: D<1> 13: D<6>
3: D<11> 9: D<2> 14: D<7>
4: D<12> 10: D<3> 15: D<8>
5: D<13> 11: D<4> 16: NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd1
6: D<14>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<8>
..............X......................... 1
OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<7>
.............X.......................... 1
OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<6>
............X........................... 1
OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<5>
...........X............................ 1
OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<4>
..........X............................. 1
OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<3>
.........X.............................. 1
OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<2>
........X............................... 1
OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<1>
.......X................................ 1
OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<15>
......X................................. 1
OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<14>
.....X.................................. 1
OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<13>
....X................................... 1
OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<12>
...X.................................... 1
OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<11>
..X..................................... 1
OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<10>
.X...................................... 1
OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig<0>
X....................................... 1
NIDAQLogiccomp/wdone
...............X........................ 1
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB16 ***********************************
Number of function block inputs used/remaining: 35/19
Number of signals used by logic mapping into function block: 35
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB16_1 (b)
DIOC<7> 3 0 0 2 FB16_2 91 I/O O
DIOC<6> 3 0 0 2 FB16_3 92 I/O O
(unused) 0 0 0 5 FB16_4 (b)
DIOC<5> 3 0 0 2 FB16_5 93 I/O O
DIOC<4> 3 0 0 2 FB16_6 94 I/O O
(unused) 0 0 0 5 FB16_7 (b)
DIOC<3> 3 0 0 2 FB16_8 95 I/O O
(unused) 0 0 0 5 FB16_9 (b)
DIOC<2> 3 0 0 2 FB16_10 96 I/O O
DIOC<1> 3 0 0 2 FB16_11 97 I/O O
DIOC<0> 3 0 0 2 FB16_12 98 I/O O
(unused) 0 0 0 5 FB16_13 (b)
NICMD_Argsig<4> 2 0 0 3 FB16_14 (b) (b)
NICMD_Argsig<3> 2 0 0 3 FB16_15 (b) (b)
NICMD_Argsig<2> 2 0 0 3 FB16_16 (b) (b)
NICMD_Argsig<1> 2 0 0 3 FB16_17 (b) (b)
NICMD_Argsig<0> 2 0 0 3 FB16_18 (b) (b)
Signals Used by Logic in Function Block
1: $OpTx$FX_SC$69 13: FIFO_Q<2> 25: NIDAQLogiccomp/StatusDatasig<2>
2: BUF_NIDAQLogiccomp/wen 14: FIFO_Q<3> 26: NIDAQLogiccomp/StatusDatasig<3>
3: DIOC<0> 15: FIFO_Q<4> 27: NIDAQLogiccomp/StatusDatasig<4>
4: DIOC<1> 16: FIFO_Q<5> 28: NIDAQLogiccomp/StatusDatasig<5>
5: DIOC<2> 17: FIFO_Q<6> 29: NIDAQLogiccomp/StatusDatasig<6>
6: DIOC<3> 18: FIFO_Q<7> 30: NIDAQLogiccomp/StatusDatasig<7>
7: DIOC<4> 19: NIDAQLogiccomp/N8/NIDAQLogiccomp/N8_D2 31: NIDAQLogiccomp/command_out<0>
8: DIOC<5> 20: NIDAQLogiccomp/NIDAQSTATE_FFd1 32: NIDAQLogiccomp/command_out<1>
9: DIOC<6> 21: NIDAQLogiccomp/NIDAQSTATE_FFd2 33: NIDAQLogiccomp/command_out<2>
10: DIOC<7> 22: NIDAQLogiccomp/NIDAQSTATE_FFd3 34: NIDAQLogiccomp/command_out<3>
11: FIFO_Q<0> 23: NIDAQLogiccomp/StatusDatasig<0> 35: NIDAQLogiccomp/command_out<4>
12: FIFO_Q<1> 24: NIDAQLogiccomp/StatusDatasig<1>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
DIOC<7> XX.......X.......XXXX........X.......... 8
DIOC<6> XX......X.......X.XXX.......X........... 8
DIOC<5> XX.....X.......X..XXX......X............ 8
DIOC<4> XX....X.......X...XXX.....X............. 8
DIOC<3> XX...X.......X....XXX....X.............. 8
DIOC<2> XX..X.......X.....XXX...X............... 8
DIOC<1> XX.X.......X......XXX..X................ 8
DIOC<0> XXX.......X.......XXX.X................. 8
NICMD_Argsig<4> ...................XXX............X..... 4
NICMD_Argsig<3> ...................XXX...........X...... 4
NICMD_Argsig<2> ...................XXX..........X....... 4
NICMD_Argsig<1> ...................XXX.........X........ 4
NICMD_Argsig<0> ...................XXX........X......... 4
0----+----1----+----2----+----3----+----4
0 0 0 0
******************************* Equations ********************************
********** Mapped Logic **********
$OpTx$FX_SC$69 <= (NOT NIDAQLogiccomp/NIDAQSTATE_FFd3 AND
NIDAQLogiccomp/NIDAQSTATE_FFd2);
BUF_NIDAQLogiccomp/wen <= ((NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NOT NIDAQLogiccomp/NIDAQSTATE_FFd3)
OR (NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NIDAQLogiccomp/NIDAQSTATE_FFd2));
CTRL <= (OpticalLogiccomp/TransmitCommandcomp/sending AND
OpticalLogiccomp/TransmitCommandcomp/sr(0));
FDCPE_DIOC0: FDCPE port map (DIOC(0),DIOC_D(0),clk,rst,'0');
DIOC_D(0) <= ((FIFO_Q(0) AND
NIDAQLogiccomp/N8/NIDAQLogiccomp/N8_D2)
OR (DIOC(0) AND NOT BUF_NIDAQLogiccomp/wen AND
NOT $OpTx$FX_SC$69)
OR (NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NIDAQLogiccomp/NIDAQSTATE_FFd2 AND NIDAQLogiccomp/StatusDatasig(0)));
FDCPE_DIOC1: FDCPE port map (DIOC(1),DIOC_D(1),clk,rst,'0');
DIOC_D(1) <= ((FIFO_Q(1) AND
NIDAQLogiccomp/N8/NIDAQLogiccomp/N8_D2)
OR (DIOC(1) AND NOT BUF_NIDAQLogiccomp/wen AND
NOT $OpTx$FX_SC$69)
OR (NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NIDAQLogiccomp/NIDAQSTATE_FFd2 AND NIDAQLogiccomp/StatusDatasig(1)));
FDCPE_DIOC2: FDCPE port map (DIOC(2),DIOC_D(2),clk,rst,'0');
DIOC_D(2) <= ((FIFO_Q(2) AND
NIDAQLogiccomp/N8/NIDAQLogiccomp/N8_D2)
OR (DIOC(2) AND NOT BUF_NIDAQLogiccomp/wen AND
NOT $OpTx$FX_SC$69)
OR (NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NIDAQLogiccomp/NIDAQSTATE_FFd2 AND NIDAQLogiccomp/StatusDatasig(2)));
FDCPE_DIOC3: FDCPE port map (DIOC(3),DIOC_D(3),clk,rst,'0');
DIOC_D(3) <= ((FIFO_Q(3) AND
NIDAQLogiccomp/N8/NIDAQLogiccomp/N8_D2)
OR (DIOC(3) AND NOT BUF_NIDAQLogiccomp/wen AND
NOT $OpTx$FX_SC$69)
OR (NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NIDAQLogiccomp/NIDAQSTATE_FFd2 AND NIDAQLogiccomp/StatusDatasig(3)));
FDCPE_DIOC4: FDCPE port map (DIOC(4),DIOC_D(4),clk,rst,'0');
DIOC_D(4) <= ((FIFO_Q(4) AND
NIDAQLogiccomp/N8/NIDAQLogiccomp/N8_D2)
OR (DIOC(4) AND NOT BUF_NIDAQLogiccomp/wen AND
NOT $OpTx$FX_SC$69)
OR (NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NIDAQLogiccomp/NIDAQSTATE_FFd2 AND NIDAQLogiccomp/StatusDatasig(4)));
FDCPE_DIOC5: FDCPE port map (DIOC(5),DIOC_D(5),clk,rst,'0');
DIOC_D(5) <= ((FIFO_Q(5) AND
NIDAQLogiccomp/N8/NIDAQLogiccomp/N8_D2)
OR (DIOC(5) AND NOT BUF_NIDAQLogiccomp/wen AND
NOT $OpTx$FX_SC$69)
OR (NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NIDAQLogiccomp/NIDAQSTATE_FFd2 AND NIDAQLogiccomp/StatusDatasig(5)));
FDCPE_DIOC6: FDCPE port map (DIOC(6),DIOC_D(6),clk,rst,'0');
DIOC_D(6) <= ((FIFO_Q(6) AND
NIDAQLogiccomp/N8/NIDAQLogiccomp/N8_D2)
OR (DIOC(6) AND NOT BUF_NIDAQLogiccomp/wen AND
NOT $OpTx$FX_SC$69)
OR (NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NIDAQLogiccomp/NIDAQSTATE_FFd2 AND NIDAQLogiccomp/StatusDatasig(6)));
FDCPE_DIOC7: FDCPE port map (DIOC(7),DIOC_D(7),clk,rst,'0');
DIOC_D(7) <= ((FIFO_Q(7) AND
NIDAQLogiccomp/N8/NIDAQLogiccomp/N8_D2)
OR (DIOC(7) AND NOT BUF_NIDAQLogiccomp/wen AND
NOT $OpTx$FX_SC$69)
OR (NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NIDAQLogiccomp/NIDAQSTATE_FFd2 AND NIDAQLogiccomp/StatusDatasig(7)));
FDCPE_DIOD0: FDCPE port map (DIOD(0),DIOD_D(0),clk,rst,'0');
DIOD_D(0) <= ((FIFO_Q(8) AND
NIDAQLogiccomp/N8/NIDAQLogiccomp/N8_D2)
OR (DIOD(0) AND NOT BUF_NIDAQLogiccomp/wen AND
NOT $OpTx$FX_SC$69)
OR (NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NIDAQLogiccomp/NIDAQSTATE_FFd2 AND NIDAQLogiccomp/StatusDatasig(8)));
FDCPE_DIOD1: FDCPE port map (DIOD(1),DIOD_D(1),clk,rst,'0');
DIOD_D(1) <= ((FIFO_Q(9) AND
NIDAQLogiccomp/N8/NIDAQLogiccomp/N8_D2)
OR (DIOD(1) AND NOT BUF_NIDAQLogiccomp/wen AND
NOT $OpTx$FX_SC$69)
OR (NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NIDAQLogiccomp/NIDAQSTATE_FFd2 AND NIDAQLogiccomp/StatusDatasig(9)));
FDCPE_DIOD2: FDCPE port map (DIOD(2),DIOD_D(2),clk,rst,'0');
DIOD_D(2) <= ((FIFO_Q(10) AND
NIDAQLogiccomp/N8/NIDAQLogiccomp/N8_D2)
OR (DIOD(2) AND NOT BUF_NIDAQLogiccomp/wen AND
NOT $OpTx$FX_SC$69)
OR (NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NIDAQLogiccomp/NIDAQSTATE_FFd2 AND NIDAQLogiccomp/StatusDatasig(10)));
FDCPE_DIOD3: FDCPE port map (DIOD(3),DIOD_D(3),clk,rst,'0');
DIOD_D(3) <= ((FIFO_Q(11) AND
NIDAQLogiccomp/N8/NIDAQLogiccomp/N8_D2)
OR (DIOD(3) AND NOT BUF_NIDAQLogiccomp/wen AND
NOT $OpTx$FX_SC$69)
OR (NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NIDAQLogiccomp/NIDAQSTATE_FFd2 AND NIDAQLogiccomp/StatusDatasig(11)));
FDCPE_DIOD4: FDCPE port map (DIOD(4),DIOD_D(4),clk,rst,'0');
DIOD_D(4) <= ((FIFO_Q(12) AND
NIDAQLogiccomp/N8/NIDAQLogiccomp/N8_D2)
OR (DIOD(4) AND NOT BUF_NIDAQLogiccomp/wen AND
NOT $OpTx$FX_SC$69)
OR (NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NIDAQLogiccomp/NIDAQSTATE_FFd2 AND NIDAQLogiccomp/StatusDatasig(12)));
FDCPE_DIOD5: FDCPE port map (DIOD(5),DIOD_D(5),clk,rst,'0');
DIOD_D(5) <= ((FIFO_Q(13) AND
NIDAQLogiccomp/N8/NIDAQLogiccomp/N8_D2)
OR (DIOD(5) AND NOT BUF_NIDAQLogiccomp/wen AND
NOT $OpTx$FX_SC$69)
OR (NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NIDAQLogiccomp/NIDAQSTATE_FFd2 AND NIDAQLogiccomp/StatusDatasig(13)));
FDCPE_DIOD6: FDCPE port map (DIOD(6),DIOD_D(6),clk,rst,'0');
DIOD_D(6) <= ((FIFO_Q(14) AND
NIDAQLogiccomp/N8/NIDAQLogiccomp/N8_D2)
OR (DIOD(6) AND NOT BUF_NIDAQLogiccomp/wen AND
NOT $OpTx$FX_SC$69)
OR (NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NIDAQLogiccomp/NIDAQSTATE_FFd2 AND NIDAQLogiccomp/StatusDatasig(14)));
FDCPE_DIOD7: FDCPE port map (DIOD(7),DIOD_D(7),clk,rst,'0');
DIOD_D(7) <= ((FIFO_Q(15) AND
NIDAQLogiccomp/N8/NIDAQLogiccomp/N8_D2)
OR (DIOD(7) AND NOT BUF_NIDAQLogiccomp/wen AND
NOT $OpTx$FX_SC$69)
OR (NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NIDAQLogiccomp/NIDAQSTATE_FFd2 AND NIDAQLogiccomp/StatusDatasig(15)));
FDCPE_EventReadoutsig: FDCPE port map (EventReadoutsig,EventReadoutsig_D,clk,rst,'0');
EventReadoutsig_D <= (NOT MainLogiccomp/MAINSTATE_FFd1 AND
NOT MainLogiccomp/MAINSTATE_FFd2 AND MainLogiccomp/MAINSTATE_FFd3);
FDCPE_EventReadysig: FDCPE port map (EventReadysig,'1',clk,NOT EventReadysig/EventReadysig_RSTF,'0',OpticalLogiccomp/RxDataLogiccomp/EventReadyCmd);
EventReadysig/EventReadysig_RSTF <= (NOT rst AND NOT EventReadoutsig);
FIFO_D(0) <= (
NOT OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd1 AND OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(0));
FIFO_D(1) <= (
NOT OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd1 AND OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(1));
FIFO_D(2) <= (
NOT OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd1 AND OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(2));
FIFO_D(3) <= (
NOT OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd1 AND OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(3));
FIFO_D(4) <= (
NOT OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd1 AND OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(4));
FIFO_D(5) <= (
NOT OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd1 AND OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(5));
FIFO_D(6) <= (
NOT OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd1 AND OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(6));
FIFO_D(7) <= (
NOT OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd1 AND OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(7));
FIFO_D(8) <= (
NOT OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd1 AND OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(8));
FIFO_D(9) <= (
NOT OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd1 AND OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(9));
FIFO_D(10) <= (
NOT OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd1 AND OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(10));
FIFO_D(11) <= (
NOT OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd1 AND OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(11));
FIFO_D(12) <= (
NOT OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd1 AND OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(12));
FIFO_D(13) <= (
NOT OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd1 AND OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(13));
FIFO_D(14) <= (
NOT OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd1 AND OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(14));
FIFO_D(15) <= (
NOT OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd1 AND OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(15));
FDCPE_MainLogiccomp/MAINSTATE_FFd1: FDCPE port map (MainLogiccomp/MAINSTATE_FFd1,MainLogiccomp/MAINSTATE_FFd1_D,clk,rst,'0');
MainLogiccomp/MAINSTATE_FFd1_D <= ((SPARE(10) AND SPARE(11) AND NOT SPARE(9) AND NOT SPARE(12) AND
NICMDsig(0) AND NOT NICMDsig(1) AND NICMDsig(2) AND NOT NICMDsig(3) AND
NOT MainLogiccomp/MAINSTATE_FFd1 AND NOT MainLogiccomp/MAINSTATE_FFd2 AND
NOT MainLogiccomp/MAINSTATE_FFd3 AND NICMD_Readysig)
OR (SPARE(10) AND SPARE(11) AND NOT SPARE(9) AND NOT SPARE(12) AND
NOT NICMDsig(0) AND NOT NICMDsig(1) AND NOT NICMDsig(2) AND NICMDsig(3) AND
NOT MainLogiccomp/MAINSTATE_FFd1 AND NOT MainLogiccomp/MAINSTATE_FFd2 AND
NOT MainLogiccomp/MAINSTATE_FFd3 AND NICMD_Readysig));
FDCPE_MainLogiccomp/MAINSTATE_FFd2: FDCPE port map (MainLogiccomp/MAINSTATE_FFd2,MainLogiccomp/MAINSTATE_FFd2_D,clk,rst,'0');
MainLogiccomp/MAINSTATE_FFd2_D <= ((NOT SPARE(10) AND NOT SPARE(11) AND NOT SPARE(12) AND
NOT MainLogiccomp/MAINSTATE_FFd1 AND NOT MainLogiccomp/MAINSTATE_FFd2 AND
NOT MainLogiccomp/MAINSTATE_FFd3 AND NICMD_Readysig)
OR (SPARE(10) AND SPARE(11) AND NOT SPARE(9) AND NOT SPARE(12) AND
NICMDsig(1) AND NICMDsig(2) AND NOT NICMDsig(3) AND
NOT MainLogiccomp/MAINSTATE_FFd1 AND NOT MainLogiccomp/MAINSTATE_FFd2 AND
NOT MainLogiccomp/MAINSTATE_FFd3 AND NICMD_Readysig));
FDCPE_MainLogiccomp/MAINSTATE_FFd3: FDCPE port map (MainLogiccomp/MAINSTATE_FFd3,MainLogiccomp/MAINSTATE_FFd3_D,clk,rst,'0');
MainLogiccomp/MAINSTATE_FFd3_D <= ((NOT SPARE(10) AND NOT SPARE(11) AND NOT SPARE(12) AND
NOT MainLogiccomp/MAINSTATE_FFd1 AND NOT MainLogiccomp/MAINSTATE_FFd2 AND
NOT MainLogiccomp/MAINSTATE_FFd3 AND NICMD_Readysig)
OR (SPARE(10) AND SPARE(11) AND NOT SPARE(9) AND NOT SPARE(12) AND
NICMDsig(0) AND NICMDsig(1) AND NICMDsig(2) AND NOT NICMDsig(3) AND
NOT MainLogiccomp/MAINSTATE_FFd1 AND NOT MainLogiccomp/MAINSTATE_FFd2 AND
NOT MainLogiccomp/MAINSTATE_FFd3 AND NICMD_Readysig)
OR (SPARE(10) AND SPARE(11) AND NOT SPARE(9) AND NOT SPARE(12) AND
NOT NICMDsig(0) AND NOT NICMDsig(1) AND NICMDsig(2) AND NOT NICMDsig(3) AND
NOT MainLogiccomp/MAINSTATE_FFd1 AND NOT MainLogiccomp/MAINSTATE_FFd2 AND
NOT MainLogiccomp/MAINSTATE_FFd3 AND NICMD_Readysig)
OR (SPARE(10) AND SPARE(11) AND NOT SPARE(9) AND NOT SPARE(12) AND
NOT NICMDsig(0) AND NOT NICMDsig(1) AND NOT NICMDsig(2) AND NICMDsig(3) AND
NOT MainLogiccomp/MAINSTATE_FFd1 AND NOT MainLogiccomp/MAINSTATE_FFd2 AND
NOT MainLogiccomp/MAINSTATE_FFd3 AND NICMD_Readysig));
FDCPE_NICMD_Argsig0: FDCPE port map (NICMD_Argsig(0),NIDAQLogiccomp/command_out(0),clk,rst,'0',NICMD_Argsig_CE(0));
NICMD_Argsig_CE(0) <= (NOT NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NIDAQLogiccomp/NIDAQSTATE_FFd3 AND NOT NIDAQLogiccomp/NIDAQSTATE_FFd2);
FDCPE_NICMD_Argsig1: FDCPE port map (NICMD_Argsig(1),NIDAQLogiccomp/command_out(1),clk,rst,'0',NICMD_Argsig_CE(1));
NICMD_Argsig_CE(1) <= (NOT NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NIDAQLogiccomp/NIDAQSTATE_FFd3 AND NOT NIDAQLogiccomp/NIDAQSTATE_FFd2);
FDCPE_NICMD_Argsig2: FDCPE port map (NICMD_Argsig(2),NIDAQLogiccomp/command_out(2),clk,rst,'0',NICMD_Argsig_CE(2));
NICMD_Argsig_CE(2) <= (NOT NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NIDAQLogiccomp/NIDAQSTATE_FFd3 AND NOT NIDAQLogiccomp/NIDAQSTATE_FFd2);
FDCPE_NICMD_Argsig3: FDCPE port map (NICMD_Argsig(3),NIDAQLogiccomp/command_out(3),clk,rst,'0',NICMD_Argsig_CE(3));
NICMD_Argsig_CE(3) <= (NOT NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NIDAQLogiccomp/NIDAQSTATE_FFd3 AND NOT NIDAQLogiccomp/NIDAQSTATE_FFd2);
FDCPE_NICMD_Argsig4: FDCPE port map (NICMD_Argsig(4),NIDAQLogiccomp/command_out(4),clk,rst,'0',NICMD_Argsig_CE(4));
NICMD_Argsig_CE(4) <= (NOT NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NIDAQLogiccomp/NIDAQSTATE_FFd3 AND NOT NIDAQLogiccomp/NIDAQSTATE_FFd2);
FDCPE_NICMD_Argsig5: FDCPE port map (NICMD_Argsig(5),NIDAQLogiccomp/command_out(5),clk,rst,'0',NICMD_Argsig_CE(5));
NICMD_Argsig_CE(5) <= (NOT NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NIDAQLogiccomp/NIDAQSTATE_FFd3 AND NOT NIDAQLogiccomp/NIDAQSTATE_FFd2);
FDCPE_NICMD_Argsig6: FDCPE port map (NICMD_Argsig(6),NIDAQLogiccomp/command_out(6),clk,rst,'0',NICMD_Argsig_CE(6));
NICMD_Argsig_CE(6) <= (NOT NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NIDAQLogiccomp/NIDAQSTATE_FFd3 AND NOT NIDAQLogiccomp/NIDAQSTATE_FFd2);
FDCPE_NICMD_Argsig7: FDCPE port map (NICMD_Argsig(7),NIDAQLogiccomp/command_out(7),clk,rst,'0',NICMD_Argsig_CE(7));
NICMD_Argsig_CE(7) <= (NOT NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NIDAQLogiccomp/NIDAQSTATE_FFd3 AND NOT NIDAQLogiccomp/NIDAQSTATE_FFd2);
FDCPE_NICMD_Readysig: FDCPE port map (NICMD_Readysig,NICMD_Readysig_D,clk,rst,'0');
NICMD_Readysig_D <= (NOT NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NIDAQLogiccomp/NIDAQSTATE_FFd3 AND NOT NIDAQLogiccomp/NIDAQSTATE_FFd2);
FDCPE_NICMDsig0: FDCPE port map (NICMDsig(0),NIDAQLogiccomp/command_out(8),clk,rst,'0',NICMDsig_CE(0));
NICMDsig_CE(0) <= (NOT NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NIDAQLogiccomp/NIDAQSTATE_FFd3 AND NOT NIDAQLogiccomp/NIDAQSTATE_FFd2);
FDCPE_NICMDsig1: FDCPE port map (NICMDsig(1),NIDAQLogiccomp/command_out(9),clk,rst,'0',NICMDsig_CE(1));
NICMDsig_CE(1) <= (NOT NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NIDAQLogiccomp/NIDAQSTATE_FFd3 AND NOT NIDAQLogiccomp/NIDAQSTATE_FFd2);
FDCPE_NICMDsig2: FDCPE port map (NICMDsig(2),NIDAQLogiccomp/command_out(10),clk,rst,'0',NICMDsig_CE(2));
NICMDsig_CE(2) <= (NOT NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NIDAQLogiccomp/NIDAQSTATE_FFd3 AND NOT NIDAQLogiccomp/NIDAQSTATE_FFd2);
FDCPE_NICMDsig3: FDCPE port map (NICMDsig(3),NIDAQLogiccomp/command_out(11),clk,rst,'0',NICMDsig_CE(3));
NICMDsig_CE(3) <= (NOT NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NIDAQLogiccomp/NIDAQSTATE_FFd3 AND NOT NIDAQLogiccomp/NIDAQSTATE_FFd2);
NIDAQLogiccomp/Msub__addsub0000__or0001/NIDAQLogiccomp/Msub__addsub0000__or0001_D2 <= (NOT NIDAQLogiccomp/NumOfWordsSentCounter(0) AND
NOT NIDAQLogiccomp/NumOfWordsSentCounter(1) AND NOT NIDAQLogiccomp/NumOfWordsSentCounter(2));
NIDAQLogiccomp/Msub__addsub0000__or0003/NIDAQLogiccomp/Msub__addsub0000__or0003_D2 <= (NOT NIDAQLogiccomp/NumOfWordsSentCounter(3) AND
NOT NIDAQLogiccomp/NumOfWordsSentCounter(4) AND
NIDAQLogiccomp/Msub__addsub0000__or0001/NIDAQLogiccomp/Msub__addsub0000__or0001_D2);
NIDAQLogiccomp/N8/NIDAQLogiccomp/N8_D2 <= ((NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NOT NIDAQLogiccomp/NIDAQSTATE_FFd3 AND NOT NIDAQLogiccomp/NIDAQSTATE_FFd2)
OR (NOT NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NOT NIDAQLogiccomp/NIDAQSTATE_FFd3 AND NIDAQLogiccomp/NIDAQSTATE_FFd2));
FDCPE_NIDAQLogiccomp/NIDAQSTATE_FFd1: FDCPE port map (NIDAQLogiccomp/NIDAQSTATE_FFd1,NIDAQLogiccomp/NIDAQSTATE_FFd1_D,clk,rst,'0');
NIDAQLogiccomp/NIDAQSTATE_FFd1_D <= ((BUF_NIDAQLogiccomp/wen)
OR ($OpTx$FX_SC$69)
OR (NOT NIDAQLogiccomp/SendingPackageFlag AND
NOT NIDAQLogiccomp/NIDAQSTATE_FFd3 AND NOT NIDAQLogiccomp/cav AND SendDataCmdsig)
OR (NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NIDAQLogiccomp/NIDAQSTATE_FFd3 AND NOT NIDAQLogiccomp/Readtimeout AND NOT NIDAQLogiccomp/wdone));
FDCPE_NIDAQLogiccomp/NIDAQSTATE_FFd2: FDCPE port map (NIDAQLogiccomp/NIDAQSTATE_FFd2,NIDAQLogiccomp/NIDAQSTATE_FFd2_D,clk,rst,'0');
NIDAQLogiccomp/NIDAQSTATE_FFd2_D <= ((NIDAQLogiccomp/NIDAQSTATE_FFd3 AND
NIDAQLogiccomp/NIDAQSTATE_FFd2)
OR (NIDAQLogiccomp/SendingPackageFlag AND
NOT NIDAQLogiccomp/NIDAQSTATE_FFd1 AND NOT NIDAQLogiccomp/NIDAQSTATE_FFd3 AND
NOT NIDAQLogiccomp/NIDAQSTATE_FFd2 AND NOT NIDAQLogiccomp/cav)
OR (NOT NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NOT NIDAQLogiccomp/NIDAQSTATE_FFd3 AND NOT NIDAQLogiccomp/NIDAQSTATE_FFd2 AND
NOT NIDAQLogiccomp/cav AND SendDataCmdsig));
FTCPE_NIDAQLogiccomp/NIDAQSTATE_FFd3: FTCPE port map (NIDAQLogiccomp/NIDAQSTATE_FFd3,NIDAQLogiccomp/NIDAQSTATE_FFd3_T,clk,rst,'0');
NIDAQLogiccomp/NIDAQSTATE_FFd3_T <= ((NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NIDAQLogiccomp/NIDAQSTATE_FFd3 AND NIDAQLogiccomp/NIDAQSTATE_FFd2)
OR (NOT NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NOT NIDAQLogiccomp/NIDAQSTATE_FFd3 AND NIDAQLogiccomp/NIDAQSTATE_FFd2)
OR (NOT NIDAQLogiccomp/SendingPackageFlag AND
NOT NIDAQLogiccomp/NIDAQSTATE_FFd1 AND NOT NIDAQLogiccomp/NIDAQSTATE_FFd3 AND
NOT NIDAQLogiccomp/cav)
OR (NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NIDAQLogiccomp/NIDAQSTATE_FFd3 AND NOT NIDAQLogiccomp/Readtimeout AND NOT NIDAQLogiccomp/wdone));
FDCPE_NIDAQLogiccomp/NI_Interfacecomp/ack1_sync0: FDCPE port map (NIDAQLogiccomp/NI_Interfacecomp/ack1_sync(0),ACK1,NOT clk,rst,'0');
FDCPE_NIDAQLogiccomp/NI_Interfacecomp/ack1_sync1: FDCPE port map (NIDAQLogiccomp/NI_Interfacecomp/ack1_sync(1),NIDAQLogiccomp/NI_Interfacecomp/ack1_sync(0),NOT clk,rst,'0');
FDCPE_NIDAQLogiccomp/NI_Interfacecomp/ack1_sync2: FDCPE port map (NIDAQLogiccomp/NI_Interfacecomp/ack1_sync(2),NIDAQLogiccomp/NI_Interfacecomp/ack1_sync(1),NOT clk,rst,'0');
FDCPE_NIDAQLogiccomp/NI_Interfacecomp/ack2_sync: FDCPE port map (NIDAQLogiccomp/NI_Interfacecomp/ack2_sync,ACK2,NOT clk,rst,'0');
FDCPE_NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd1: FDCPE port map (NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd1,NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd1_D,clk,rst,'0');
NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd1_D <= (NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd3 AND
NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd2 AND NOT NIDAQLogiccomp/NI_Interfacecomp/ack2_sync);
FDCPE_NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd2: FDCPE port map (NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd2,NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd2_D,clk,rst,'0');
NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd2_D <= ((NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd3 AND
NIDAQLogiccomp/NI_Interfacecomp/ack2_sync)
OR (NOT NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd3 AND
NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd2));
FDCPE_NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd3: FDCPE port map (NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd3,NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd3_D,clk,rst,'0');
NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd3_D <= ((NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd3 AND
NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd2 AND NIDAQLogiccomp/NI_Interfacecomp/ack2_sync)
OR (NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd3 AND
NOT NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd2 AND NOT NIDAQLogiccomp/NI_Interfacecomp/ack2_sync)
OR (NOT NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd3 AND
NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd2 AND NOT NIDAQLogiccomp/NI_Interfacecomp/req2_cnt(0) AND
NOT NIDAQLogiccomp/NI_Interfacecomp/req2_cnt(1))
OR (NOT NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd3 AND
NOT NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd2 AND NOT NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd1 AND
NIDAQLogiccomp/wen));
FDCPE_NIDAQLogiccomp/NI_Interfacecomp/req2_cnt0: FDCPE port map (NIDAQLogiccomp/NI_Interfacecomp/req2_cnt(0),NIDAQLogiccomp/NI_Interfacecomp/req2_cnt_D(0),clk,rst,'0');
NIDAQLogiccomp/NI_Interfacecomp/req2_cnt_D(0) <= (NOT NIDAQLogiccomp/NI_Interfacecomp/req2_cnt(0) AND
NOT NIDAQLogiccomp/NI_Interfacecomp/req2_cnt_ld);
FDCPE_NIDAQLogiccomp/NI_Interfacecomp/req2_cnt1: FDCPE port map (NIDAQLogiccomp/NI_Interfacecomp/req2_cnt(1),NIDAQLogiccomp/NI_Interfacecomp/req2_cnt_D(1),clk,rst,'0');
NIDAQLogiccomp/NI_Interfacecomp/req2_cnt_D(1) <= ((NIDAQLogiccomp/NI_Interfacecomp/req2_cnt(0) AND
NOT NIDAQLogiccomp/NI_Interfacecomp/req2_cnt(1) AND NOT NIDAQLogiccomp/NI_Interfacecomp/req2_cnt_ld)
OR (NOT NIDAQLogiccomp/NI_Interfacecomp/req2_cnt(0) AND
NIDAQLogiccomp/NI_Interfacecomp/req2_cnt(1) AND NOT NIDAQLogiccomp/NI_Interfacecomp/req2_cnt_ld));
FDCPE_NIDAQLogiccomp/NI_Interfacecomp/req2_cnt_ld: FDCPE port map (NIDAQLogiccomp/NI_Interfacecomp/req2_cnt_ld,NOT NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd2,clk,'0',rst);
FDCPE_NIDAQLogiccomp/NumOfWordsSentCounter0: FDCPE port map (NIDAQLogiccomp/NumOfWordsSentCounter(0),NIDAQLogiccomp/NumOfWordsSentCounter_D(0),clk,rst,'0');
NIDAQLogiccomp/NumOfWordsSentCounter_D(0) <= ((NIDAQLogiccomp/SendingPackageFlag AND
NIDAQLogiccomp/NumOfWordsSentCounter(0) AND NOT NIDAQLogiccomp/wen)
OR (NIDAQLogiccomp/SendingPackageFlag AND
NOT NIDAQLogiccomp/NumOfWordsSentCounter(0) AND NIDAQLogiccomp/wen));
FTCPE_NIDAQLogiccomp/NumOfWordsSentCounter1: FTCPE port map (NIDAQLogiccomp/NumOfWordsSentCounter(1),NIDAQLogiccomp/NumOfWordsSentCounter_T(1),clk,rst,'0');
NIDAQLogiccomp/NumOfWordsSentCounter_T(1) <= ((NOT NIDAQLogiccomp/SendingPackageFlag AND
NIDAQLogiccomp/NumOfWordsSentCounter(1))
OR (NIDAQLogiccomp/SendingPackageFlag AND
NOT NIDAQLogiccomp/NumOfWordsSentCounter(0) AND NIDAQLogiccomp/wen));
FTCPE_NIDAQLogiccomp/NumOfWordsSentCounter2: FTCPE port map (NIDAQLogiccomp/NumOfWordsSentCounter(2),NIDAQLogiccomp/NumOfWordsSentCounter_T(2),clk,rst,'0');
NIDAQLogiccomp/NumOfWordsSentCounter_T(2) <= ((NOT NIDAQLogiccomp/SendingPackageFlag AND
NIDAQLogiccomp/NumOfWordsSentCounter(2))
OR (NIDAQLogiccomp/SendingPackageFlag AND
NOT NIDAQLogiccomp/NumOfWordsSentCounter(0) AND NOT NIDAQLogiccomp/NumOfWordsSentCounter(1) AND
NIDAQLogiccomp/wen));
FTCPE_NIDAQLogiccomp/NumOfWordsSentCounter3: FTCPE port map (NIDAQLogiccomp/NumOfWordsSentCounter(3),NIDAQLogiccomp/NumOfWordsSentCounter_T(3),clk,rst,'0');
NIDAQLogiccomp/NumOfWordsSentCounter_T(3) <= ((NOT NIDAQLogiccomp/SendingPackageFlag AND
NIDAQLogiccomp/NumOfWordsSentCounter(3))
OR (NIDAQLogiccomp/SendingPackageFlag AND
NIDAQLogiccomp/wen AND
NIDAQLogiccomp/Msub__addsub0000__or0001/NIDAQLogiccomp/Msub__addsub0000__or0001_D2));
FTCPE_NIDAQLogiccomp/NumOfWordsSentCounter4: FTCPE port map (NIDAQLogiccomp/NumOfWordsSentCounter(4),NIDAQLogiccomp/NumOfWordsSentCounter_T(4),clk,'0',rst);
NIDAQLogiccomp/NumOfWordsSentCounter_T(4) <= ((NOT NIDAQLogiccomp/SendingPackageFlag AND
NOT NIDAQLogiccomp/NumOfWordsSentCounter(4))
OR (NIDAQLogiccomp/SendingPackageFlag AND
NOT NIDAQLogiccomp/NumOfWordsSentCounter(3) AND NIDAQLogiccomp/wen AND
NIDAQLogiccomp/Msub__addsub0000__or0001/NIDAQLogiccomp/Msub__addsub0000__or0001_D2));
FTCPE_NIDAQLogiccomp/NumOfWordsSentCounter5: FTCPE port map (NIDAQLogiccomp/NumOfWordsSentCounter(5),NIDAQLogiccomp/NumOfWordsSentCounter_T(5),clk,rst,'0');
NIDAQLogiccomp/NumOfWordsSentCounter_T(5) <= ((NOT NIDAQLogiccomp/SendingPackageFlag AND
NIDAQLogiccomp/NumOfWordsSentCounter(5))
OR (NIDAQLogiccomp/SendingPackageFlag AND
NIDAQLogiccomp/wen AND
NIDAQLogiccomp/Msub__addsub0000__or0003/NIDAQLogiccomp/Msub__addsub0000__or0003_D2));
FTCPE_NIDAQLogiccomp/NumOfWordsSentCounter6: FTCPE port map (NIDAQLogiccomp/NumOfWordsSentCounter(6),NIDAQLogiccomp/NumOfWordsSentCounter_T(6),clk,rst,'0');
NIDAQLogiccomp/NumOfWordsSentCounter_T(6) <= ((NOT NIDAQLogiccomp/SendingPackageFlag AND
NIDAQLogiccomp/NumOfWordsSentCounter(6))
OR (NIDAQLogiccomp/SendingPackageFlag AND
NOT NIDAQLogiccomp/NumOfWordsSentCounter(5) AND NIDAQLogiccomp/wen AND
NIDAQLogiccomp/Msub__addsub0000__or0003/NIDAQLogiccomp/Msub__addsub0000__or0003_D2));
FTCPE_NIDAQLogiccomp/NumOfWordsSentCounter7: FTCPE port map (NIDAQLogiccomp/NumOfWordsSentCounter(7),NIDAQLogiccomp/NumOfWordsSentCounter_T(7),clk,rst,'0');
NIDAQLogiccomp/NumOfWordsSentCounter_T(7) <= ((NOT NIDAQLogiccomp/SendingPackageFlag AND
NIDAQLogiccomp/NumOfWordsSentCounter(7))
OR (NIDAQLogiccomp/SendingPackageFlag AND
NOT NIDAQLogiccomp/NumOfWordsSentCounter(5) AND NOT NIDAQLogiccomp/NumOfWordsSentCounter(6) AND
NIDAQLogiccomp/wen AND
NIDAQLogiccomp/Msub__addsub0000__or0003/NIDAQLogiccomp/Msub__addsub0000__or0003_D2));
FDCPE_NIDAQLogiccomp/Readtimeout: FDCPE port map (NIDAQLogiccomp/Readtimeout,NIDAQLogiccomp/Readtimeout_D,clk,rst,'0');
NIDAQLogiccomp/Readtimeout_D <= (NIDAQLogiccomp/Readtimeouten AND
NOT NIDAQLogiccomp/Readtimeoutcounter_0_0 AND NOT NIDAQLogiccomp/Readtimeoutcounter_0_1 AND
NOT NIDAQLogiccomp/Readtimeoutcounter_0_10 AND NOT NIDAQLogiccomp/Readtimeoutcounter_0_11 AND
NIDAQLogiccomp/Readtimeoutcounter_0_12 AND NIDAQLogiccomp/Readtimeoutcounter_0_13 AND
NIDAQLogiccomp/Readtimeoutcounter_0_14 AND NOT NIDAQLogiccomp/Readtimeoutcounter_0_2 AND
NOT NIDAQLogiccomp/Readtimeoutcounter_0_3 AND NOT NIDAQLogiccomp/Readtimeoutcounter_0_4 AND
NOT NIDAQLogiccomp/Readtimeoutcounter_0_5 AND NOT NIDAQLogiccomp/Readtimeoutcounter_0_6 AND
NIDAQLogiccomp/Readtimeoutcounter_0_7 AND NOT NIDAQLogiccomp/Readtimeoutcounter_0_8 AND
NOT NIDAQLogiccomp/Readtimeoutcounter_0_9 AND NIDAQLogiccomp/Readtimeoutcounter_0_15);
FDCPE_NIDAQLogiccomp/Readtimeoutcounter_0_0: FDCPE port map (NIDAQLogiccomp/Readtimeoutcounter_0_0,NIDAQLogiccomp/Readtimeoutcounter_0_0_D,clk,rst,'0');
NIDAQLogiccomp/Readtimeoutcounter_0_0_D <= (NIDAQLogiccomp/Readtimeouten AND
NOT NIDAQLogiccomp/Readtimeoutcounter_0_0);
FDCPE_NIDAQLogiccomp/Readtimeoutcounter_0_1: FDCPE port map (NIDAQLogiccomp/Readtimeoutcounter_0_1,NIDAQLogiccomp/Readtimeoutcounter_0_1_D,clk,rst,'0');
NIDAQLogiccomp/Readtimeoutcounter_0_1_D <= ((NIDAQLogiccomp/Readtimeouten AND
NIDAQLogiccomp/Readtimeoutcounter_0_0 AND NOT NIDAQLogiccomp/Readtimeoutcounter_0_1)
OR (NIDAQLogiccomp/Readtimeouten AND
NOT NIDAQLogiccomp/Readtimeoutcounter_0_0 AND NIDAQLogiccomp/Readtimeoutcounter_0_1));
FDCPE_NIDAQLogiccomp/Readtimeoutcounter_0_10: FDCPE port map (NIDAQLogiccomp/Readtimeoutcounter_0_10,NIDAQLogiccomp/Readtimeoutcounter_0_10_D,clk,rst,'0');
NIDAQLogiccomp/Readtimeoutcounter_0_10_D <= ((NIDAQLogiccomp/Readtimeouten AND
NIDAQLogiccomp/Readtimeoutcounter_0_10 AND
NOT NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0008/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0008_D2)
OR (NIDAQLogiccomp/Readtimeouten AND
NOT NIDAQLogiccomp/Readtimeoutcounter_0_10 AND
NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0008/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0008_D2));
FDCPE_NIDAQLogiccomp/Readtimeoutcounter_0_11: FDCPE port map (NIDAQLogiccomp/Readtimeoutcounter_0_11,NIDAQLogiccomp/Readtimeoutcounter_0_11_D,clk,rst,'0');
NIDAQLogiccomp/Readtimeoutcounter_0_11_D <= ((NIDAQLogiccomp/Readtimeouten AND
NIDAQLogiccomp/Readtimeoutcounter_0_11 AND
NOT NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0010/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0010_D2)
OR (NIDAQLogiccomp/Readtimeouten AND
NIDAQLogiccomp/Readtimeoutcounter_0_10 AND
NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0008/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0008_D2 AND
NOT NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0010/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0010_D2));
FDCPE_NIDAQLogiccomp/Readtimeoutcounter_0_12: FDCPE port map (NIDAQLogiccomp/Readtimeoutcounter_0_12,NIDAQLogiccomp/Readtimeoutcounter_0_12_D,clk,rst,'0');
NIDAQLogiccomp/Readtimeoutcounter_0_12_D <= ((NIDAQLogiccomp/Readtimeouten AND
NIDAQLogiccomp/Readtimeoutcounter_0_12 AND
NOT NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0010/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0010_D2)
OR (NIDAQLogiccomp/Readtimeouten AND
NOT NIDAQLogiccomp/Readtimeoutcounter_0_12 AND
NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0010/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0010_D2));
FTCPE_NIDAQLogiccomp/Readtimeoutcounter_0_13: FTCPE port map (NIDAQLogiccomp/Readtimeoutcounter_0_13,NIDAQLogiccomp/Readtimeoutcounter_0_13_T,clk,rst,'0');
NIDAQLogiccomp/Readtimeoutcounter_0_13_T <= ((NOT NIDAQLogiccomp/Readtimeouten AND
NIDAQLogiccomp/Readtimeoutcounter_0_13)
OR (NIDAQLogiccomp/Readtimeouten AND
NIDAQLogiccomp/Readtimeoutcounter_0_12 AND
NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0010/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0010_D2));
FDCPE_NIDAQLogiccomp/Readtimeoutcounter_0_14: FDCPE port map (NIDAQLogiccomp/Readtimeoutcounter_0_14,NIDAQLogiccomp/Readtimeoutcounter_0_14_D,clk,rst,'0');
NIDAQLogiccomp/Readtimeoutcounter_0_14_D <= ((NIDAQLogiccomp/Readtimeouten AND
NIDAQLogiccomp/Readtimeoutcounter_0_14 AND
NOT NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0013/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0013_D2)
OR (NIDAQLogiccomp/Readtimeouten AND
NIDAQLogiccomp/Readtimeoutcounter_0_12 AND NIDAQLogiccomp/Readtimeoutcounter_0_13 AND
NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0010/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0010_D2 AND
NOT NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0013/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0013_D2));
FDCPE_NIDAQLogiccomp/Readtimeoutcounter_0_15: FDCPE port map (NIDAQLogiccomp/Readtimeoutcounter_0_15,NIDAQLogiccomp/Readtimeoutcounter_0_15_D,clk,rst,'0');
NIDAQLogiccomp/Readtimeoutcounter_0_15_D <= ((NIDAQLogiccomp/Readtimeouten AND
NIDAQLogiccomp/Readtimeoutcounter_0_15 AND
NOT NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0013/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0013_D2)
OR (NIDAQLogiccomp/Readtimeouten AND
NOT NIDAQLogiccomp/Readtimeoutcounter_0_15 AND
NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0013/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0013_D2));
FTCPE_NIDAQLogiccomp/Readtimeoutcounter_0_2: FTCPE port map (NIDAQLogiccomp/Readtimeoutcounter_0_2,NIDAQLogiccomp/Readtimeoutcounter_0_2_T,clk,rst,'0');
NIDAQLogiccomp/Readtimeoutcounter_0_2_T <= ((NOT NIDAQLogiccomp/Readtimeouten AND
NIDAQLogiccomp/Readtimeoutcounter_0_2)
OR (NIDAQLogiccomp/Readtimeouten AND
NIDAQLogiccomp/Readtimeoutcounter_0_0 AND NIDAQLogiccomp/Readtimeoutcounter_0_1));
FTCPE_NIDAQLogiccomp/Readtimeoutcounter_0_3: FTCPE port map (NIDAQLogiccomp/Readtimeoutcounter_0_3,NIDAQLogiccomp/Readtimeoutcounter_0_3_T,clk,rst,'0');
NIDAQLogiccomp/Readtimeoutcounter_0_3_T <= ((NOT NIDAQLogiccomp/Readtimeouten AND
NIDAQLogiccomp/Readtimeoutcounter_0_3)
OR (NIDAQLogiccomp/Readtimeouten AND
NIDAQLogiccomp/Readtimeoutcounter_0_0 AND NIDAQLogiccomp/Readtimeoutcounter_0_1 AND
NIDAQLogiccomp/Readtimeoutcounter_0_2));
FDCPE_NIDAQLogiccomp/Readtimeoutcounter_0_4: FDCPE port map (NIDAQLogiccomp/Readtimeoutcounter_0_4,NIDAQLogiccomp/Readtimeoutcounter_0_4_D,clk,rst,'0');
NIDAQLogiccomp/Readtimeoutcounter_0_4_D <= ((NIDAQLogiccomp/Readtimeouten AND
NIDAQLogiccomp/Readtimeoutcounter_0_4 AND
NOT NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0003/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0003_D2)
OR (NIDAQLogiccomp/Readtimeouten AND
NIDAQLogiccomp/Readtimeoutcounter_0_0 AND NIDAQLogiccomp/Readtimeoutcounter_0_1 AND
NIDAQLogiccomp/Readtimeoutcounter_0_2 AND NIDAQLogiccomp/Readtimeoutcounter_0_3 AND
NOT NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0003/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0003_D2));
FDCPE_NIDAQLogiccomp/Readtimeoutcounter_0_5: FDCPE port map (NIDAQLogiccomp/Readtimeoutcounter_0_5,NIDAQLogiccomp/Readtimeoutcounter_0_5_D,clk,rst,'0');
NIDAQLogiccomp/Readtimeoutcounter_0_5_D <= ((NIDAQLogiccomp/Readtimeouten AND
NIDAQLogiccomp/Readtimeoutcounter_0_5 AND
NOT NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0003/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0003_D2)
OR (NIDAQLogiccomp/Readtimeouten AND
NOT NIDAQLogiccomp/Readtimeoutcounter_0_5 AND
NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0003/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0003_D2));
FDCPE_NIDAQLogiccomp/Readtimeoutcounter_0_6: FDCPE port map (NIDAQLogiccomp/Readtimeoutcounter_0_6,NIDAQLogiccomp/Readtimeoutcounter_0_6_D,clk,rst,'0');
NIDAQLogiccomp/Readtimeoutcounter_0_6_D <= ((NIDAQLogiccomp/Readtimeouten AND
NIDAQLogiccomp/Readtimeoutcounter_0_6 AND
NOT NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0005/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0005_D2)
OR (NIDAQLogiccomp/Readtimeouten AND
NIDAQLogiccomp/Readtimeoutcounter_0_5 AND
NOT NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0005/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0005_D2 AND
NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0003/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0003_D2));
FDCPE_NIDAQLogiccomp/Readtimeoutcounter_0_7: FDCPE port map (NIDAQLogiccomp/Readtimeoutcounter_0_7,NIDAQLogiccomp/Readtimeoutcounter_0_7_D,clk,rst,'0');
NIDAQLogiccomp/Readtimeoutcounter_0_7_D <= ((NIDAQLogiccomp/Readtimeouten AND
NIDAQLogiccomp/Readtimeoutcounter_0_7 AND
NOT NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0005/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0005_D2)
OR (NIDAQLogiccomp/Readtimeouten AND
NOT NIDAQLogiccomp/Readtimeoutcounter_0_7 AND
NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0005/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0005_D2));
FTCPE_NIDAQLogiccomp/Readtimeoutcounter_0_8: FTCPE port map (NIDAQLogiccomp/Readtimeoutcounter_0_8,NIDAQLogiccomp/Readtimeoutcounter_0_8_T,clk,rst,'0');
NIDAQLogiccomp/Readtimeoutcounter_0_8_T <= ((NOT NIDAQLogiccomp/Readtimeouten AND
NIDAQLogiccomp/Readtimeoutcounter_0_8)
OR (NIDAQLogiccomp/Readtimeouten AND
NIDAQLogiccomp/Readtimeoutcounter_0_7 AND
NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0005/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0005_D2));
FDCPE_NIDAQLogiccomp/Readtimeoutcounter_0_9: FDCPE port map (NIDAQLogiccomp/Readtimeoutcounter_0_9,NIDAQLogiccomp/Readtimeoutcounter_0_9_D,clk,rst,'0');
NIDAQLogiccomp/Readtimeoutcounter_0_9_D <= ((NIDAQLogiccomp/Readtimeouten AND
NIDAQLogiccomp/Readtimeoutcounter_0_9 AND
NOT NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0008/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0008_D2)
OR (NIDAQLogiccomp/Readtimeouten AND
NIDAQLogiccomp/Readtimeoutcounter_0_7 AND NIDAQLogiccomp/Readtimeoutcounter_0_8 AND
NOT NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0008/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0008_D2 AND
NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0005/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0005_D2));
NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0003/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0003_D2 <= (NIDAQLogiccomp/Readtimeoutcounter_0_0 AND
NIDAQLogiccomp/Readtimeoutcounter_0_1 AND NIDAQLogiccomp/Readtimeoutcounter_0_2 AND
NIDAQLogiccomp/Readtimeoutcounter_0_3 AND NIDAQLogiccomp/Readtimeoutcounter_0_4);
NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0005/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0005_D2 <= (NIDAQLogiccomp/Readtimeoutcounter_0_5 AND
NIDAQLogiccomp/Readtimeoutcounter_0_6 AND
NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0003/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0003_D2);
NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0008/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0008_D2 <= (NIDAQLogiccomp/Readtimeoutcounter_0_7 AND
NIDAQLogiccomp/Readtimeoutcounter_0_8 AND NIDAQLogiccomp/Readtimeoutcounter_0_9 AND
NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0005/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0005_D2);
NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0010/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0010_D2 <= (NIDAQLogiccomp/Readtimeoutcounter_0_10 AND
NIDAQLogiccomp/Readtimeoutcounter_0_11 AND
NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0008/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0008_D2);
NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0013/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0013_D2 <= (NIDAQLogiccomp/Readtimeoutcounter_0_12 AND
NIDAQLogiccomp/Readtimeoutcounter_0_13 AND NIDAQLogiccomp/Readtimeoutcounter_0_14 AND
NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0010/NIDAQLogiccomp/Readtimeoutcounter_Madd__add0000__and0010_D2);
FDCPE_NIDAQLogiccomp/Readtimeouten: FDCPE port map (NIDAQLogiccomp/Readtimeouten,NIDAQLogiccomp/Readtimeouten_D,clk,rst,'0');
NIDAQLogiccomp/Readtimeouten_D <= (NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NIDAQLogiccomp/NIDAQSTATE_FFd3);
FTCPE_NIDAQLogiccomp/SendingPackageFlag: FTCPE port map (NIDAQLogiccomp/SendingPackageFlag,NIDAQLogiccomp/SendingPackageFlag_T,clk,rst,'0');
NIDAQLogiccomp/SendingPackageFlag_T <= ((NOT NIDAQLogiccomp/SendingPackageFlag AND
EventReadoutsig AND EFn)
OR (NIDAQLogiccomp/SendingPackageFlag AND
NOT NIDAQLogiccomp/NumOfWordsSentCounter(0) AND NOT NIDAQLogiccomp/NumOfWordsSentCounter(1) AND
NOT NIDAQLogiccomp/NumOfWordsSentCounter(2) AND NOT NIDAQLogiccomp/NumOfWordsSentCounter(3) AND
NOT NIDAQLogiccomp/NumOfWordsSentCounter(4) AND NOT NIDAQLogiccomp/NumOfWordsSentCounter(5) AND
NOT NIDAQLogiccomp/NumOfWordsSentCounter(6) AND NOT NIDAQLogiccomp/NumOfWordsSentCounter(7) AND
NOT EventReadoutsig)
OR (NIDAQLogiccomp/SendingPackageFlag AND
NOT NIDAQLogiccomp/NumOfWordsSentCounter(0) AND NOT NIDAQLogiccomp/NumOfWordsSentCounter(1) AND
NOT NIDAQLogiccomp/NumOfWordsSentCounter(2) AND NOT NIDAQLogiccomp/NumOfWordsSentCounter(3) AND
NOT NIDAQLogiccomp/NumOfWordsSentCounter(4) AND NOT NIDAQLogiccomp/NumOfWordsSentCounter(5) AND
NOT NIDAQLogiccomp/NumOfWordsSentCounter(6) AND NOT NIDAQLogiccomp/NumOfWordsSentCounter(7) AND NOT EFn));
FDCPE_NIDAQLogiccomp/StatusDatasig0: FDCPE port map (NIDAQLogiccomp/StatusDatasig(0),StatusDatasig(0),clk,'0','0',NOT rst);
FDCPE_NIDAQLogiccomp/StatusDatasig1: FDCPE port map (NIDAQLogiccomp/StatusDatasig(1),StatusDatasig(1),clk,'0','0',NOT rst);
FDCPE_NIDAQLogiccomp/StatusDatasig2: FDCPE port map (NIDAQLogiccomp/StatusDatasig(2),StatusDatasig(2),clk,'0','0',NOT rst);
FDCPE_NIDAQLogiccomp/StatusDatasig3: FDCPE port map (NIDAQLogiccomp/StatusDatasig(3),StatusDatasig(3),clk,'0','0',NOT rst);
FDCPE_NIDAQLogiccomp/StatusDatasig4: FDCPE port map (NIDAQLogiccomp/StatusDatasig(4),StatusDatasig(4),clk,'0','0',NOT rst);
FDCPE_NIDAQLogiccomp/StatusDatasig5: FDCPE port map (NIDAQLogiccomp/StatusDatasig(5),StatusDatasig(5),clk,'0','0',NOT rst);
FDCPE_NIDAQLogiccomp/StatusDatasig6: FDCPE port map (NIDAQLogiccomp/StatusDatasig(6),StatusDatasig(6),clk,'0','0',NOT rst);
FDCPE_NIDAQLogiccomp/StatusDatasig7: FDCPE port map (NIDAQLogiccomp/StatusDatasig(7),StatusDatasig(7),clk,'0','0',NOT rst);
FDCPE_NIDAQLogiccomp/StatusDatasig8: FDCPE port map (NIDAQLogiccomp/StatusDatasig(8),StatusDatasig(8),clk,'0','0',NOT rst);
FDCPE_NIDAQLogiccomp/StatusDatasig9: FDCPE port map (NIDAQLogiccomp/StatusDatasig(9),StatusDatasig(9),clk,'0','0',NOT rst);
FDCPE_NIDAQLogiccomp/StatusDatasig10: FDCPE port map (NIDAQLogiccomp/StatusDatasig(10),StatusDatasig(10),clk,'0','0',NOT rst);
FDCPE_NIDAQLogiccomp/StatusDatasig11: FDCPE port map (NIDAQLogiccomp/StatusDatasig(11),StatusDatasig(11),clk,'0','0',NOT rst);
FDCPE_NIDAQLogiccomp/StatusDatasig12: FDCPE port map (NIDAQLogiccomp/StatusDatasig(12),StatusDatasig(12),clk,'0','0',NOT rst);
FDCPE_NIDAQLogiccomp/StatusDatasig13: FDCPE port map (NIDAQLogiccomp/StatusDatasig(13),StatusDatasig(13),clk,'0','0',NOT rst);
FDCPE_NIDAQLogiccomp/StatusDatasig14: FDCPE port map (NIDAQLogiccomp/StatusDatasig(14),StatusDatasig(14),clk,'0','0',NOT rst);
FDCPE_NIDAQLogiccomp/StatusDatasig15: FDCPE port map (NIDAQLogiccomp/StatusDatasig(15),StatusDatasig(15),clk,'0','0',NOT rst);
FDCPE_NIDAQLogiccomp/cav: FDCPE port map (NIDAQLogiccomp/cav,NIDAQLogiccomp/cav_D,NOT clk,rst,'0');
NIDAQLogiccomp/cav_D <= (NOT NIDAQLogiccomp/NI_Interfacecomp/ack1_sync(1) AND
NIDAQLogiccomp/NI_Interfacecomp/ack1_sync(2));
FDCPE_NIDAQLogiccomp/command_out0: FDCPE port map (NIDAQLogiccomp/command_out(0),DIOB(0),clk,rst,'0');
FDCPE_NIDAQLogiccomp/command_out1: FDCPE port map (NIDAQLogiccomp/command_out(1),DIOB(1),clk,rst,'0');
FDCPE_NIDAQLogiccomp/command_out2: FDCPE port map (NIDAQLogiccomp/command_out(2),DIOB(2),clk,rst,'0');
FDCPE_NIDAQLogiccomp/command_out3: FDCPE port map (NIDAQLogiccomp/command_out(3),DIOB(3),clk,rst,'0');
FDCPE_NIDAQLogiccomp/command_out4: FDCPE port map (NIDAQLogiccomp/command_out(4),DIOB(4),clk,rst,'0');
FDCPE_NIDAQLogiccomp/command_out5: FDCPE port map (NIDAQLogiccomp/command_out(5),DIOB(5),clk,rst,'0');
FDCPE_NIDAQLogiccomp/command_out6: FDCPE port map (NIDAQLogiccomp/command_out(6),DIOB(6),clk,rst,'0');
FDCPE_NIDAQLogiccomp/command_out7: FDCPE port map (NIDAQLogiccomp/command_out(7),DIOB(7),clk,rst,'0');
FDCPE_NIDAQLogiccomp/command_out8: FDCPE port map (NIDAQLogiccomp/command_out(8),DIOA(0),clk,rst,'0');
FDCPE_NIDAQLogiccomp/command_out9: FDCPE port map (NIDAQLogiccomp/command_out(9),DIOA(1),clk,rst,'0');
FDCPE_NIDAQLogiccomp/command_out10: FDCPE port map (NIDAQLogiccomp/command_out(10),DIOA(2),clk,rst,'0');
FDCPE_NIDAQLogiccomp/command_out11: FDCPE port map (NIDAQLogiccomp/command_out(11),DIOA(3),clk,rst,'0');
FDCPE_NIDAQLogiccomp/command_out12: FDCPE port map (NIDAQLogiccomp/command_out(12),DIOA(4),clk,rst,'0');
FDCPE_NIDAQLogiccomp/command_out13: FDCPE port map (NIDAQLogiccomp/command_out(13),DIOA(5),clk,rst,'0');
FDCPE_NIDAQLogiccomp/command_out14: FDCPE port map (NIDAQLogiccomp/command_out(14),DIOA(6),clk,rst,'0');
FDCPE_NIDAQLogiccomp/command_out15: FDCPE port map (NIDAQLogiccomp/command_out(15),DIOA(7),clk,rst,'0');
FDCPE_NIDAQLogiccomp/wdone: FDCPE port map (NIDAQLogiccomp/wdone,NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd1,clk,rst,'0');
FDCPE_NIDAQLogiccomp/wen: FDCPE port map (NIDAQLogiccomp/wen,BUF_NIDAQLogiccomp/wen,clk,rst,'0');
OEn <= '0';
FDCPE_OPTCMD_Argsig0: FDCPE port map (OPTCMD_Argsig(0),OPTCMD_Argsig_D(0),clk,rst,'0');
OPTCMD_Argsig_D(0) <= ((NOT MainLogiccomp/MAINSTATE_FFd2 AND OPTCMD_Argsig(0))
OR (NICMD_Argsig(0) AND MainLogiccomp/MAINSTATE_FFd2 AND
MainLogiccomp/MAINSTATE_FFd3));
FDCPE_OPTCMD_Argsig1: FDCPE port map (OPTCMD_Argsig(1),OPTCMD_Argsig_D(1),clk,rst,'0');
OPTCMD_Argsig_D(1) <= ((NOT MainLogiccomp/MAINSTATE_FFd2 AND OPTCMD_Argsig(1))
OR (NICMD_Argsig(1) AND MainLogiccomp/MAINSTATE_FFd2 AND
MainLogiccomp/MAINSTATE_FFd3));
FDCPE_OPTCMD_Argsig2: FDCPE port map (OPTCMD_Argsig(2),OPTCMD_Argsig_D(2),clk,rst,'0');
OPTCMD_Argsig_D(2) <= ((NOT MainLogiccomp/MAINSTATE_FFd2 AND OPTCMD_Argsig(2))
OR (NICMD_Argsig(2) AND MainLogiccomp/MAINSTATE_FFd2 AND
MainLogiccomp/MAINSTATE_FFd3));
FDCPE_OPTCMD_Argsig3: FDCPE port map (OPTCMD_Argsig(3),OPTCMD_Argsig_D(3),clk,rst,'0');
OPTCMD_Argsig_D(3) <= ((NOT MainLogiccomp/MAINSTATE_FFd2 AND OPTCMD_Argsig(3))
OR (NICMD_Argsig(3) AND MainLogiccomp/MAINSTATE_FFd2 AND
MainLogiccomp/MAINSTATE_FFd3));
FDCPE_OPTCMD_Argsig4: FDCPE port map (OPTCMD_Argsig(4),OPTCMD_Argsig_D(4),clk,rst,'0');
OPTCMD_Argsig_D(4) <= ((NOT MainLogiccomp/MAINSTATE_FFd2 AND OPTCMD_Argsig(4))
OR (NICMD_Argsig(4) AND MainLogiccomp/MAINSTATE_FFd2 AND
MainLogiccomp/MAINSTATE_FFd3));
FDCPE_OPTCMD_Argsig5: FDCPE port map (OPTCMD_Argsig(5),OPTCMD_Argsig_D(5),clk,rst,'0');
OPTCMD_Argsig_D(5) <= ((NOT MainLogiccomp/MAINSTATE_FFd2 AND OPTCMD_Argsig(5))
OR (NICMD_Argsig(5) AND MainLogiccomp/MAINSTATE_FFd2 AND
MainLogiccomp/MAINSTATE_FFd3));
FDCPE_OPTCMD_Argsig6: FDCPE port map (OPTCMD_Argsig(6),OPTCMD_Argsig_D(6),clk,rst,'0');
OPTCMD_Argsig_D(6) <= ((NOT MainLogiccomp/MAINSTATE_FFd2 AND OPTCMD_Argsig(6))
OR (NICMD_Argsig(6) AND MainLogiccomp/MAINSTATE_FFd2 AND
MainLogiccomp/MAINSTATE_FFd3));
FDCPE_OPTCMD_Argsig7: FDCPE port map (OPTCMD_Argsig(7),OPTCMD_Argsig_D(7),clk,rst,'0');
OPTCMD_Argsig_D(7) <= ((NOT MainLogiccomp/MAINSTATE_FFd2 AND OPTCMD_Argsig(7))
OR (NICMD_Argsig(7) AND MainLogiccomp/MAINSTATE_FFd2 AND
MainLogiccomp/MAINSTATE_FFd3));
FDCPE_OPTCMD_Readysig: FDCPE port map (OPTCMD_Readysig,MainLogiccomp/MAINSTATE_FFd2,clk,rst,'0');
FDCPE_OPTCMDsig0: FDCPE port map (OPTCMDsig(0),OPTCMDsig_D(0),clk,rst,'0');
OPTCMDsig_D(0) <= ((NOT MainLogiccomp/MAINSTATE_FFd2 AND OPTCMDsig(0))
OR (NICMDsig(0) AND MainLogiccomp/MAINSTATE_FFd2 AND
MainLogiccomp/MAINSTATE_FFd3));
FDCPE_OPTCMDsig1: FDCPE port map (OPTCMDsig(1),OPTCMDsig_D(1),clk,rst,'0');
OPTCMDsig_D(1) <= ((NOT MainLogiccomp/MAINSTATE_FFd2 AND NOT OPTCMDsig(1))
OR (NOT NICMDsig(1) AND MainLogiccomp/MAINSTATE_FFd2 AND
MainLogiccomp/MAINSTATE_FFd3));
FDCPE_OPTCMDsig2: FDCPE port map (OPTCMDsig(2),OPTCMDsig_D(2),clk,rst,'0');
OPTCMDsig_D(2) <= ((NOT MainLogiccomp/MAINSTATE_FFd2 AND NOT OPTCMDsig(2))
OR (NOT NICMDsig(2) AND MainLogiccomp/MAINSTATE_FFd2 AND
MainLogiccomp/MAINSTATE_FFd3));
FDCPE_OPTCMDsig3: FDCPE port map (OPTCMDsig(3),OPTCMDsig_D(3),clk,rst,'0');
OPTCMDsig_D(3) <= ((NOT MainLogiccomp/MAINSTATE_FFd2 AND OPTCMDsig(3))
OR (NICMDsig(3) AND MainLogiccomp/MAINSTATE_FFd2 AND
MainLogiccomp/MAINSTATE_FFd3));
FDCPE_OPTCMDsig4: FDCPE port map (OPTCMDsig(4),OPTCMDsig_D(4),clk,rst,'0');
OPTCMDsig_D(4) <= ((NOT MainLogiccomp/MAINSTATE_FFd2 AND OPTCMDsig(4))
OR (SPARE(9) AND MainLogiccomp/MAINSTATE_FFd2 AND
MainLogiccomp/MAINSTATE_FFd3));
FDCPE_OPTCMDsig5: FDCPE port map (OPTCMDsig(5),OPTCMDsig_D(5),clk,rst,'0');
OPTCMDsig_D(5) <= ((NOT MainLogiccomp/MAINSTATE_FFd2 AND NOT OPTCMDsig(5))
OR (NOT SPARE(10) AND MainLogiccomp/MAINSTATE_FFd2 AND
MainLogiccomp/MAINSTATE_FFd3));
FDCPE_OPTCMDsig6: FDCPE port map (OPTCMDsig(6),OPTCMDsig_D(6),clk,rst,'0');
OPTCMDsig_D(6) <= ((NOT MainLogiccomp/MAINSTATE_FFd2 AND NOT OPTCMDsig(6))
OR (NOT SPARE(11) AND MainLogiccomp/MAINSTATE_FFd2 AND
MainLogiccomp/MAINSTATE_FFd3));
FDCPE_OPTCMDsig7: FDCPE port map (OPTCMDsig(7),OPTCMDsig_D(7),clk,rst,'0');
OPTCMDsig_D(7) <= ((NOT MainLogiccomp/MAINSTATE_FFd2 AND OPTCMDsig(7))
OR (SPARE(12) AND MainLogiccomp/MAINSTATE_FFd2 AND
MainLogiccomp/MAINSTATE_FFd3));
FDCPE_OpticalLogiccomp/GenSimDatasig: FDCPE port map (OpticalLogiccomp/GenSimDatasig,OpticalLogiccomp/GenSimDatasig_D,clk,rst,'0');
OpticalLogiccomp/GenSimDatasig_D <= (NOT OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
OpticalLogiccomp/OPTICALLOGICSTATE_FFd2);
FTCPE_OpticalLogiccomp/OPTICALLOGICSTATE_FFd1: FTCPE port map (OpticalLogiccomp/OPTICALLOGICSTATE_FFd1,OpticalLogiccomp/OPTICALLOGICSTATE_FFd1_T,clk,rst,'0');
OpticalLogiccomp/OPTICALLOGICSTATE_FFd1_T <= ((NOT OpticalLogiccomp/TransmitCommandcomp/sending AND
OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND OpticalLogiccomp/OPTICALLOGICSTATE_FFd2)
OR (NOT OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
NOT OpticalLogiccomp/OPTICALLOGICSTATE_FFd2 AND NOT OPTCMDsig(6) AND NOT OPTCMDsig(7) AND OPTCMD_Readysig)
OR (NOT OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
NOT OpticalLogiccomp/OPTICALLOGICSTATE_FFd2 AND OPTCMDsig(0) AND NOT OPTCMDsig(7) AND OPTCMDsig(1) AND
OPTCMDsig(2) AND NOT OPTCMDsig(3) AND NOT OPTCMDsig(4) AND OPTCMDsig(5) AND
OPTCMD_Readysig));
FTCPE_OpticalLogiccomp/OPTICALLOGICSTATE_FFd2: FTCPE port map (OpticalLogiccomp/OPTICALLOGICSTATE_FFd2,OpticalLogiccomp/OPTICALLOGICSTATE_FFd2_T,clk,rst,'0');
OpticalLogiccomp/OPTICALLOGICSTATE_FFd2_T <= ((NOT OpticalLogiccomp/TransmitCommandcomp/sending AND
OpticalLogiccomp/OPTICALLOGICSTATE_FFd1)
OR (NOT OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
OpticalLogiccomp/OPTICALLOGICSTATE_FFd2)
OR (NOT OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
NOT OPTCMDsig(0) AND OPTCMDsig(6) AND NOT OPTCMDsig(7) AND OPTCMDsig(1) AND
OPTCMDsig(2) AND NOT OPTCMDsig(3) AND NOT OPTCMDsig(4) AND OPTCMDsig(5) AND
OPTCMD_Readysig));
FDCPE_OpticalLogiccomp/RxDataLogiccomp/Busy: FDCPE port map (OpticalLogiccomp/RxDataLogiccomp/Busy,OpticalLogiccomp/RxDataLogiccomp/Busy_D,clk,rst,'0');
OpticalLogiccomp/RxDataLogiccomp/Busy_D <= (
NOT OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd1 AND
NOT OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd2);
FDCPE_OpticalLogiccomp/RxDataLogiccomp/EventReadyCmd: FDCPE port map (OpticalLogiccomp/RxDataLogiccomp/EventReadyCmd,OpticalLogiccomp/RxDataLogiccomp/EventReadyCmd_D,clk,rst,'0');
OpticalLogiccomp/RxDataLogiccomp/EventReadyCmd_D <= (
OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd2 AND OpticalLogiccomp/RxDataLogiccomp/GenDataDonesig);
FDCPE_OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig0: FDCPE port map (OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(0),D(0),clk,rst,'0');
FDCPE_OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig1: FDCPE port map (OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(1),D(1),clk,rst,'0');
FDCPE_OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig2: FDCPE port map (OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(2),D(2),clk,rst,'0');
FDCPE_OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig3: FDCPE port map (OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(3),D(3),clk,rst,'0');
FDCPE_OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig4: FDCPE port map (OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(4),D(4),clk,rst,'0');
FDCPE_OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig5: FDCPE port map (OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(5),D(5),clk,rst,'0');
FDCPE_OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig6: FDCPE port map (OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(6),D(6),clk,rst,'0');
FDCPE_OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig7: FDCPE port map (OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(7),D(7),clk,rst,'0');
FDCPE_OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig8: FDCPE port map (OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(8),D(8),clk,rst,'0');
FDCPE_OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig9: FDCPE port map (OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(9),D(9),clk,rst,'0');
FDCPE_OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig10: FDCPE port map (OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(10),D(10),clk,rst,'0');
FDCPE_OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig11: FDCPE port map (OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(11),D(11),clk,rst,'0');
FDCPE_OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig12: FDCPE port map (OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(12),D(12),clk,rst,'0');
FDCPE_OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig13: FDCPE port map (OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(13),D(13),clk,rst,'0');
FDCPE_OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig14: FDCPE port map (OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(14),D(14),clk,rst,'0');
FDCPE_OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig15: FDCPE port map (OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(15),D(15),clk,rst,'0');
FDCPE_OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_0: FDCPE port map (OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_0,OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_0_D,clk,rst,'0');
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_0_D <= (OpticalLogiccomp/RxDataLogiccomp/Busy AND
NOT OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_0);
FDCPE_OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_1: FDCPE port map (OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_1,OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_1_D,clk,rst,'0');
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_1_D <= ((OpticalLogiccomp/RxDataLogiccomp/Busy AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_0 AND
NOT OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_1)
OR (OpticalLogiccomp/RxDataLogiccomp/Busy AND
NOT OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_0 AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_1));
FTCPE_OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_10: FTCPE port map (OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_10,OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_10_T,clk,rst,'0');
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_10_T <= ((NOT OpticalLogiccomp/RxDataLogiccomp/Busy AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_10)
OR (OpticalLogiccomp/RxDataLogiccomp/Busy AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_9 AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0007/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0007_D2));
FTCPE_OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_11: FTCPE port map (OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_11,OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_11_T,clk,rst,'0');
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_11_T <= ((NOT OpticalLogiccomp/RxDataLogiccomp/Busy AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_11)
OR (OpticalLogiccomp/RxDataLogiccomp/Busy AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_10 AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_9 AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0007/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0007_D2));
FDCPE_OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_12: FDCPE port map (OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_12,OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_12_D,clk,rst,'0');
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_12_D <= ((OpticalLogiccomp/RxDataLogiccomp/Busy AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_12 AND
NOT OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0011/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0011_D2)
OR (OpticalLogiccomp/RxDataLogiccomp/Busy AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_10 AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_11 AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_9 AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0007/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0007_D2 AND
NOT OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0011/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0011_D2));
FDCPE_OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_13: FDCPE port map (OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_13,OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_13_D,clk,rst,'0');
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_13_D <= ((OpticalLogiccomp/RxDataLogiccomp/Busy AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_13 AND
NOT OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0011/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0011_D2)
OR (OpticalLogiccomp/RxDataLogiccomp/Busy AND
NOT OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_13 AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0011/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0011_D2));
FTCPE_OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_14: FTCPE port map (OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_14,OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_14_T,clk,rst,'0');
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_14_T <= ((NOT OpticalLogiccomp/RxDataLogiccomp/Busy AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_14)
OR (OpticalLogiccomp/RxDataLogiccomp/Busy AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_13 AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0011/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0011_D2));
FTCPE_OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_15: FTCPE port map (OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_15,OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_15_T,clk,rst,'0');
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_15_T <= ((NOT OpticalLogiccomp/RxDataLogiccomp/Busy AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_15)
OR (OpticalLogiccomp/RxDataLogiccomp/Busy AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_13 AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_14 AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0011/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0011_D2));
FTCPE_OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_2: FTCPE port map (OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_2,OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_2_T,clk,rst,'0');
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_2_T <= ((NOT OpticalLogiccomp/RxDataLogiccomp/Busy AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_2)
OR (OpticalLogiccomp/RxDataLogiccomp/Busy AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_0 AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_1));
FTCPE_OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_3: FTCPE port map (OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_3,OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_3_T,clk,rst,'0');
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_3_T <= ((NOT OpticalLogiccomp/RxDataLogiccomp/Busy AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_3)
OR (OpticalLogiccomp/RxDataLogiccomp/Busy AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_0 AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_1 AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_2));
FDCPE_OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_4: FDCPE port map (OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_4,OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_4_D,clk,rst,'0');
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_4_D <= ((OpticalLogiccomp/RxDataLogiccomp/Busy AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_4 AND
NOT OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0003/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0003_D2)
OR (OpticalLogiccomp/RxDataLogiccomp/Busy AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_0 AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_1 AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_2 AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_3 AND
NOT OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0003/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0003_D2));
FDCPE_OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_5: FDCPE port map (OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_5,OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_5_D,clk,rst,'0');
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_5_D <= ((OpticalLogiccomp/RxDataLogiccomp/Busy AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_5 AND
NOT OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0003/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0003_D2)
OR (OpticalLogiccomp/RxDataLogiccomp/Busy AND
NOT OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_5 AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0003/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0003_D2));
FTCPE_OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_6: FTCPE port map (OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_6,OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_6_T,clk,rst,'0');
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_6_T <= ((NOT OpticalLogiccomp/RxDataLogiccomp/Busy AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_6)
OR (OpticalLogiccomp/RxDataLogiccomp/Busy AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_5 AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0003/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0003_D2));
FTCPE_OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_7: FTCPE port map (OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_7,OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_7_T,clk,rst,'0');
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_7_T <= ((NOT OpticalLogiccomp/RxDataLogiccomp/Busy AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_7)
OR (OpticalLogiccomp/RxDataLogiccomp/Busy AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_5 AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_6 AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0003/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0003_D2));
FDCPE_OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_8: FDCPE port map (OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_8,OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_8_D,clk,rst,'0');
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_8_D <= ((OpticalLogiccomp/RxDataLogiccomp/Busy AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_8 AND
NOT OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0007/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0007_D2)
OR (OpticalLogiccomp/RxDataLogiccomp/Busy AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_5 AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_6 AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_7 AND
NOT OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0007/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0007_D2 AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0003/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0003_D2));
FDCPE_OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_9: FDCPE port map (OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_9,OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_9_D,clk,rst,'0');
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_9_D <= ((OpticalLogiccomp/RxDataLogiccomp/Busy AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_9 AND
NOT OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0007/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0007_D2)
OR (OpticalLogiccomp/RxDataLogiccomp/Busy AND
NOT OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_9 AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0007/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0007_D2));
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0003/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0003_D2 <= (
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_0 AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_1 AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_2 AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_3 AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_4);
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0007/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0007_D2 <= (
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_5 AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_6 AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_7 AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_8 AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0003/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0003_D2);
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0011/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0011_D2 <= (
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_10 AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_11 AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_12 AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_9 AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0007/OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_Madd__add0000__and0007_D2);
FDCPE_OpticalLogiccomp/RxDataLogiccomp/GenDataDonesig: FDCPE port map (OpticalLogiccomp/RxDataLogiccomp/GenDataDonesig,OpticalLogiccomp/RxDataLogiccomp/GenDataDonesig_D,clk,rst,'0');
OpticalLogiccomp/RxDataLogiccomp/GenDataDonesig_D <= (
NOT OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_0 AND
NOT OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_1 AND
NOT OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_10 AND
NOT OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_11 AND
OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_12 AND
NOT OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_13 AND
NOT OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_14 AND
NOT OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_2 AND
NOT OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_3 AND
NOT OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_4 AND
NOT OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_5 AND
NOT OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_6 AND
NOT OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_7 AND
NOT OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_8 AND
NOT OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_9 AND
NOT OpticalLogiccomp/RxDataLogiccomp/GenDataCounter_0_15);
FTCPE_OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd1: FTCPE port map (OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd1,OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd1_T,clk,rst,'0');
OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd1_T <= ((
OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd1 AND
OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd2 AND OpticalLogiccomp/RxDataLogiccomp/GenDataDonesig)
OR (
NOT OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd1 AND
NOT OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd2 AND OpticalLogiccomp/GenSimDatasig));
FTCPE_OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd2: FTCPE port map (OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd2,OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd2_T,clk,rst,'0');
OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd2_T <= ((
OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd1 AND
NOT OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd2)
OR (
OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd2 AND OpticalLogiccomp/RxDataLogiccomp/GenDataDonesig)
OR (
NOT OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd2 AND NOT OpticalLogiccomp/GenSimDatasig AND
NOT OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(0) AND NOT OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(10) AND
OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(11) AND NOT OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(12) AND
OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(13) AND NOT OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(14) AND
OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(15) AND OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(1) AND
NOT OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(2) AND OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(3) AND
NOT OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(4) AND OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(5) AND
NOT OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(6) AND OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(7) AND
NOT OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(8) AND OpticalLogiccomp/RxDataLogiccomp/GLinkDatasig(9) AND
DATAOK AND NOT RXERROR));
FDCPE_OpticalLogiccomp/TransmitCommandcomp/cnt0: FDCPE port map (OpticalLogiccomp/TransmitCommandcomp/cnt(0),OpticalLogiccomp/TransmitCommandcomp/cnt_D(0),clk,rst,'0');
OpticalLogiccomp/TransmitCommandcomp/cnt_D(0) <= (OpticalLogiccomp/TransmitCommandcomp/sending AND
OpticalLogiccomp/TransmitCommandcomp/cnt(0));
FDCPE_OpticalLogiccomp/TransmitCommandcomp/cnt1: FDCPE port map (OpticalLogiccomp/TransmitCommandcomp/cnt(1),OpticalLogiccomp/TransmitCommandcomp/cnt_D(1),clk,rst,'0');
OpticalLogiccomp/TransmitCommandcomp/cnt_D(1) <= ((OpticalLogiccomp/TransmitCommandcomp/sending AND
OpticalLogiccomp/TransmitCommandcomp/cnt(0) AND NOT OpticalLogiccomp/TransmitCommandcomp/cnt(1))
OR (OpticalLogiccomp/TransmitCommandcomp/sending AND
NOT OpticalLogiccomp/TransmitCommandcomp/cnt(0) AND OpticalLogiccomp/TransmitCommandcomp/cnt(1)));
FTCPE_OpticalLogiccomp/TransmitCommandcomp/cnt2: FTCPE port map (OpticalLogiccomp/TransmitCommandcomp/cnt(2),OpticalLogiccomp/TransmitCommandcomp/cnt_T(2),clk,rst,'0');
OpticalLogiccomp/TransmitCommandcomp/cnt_T(2) <= ((NOT OpticalLogiccomp/TransmitCommandcomp/sending AND
OpticalLogiccomp/TransmitCommandcomp/cnt(2))
OR (OpticalLogiccomp/TransmitCommandcomp/sending AND
NOT OpticalLogiccomp/TransmitCommandcomp/cnt(0) AND NOT OpticalLogiccomp/TransmitCommandcomp/cnt(1)));
FDCPE_OpticalLogiccomp/TransmitCommandcomp/cnt3: FDCPE port map (OpticalLogiccomp/TransmitCommandcomp/cnt(3),OpticalLogiccomp/TransmitCommandcomp/cnt_D(3),clk,rst,'0');
OpticalLogiccomp/TransmitCommandcomp/cnt_D(3) <= ((OpticalLogiccomp/TransmitCommandcomp/sending AND
OpticalLogiccomp/TransmitCommandcomp/cnt(3) AND
NOT OpticalLogiccomp/TransmitCommandcomp/cnt_Msub__sub0000__or0001/OpticalLogiccomp/TransmitCommandcomp/cnt_Msub__sub0000__or0001_D2)
OR (OpticalLogiccomp/TransmitCommandcomp/sending AND
NOT OpticalLogiccomp/TransmitCommandcomp/cnt(3) AND
OpticalLogiccomp/TransmitCommandcomp/cnt_Msub__sub0000__or0001/OpticalLogiccomp/TransmitCommandcomp/cnt_Msub__sub0000__or0001_D2));
FTCPE_OpticalLogiccomp/TransmitCommandcomp/cnt4: FTCPE port map (OpticalLogiccomp/TransmitCommandcomp/cnt(4),OpticalLogiccomp/TransmitCommandcomp/cnt_T(4),clk,rst,'0');
OpticalLogiccomp/TransmitCommandcomp/cnt_T(4) <= ((NOT OpticalLogiccomp/TransmitCommandcomp/sending AND
NOT OpticalLogiccomp/TransmitCommandcomp/cnt(4))
OR (OpticalLogiccomp/TransmitCommandcomp/sending AND
NOT OpticalLogiccomp/TransmitCommandcomp/cnt(3) AND
OpticalLogiccomp/TransmitCommandcomp/cnt_Msub__sub0000__or0001/OpticalLogiccomp/TransmitCommandcomp/cnt_Msub__sub0000__or0001_D2));
OpticalLogiccomp/TransmitCommandcomp/cnt_Msub__sub0000__or0001/OpticalLogiccomp/TransmitCommandcomp/cnt_Msub__sub0000__or0001_D2 <= (NOT OpticalLogiccomp/TransmitCommandcomp/cnt(0) AND
NOT OpticalLogiccomp/TransmitCommandcomp/cnt(1) AND NOT OpticalLogiccomp/TransmitCommandcomp/cnt(2));
FDCPE_OpticalLogiccomp/TransmitCommandcomp/sending: FDCPE port map (OpticalLogiccomp/TransmitCommandcomp/sending,OpticalLogiccomp/TransmitCommandcomp/sending_D,clk,rst,'0');
OpticalLogiccomp/TransmitCommandcomp/sending_D <= (NOT OpticalLogiccomp/TransmitCommandcomp/cnt(0) AND
NOT OpticalLogiccomp/TransmitCommandcomp/cnt(1) AND NOT OpticalLogiccomp/TransmitCommandcomp/cnt(2) AND
NOT OpticalLogiccomp/TransmitCommandcomp/cnt(3) AND NOT OpticalLogiccomp/TransmitCommandcomp/cnt(4));
FDCPE_OpticalLogiccomp/TransmitCommandcomp/sr0: FDCPE port map (OpticalLogiccomp/TransmitCommandcomp/sr(0),OpticalLogiccomp/TransmitCommandcomp/sr_D(0),clk,rst,'0');
OpticalLogiccomp/TransmitCommandcomp/sr_D(0) <= (OpticalLogiccomp/TransmitCommandcomp/sending AND
NOT OpticalLogiccomp/TransmitCommandcomp/sr(1));
FDCPE_OpticalLogiccomp/TransmitCommandcomp/sr1: FDCPE port map (OpticalLogiccomp/TransmitCommandcomp/sr(1),OpticalLogiccomp/TransmitCommandcomp/sr_D(1),clk,rst,'0');
OpticalLogiccomp/TransmitCommandcomp/sr_D(1) <= (OpticalLogiccomp/TransmitCommandcomp/sending AND
NOT OpticalLogiccomp/TransmitCommandcomp/sr(2));
FDCPE_OpticalLogiccomp/TransmitCommandcomp/sr2: FDCPE port map (OpticalLogiccomp/TransmitCommandcomp/sr(2),OpticalLogiccomp/TransmitCommandcomp/sr_D(2),clk,rst,'0');
OpticalLogiccomp/TransmitCommandcomp/sr_D(2) <= (OpticalLogiccomp/TransmitCommandcomp/sending AND
OpticalLogiccomp/TransmitCommandcomp/sr(3));
FDCPE_OpticalLogiccomp/TransmitCommandcomp/sr3: FDCPE port map (OpticalLogiccomp/TransmitCommandcomp/sr(3),OpticalLogiccomp/TransmitCommandcomp/sr_D(3),clk,rst,'0');
OpticalLogiccomp/TransmitCommandcomp/sr_D(3) <= (OpticalLogiccomp/TransmitCommandcomp/sending AND
NOT OpticalLogiccomp/TransmitCommandcomp/sr(4));
FDCPE_OpticalLogiccomp/TransmitCommandcomp/sr4: FDCPE port map (OpticalLogiccomp/TransmitCommandcomp/sr(4),OpticalLogiccomp/TransmitCommandcomp/sr_D(4),clk,rst,'0');
OpticalLogiccomp/TransmitCommandcomp/sr_D(4) <= ((OpticalLogiccomp/TransmitCommandcomp/sending AND
OpticalLogiccomp/TransmitCommandcomp/sr(5))
OR (NOT OpticalLogiccomp/TransmitCommandcomp/sending AND
OpticalLogiccomp/command_insig(0)));
FDCPE_OpticalLogiccomp/TransmitCommandcomp/sr5: FDCPE port map (OpticalLogiccomp/TransmitCommandcomp/sr(5),OpticalLogiccomp/TransmitCommandcomp/sr_D(5),clk,rst,'0');
OpticalLogiccomp/TransmitCommandcomp/sr_D(5) <= ((OpticalLogiccomp/TransmitCommandcomp/sending AND
OpticalLogiccomp/TransmitCommandcomp/sr(6))
OR (NOT OpticalLogiccomp/TransmitCommandcomp/sending AND
OpticalLogiccomp/command_insig(1)));
FDCPE_OpticalLogiccomp/TransmitCommandcomp/sr6: FDCPE port map (OpticalLogiccomp/TransmitCommandcomp/sr(6),OpticalLogiccomp/TransmitCommandcomp/sr_D(6),clk,rst,'0');
OpticalLogiccomp/TransmitCommandcomp/sr_D(6) <= ((OpticalLogiccomp/TransmitCommandcomp/sending AND
OpticalLogiccomp/TransmitCommandcomp/sr(7))
OR (NOT OpticalLogiccomp/TransmitCommandcomp/sending AND
OpticalLogiccomp/command_insig(2)));
FDCPE_OpticalLogiccomp/TransmitCommandcomp/sr7: FDCPE port map (OpticalLogiccomp/TransmitCommandcomp/sr(7),OpticalLogiccomp/TransmitCommandcomp/sr_D(7),clk,rst,'0');
OpticalLogiccomp/TransmitCommandcomp/sr_D(7) <= ((OpticalLogiccomp/TransmitCommandcomp/sending AND
OpticalLogiccomp/TransmitCommandcomp/sr(8))
OR (NOT OpticalLogiccomp/TransmitCommandcomp/sending AND
OpticalLogiccomp/command_insig(3)));
FDCPE_OpticalLogiccomp/TransmitCommandcomp/sr8: FDCPE port map (OpticalLogiccomp/TransmitCommandcomp/sr(8),OpticalLogiccomp/TransmitCommandcomp/sr_D(8),clk,rst,'0');
OpticalLogiccomp/TransmitCommandcomp/sr_D(8) <= ((OpticalLogiccomp/TransmitCommandcomp/sending AND
OpticalLogiccomp/TransmitCommandcomp/sr(9))
OR (NOT OpticalLogiccomp/TransmitCommandcomp/sending AND
OpticalLogiccomp/command_insig(4)));
FDCPE_OpticalLogiccomp/TransmitCommandcomp/sr9: FDCPE port map (OpticalLogiccomp/TransmitCommandcomp/sr(9),OpticalLogiccomp/TransmitCommandcomp/sr_D(9),clk,rst,'0');
OpticalLogiccomp/TransmitCommandcomp/sr_D(9) <= ((OpticalLogiccomp/TransmitCommandcomp/sending AND
OpticalLogiccomp/TransmitCommandcomp/sr(10))
OR (NOT OpticalLogiccomp/TransmitCommandcomp/sending AND
OpticalLogiccomp/command_insig(5)));
FDCPE_OpticalLogiccomp/TransmitCommandcomp/sr10: FDCPE port map (OpticalLogiccomp/TransmitCommandcomp/sr(10),OpticalLogiccomp/TransmitCommandcomp/sr_D(10),clk,rst,'0');
OpticalLogiccomp/TransmitCommandcomp/sr_D(10) <= ((OpticalLogiccomp/TransmitCommandcomp/sending AND
OpticalLogiccomp/TransmitCommandcomp/sr(11))
OR (NOT OpticalLogiccomp/TransmitCommandcomp/sending AND
OpticalLogiccomp/command_insig(6)));
FDCPE_OpticalLogiccomp/TransmitCommandcomp/sr11: FDCPE port map (OpticalLogiccomp/TransmitCommandcomp/sr(11),OpticalLogiccomp/TransmitCommandcomp/sr_D(11),clk,rst,'0');
OpticalLogiccomp/TransmitCommandcomp/sr_D(11) <= ((OpticalLogiccomp/TransmitCommandcomp/sending AND
OpticalLogiccomp/TransmitCommandcomp/sr(12))
OR (NOT OpticalLogiccomp/TransmitCommandcomp/sending AND
OpticalLogiccomp/command_insig(7)));
FDCPE_OpticalLogiccomp/TransmitCommandcomp/sr12: FDCPE port map (OpticalLogiccomp/TransmitCommandcomp/sr(12),OpticalLogiccomp/TransmitCommandcomp/sr_D(12),clk,rst,'0');
OpticalLogiccomp/TransmitCommandcomp/sr_D(12) <= ((OpticalLogiccomp/TransmitCommandcomp/sending AND
OpticalLogiccomp/TransmitCommandcomp/sr(13))
OR (NOT OpticalLogiccomp/TransmitCommandcomp/sending AND
OpticalLogiccomp/command_insig(8)));
FDCPE_OpticalLogiccomp/TransmitCommandcomp/sr13: FDCPE port map (OpticalLogiccomp/TransmitCommandcomp/sr(13),OpticalLogiccomp/TransmitCommandcomp/sr_D(13),clk,rst,'0');
OpticalLogiccomp/TransmitCommandcomp/sr_D(13) <= ((OpticalLogiccomp/TransmitCommandcomp/sending AND
OpticalLogiccomp/TransmitCommandcomp/sr(14))
OR (NOT OpticalLogiccomp/TransmitCommandcomp/sending AND
OpticalLogiccomp/command_insig(9)));
FDCPE_OpticalLogiccomp/TransmitCommandcomp/sr14: FDCPE port map (OpticalLogiccomp/TransmitCommandcomp/sr(14),OpticalLogiccomp/TransmitCommandcomp/sr_D(14),clk,rst,'0');
OpticalLogiccomp/TransmitCommandcomp/sr_D(14) <= ((OpticalLogiccomp/TransmitCommandcomp/sending AND
OpticalLogiccomp/TransmitCommandcomp/sr(15))
OR (NOT OpticalLogiccomp/TransmitCommandcomp/sending AND
OpticalLogiccomp/command_insig(10)));
FDCPE_OpticalLogiccomp/TransmitCommandcomp/sr15: FDCPE port map (OpticalLogiccomp/TransmitCommandcomp/sr(15),OpticalLogiccomp/TransmitCommandcomp/sr_D(15),clk,rst,'0');
OpticalLogiccomp/TransmitCommandcomp/sr_D(15) <= ((OpticalLogiccomp/TransmitCommandcomp/sending AND
OpticalLogiccomp/TransmitCommandcomp/sr(16))
OR (NOT OpticalLogiccomp/TransmitCommandcomp/sending AND
OpticalLogiccomp/command_insig(11)));
FDCPE_OpticalLogiccomp/TransmitCommandcomp/sr16: FDCPE port map (OpticalLogiccomp/TransmitCommandcomp/sr(16),OpticalLogiccomp/TransmitCommandcomp/sr_D(16),clk,rst,'0');
OpticalLogiccomp/TransmitCommandcomp/sr_D(16) <= ((OpticalLogiccomp/TransmitCommandcomp/sending AND
OpticalLogiccomp/TransmitCommandcomp/sr(17))
OR (NOT OpticalLogiccomp/TransmitCommandcomp/sending AND
OpticalLogiccomp/command_insig(12)));
FDCPE_OpticalLogiccomp/TransmitCommandcomp/sr17: FDCPE port map (OpticalLogiccomp/TransmitCommandcomp/sr(17),OpticalLogiccomp/TransmitCommandcomp/sr_D(17),clk,rst,'0');
OpticalLogiccomp/TransmitCommandcomp/sr_D(17) <= ((OpticalLogiccomp/TransmitCommandcomp/sending AND
OpticalLogiccomp/TransmitCommandcomp/sr(18))
OR (NOT OpticalLogiccomp/TransmitCommandcomp/sending AND
OpticalLogiccomp/command_insig(13)));
FDCPE_OpticalLogiccomp/TransmitCommandcomp/sr18: FDCPE port map (OpticalLogiccomp/TransmitCommandcomp/sr(18),OpticalLogiccomp/TransmitCommandcomp/sr_D(18),clk,rst,'0');
OpticalLogiccomp/TransmitCommandcomp/sr_D(18) <= ((OpticalLogiccomp/TransmitCommandcomp/sr(19) AND
OpticalLogiccomp/TransmitCommandcomp/sending)
OR (NOT OpticalLogiccomp/TransmitCommandcomp/sending AND
OpticalLogiccomp/command_insig(14)));
FDCPE_OpticalLogiccomp/TransmitCommandcomp/sr19: FDCPE port map (OpticalLogiccomp/TransmitCommandcomp/sr(19),OpticalLogiccomp/command_insig(15),clk,rst,'0',NOT OpticalLogiccomp/TransmitCommandcomp/sending);
FDCPE_OpticalLogiccomp/command_insig0: FDCPE port map (OpticalLogiccomp/command_insig(0),OpticalLogiccomp/command_insig_D(0),clk,rst,'0');
OpticalLogiccomp/command_insig_D(0) <= ((OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
OPTCMD_Argsig(0))
OR (NOT OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
OpticalLogiccomp/OPTICALLOGICSTATE_FFd2 AND OpticalLogiccomp/command_insig(0))
OR (NOT OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
NOT OpticalLogiccomp/OPTICALLOGICSTATE_FFd2 AND HFn));
FDCPE_OpticalLogiccomp/command_insig1: FDCPE port map (OpticalLogiccomp/command_insig(1),OpticalLogiccomp/command_insig_D(1),clk,rst,'0');
OpticalLogiccomp/command_insig_D(1) <= ((OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
OPTCMD_Argsig(1))
OR (NOT OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
OpticalLogiccomp/OPTICALLOGICSTATE_FFd2 AND OpticalLogiccomp/command_insig(1)));
FDCPE_OpticalLogiccomp/command_insig2: FDCPE port map (OpticalLogiccomp/command_insig(2),OpticalLogiccomp/command_insig_D(2),clk,rst,'0');
OpticalLogiccomp/command_insig_D(2) <= ((OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
OPTCMD_Argsig(2))
OR (NOT OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
OpticalLogiccomp/OPTICALLOGICSTATE_FFd2 AND OpticalLogiccomp/command_insig(2)));
FDCPE_OpticalLogiccomp/command_insig3: FDCPE port map (OpticalLogiccomp/command_insig(3),OpticalLogiccomp/command_insig_D(3),clk,rst,'0');
OpticalLogiccomp/command_insig_D(3) <= ((OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
OPTCMD_Argsig(3))
OR (NOT OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
OpticalLogiccomp/OPTICALLOGICSTATE_FFd2 AND OpticalLogiccomp/command_insig(3)));
FDCPE_OpticalLogiccomp/command_insig4: FDCPE port map (OpticalLogiccomp/command_insig(4),OpticalLogiccomp/command_insig_D(4),clk,rst,'0');
OpticalLogiccomp/command_insig_D(4) <= ((OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
OPTCMD_Argsig(4))
OR (NOT OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
OpticalLogiccomp/OPTICALLOGICSTATE_FFd2 AND OpticalLogiccomp/command_insig(4)));
FDCPE_OpticalLogiccomp/command_insig5: FDCPE port map (OpticalLogiccomp/command_insig(5),OpticalLogiccomp/command_insig_D(5),clk,rst,'0');
OpticalLogiccomp/command_insig_D(5) <= ((OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
OPTCMD_Argsig(5))
OR (NOT OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
OpticalLogiccomp/OPTICALLOGICSTATE_FFd2 AND OpticalLogiccomp/command_insig(5)));
FDCPE_OpticalLogiccomp/command_insig6: FDCPE port map (OpticalLogiccomp/command_insig(6),OpticalLogiccomp/command_insig_D(6),clk,rst,'0');
OpticalLogiccomp/command_insig_D(6) <= ((OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
OPTCMD_Argsig(6))
OR (NOT OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
OpticalLogiccomp/OPTICALLOGICSTATE_FFd2 AND OpticalLogiccomp/command_insig(6)));
FDCPE_OpticalLogiccomp/command_insig7: FDCPE port map (OpticalLogiccomp/command_insig(7),OpticalLogiccomp/command_insig_D(7),clk,rst,'0');
OpticalLogiccomp/command_insig_D(7) <= ((OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
OPTCMD_Argsig(7))
OR (NOT OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
OpticalLogiccomp/OPTICALLOGICSTATE_FFd2 AND OpticalLogiccomp/command_insig(7)));
FDCPE_OpticalLogiccomp/command_insig8: FDCPE port map (OpticalLogiccomp/command_insig(8),OpticalLogiccomp/command_insig_D(8),clk,rst,'0');
OpticalLogiccomp/command_insig_D(8) <= ((OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
NOT OPTCMDsig(0))
OR (NOT OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
OpticalLogiccomp/OPTICALLOGICSTATE_FFd2 AND NOT OpticalLogiccomp/command_insig(8)));
FDCPE_OpticalLogiccomp/command_insig9: FDCPE port map (OpticalLogiccomp/command_insig(9),OpticalLogiccomp/command_insig_D(9),clk,rst,'0');
OpticalLogiccomp/command_insig_D(9) <= ((OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
OPTCMDsig(1))
OR (NOT OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
OpticalLogiccomp/OPTICALLOGICSTATE_FFd2 AND OpticalLogiccomp/command_insig(9)));
FDCPE_OpticalLogiccomp/command_insig10: FDCPE port map (OpticalLogiccomp/command_insig(10),OpticalLogiccomp/command_insig_D(10),clk,rst,'0');
OpticalLogiccomp/command_insig_D(10) <= ((OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
OPTCMDsig(2))
OR (NOT OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
OpticalLogiccomp/OPTICALLOGICSTATE_FFd2 AND OpticalLogiccomp/command_insig(10)));
FDCPE_OpticalLogiccomp/command_insig11: FDCPE port map (OpticalLogiccomp/command_insig(11),OpticalLogiccomp/command_insig_D(11),clk,rst,'0');
OpticalLogiccomp/command_insig_D(11) <= ((OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
NOT OPTCMDsig(3))
OR (NOT OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
OpticalLogiccomp/OPTICALLOGICSTATE_FFd2 AND NOT OpticalLogiccomp/command_insig(11)));
FDCPE_OpticalLogiccomp/command_insig12: FDCPE port map (OpticalLogiccomp/command_insig(12),OpticalLogiccomp/command_insig_D(12),clk,rst,'0');
OpticalLogiccomp/command_insig_D(12) <= ((OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
OPTCMDsig(4))
OR (NOT OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
OpticalLogiccomp/OPTICALLOGICSTATE_FFd2 AND OpticalLogiccomp/command_insig(12)));
FDCPE_OpticalLogiccomp/command_insig13: FDCPE port map (OpticalLogiccomp/command_insig(13),OpticalLogiccomp/command_insig_D(13),clk,rst,'0');
OpticalLogiccomp/command_insig_D(13) <= ((OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
NOT OPTCMDsig(5))
OR (NOT OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
OpticalLogiccomp/OPTICALLOGICSTATE_FFd2 AND NOT OpticalLogiccomp/command_insig(13)));
FDCPE_OpticalLogiccomp/command_insig14: FDCPE port map (OpticalLogiccomp/command_insig(14),OpticalLogiccomp/command_insig_D(14),clk,rst,'0');
OpticalLogiccomp/command_insig_D(14) <= ((OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
NOT OPTCMDsig(6))
OR (NOT OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
OpticalLogiccomp/OPTICALLOGICSTATE_FFd2 AND NOT OpticalLogiccomp/command_insig(14)));
FDCPE_OpticalLogiccomp/command_insig15: FDCPE port map (OpticalLogiccomp/command_insig(15),OpticalLogiccomp/command_insig_D(15),clk,rst,'0');
OpticalLogiccomp/command_insig_D(15) <= ((OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
OPTCMDsig(7))
OR (NOT OpticalLogiccomp/OPTICALLOGICSTATE_FFd1 AND
OpticalLogiccomp/OPTICALLOGICSTATE_FFd2 AND OpticalLogiccomp/command_insig(15)));
RCLK <= clk;
FDCPE_RENn: FDCPE port map (RENn,RENn_D,clk,'0',rst);
RENn_D <= (NOT NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NIDAQLogiccomp/NIDAQSTATE_FFd3 AND NIDAQLogiccomp/NIDAQSTATE_FFd2);
FDCPE_REQ1: FDCPE port map (REQ1,NIDAQLogiccomp/NI_Interfacecomp/ack1_sync(2),NOT clk,rst,'0');
FDCPE_REQ2: FDCPE port map (REQ2,NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd3,clk,rst,'0');
FDCPE_RSTn: FDCPE port map (RSTn,'1',clk,rst,'0');
FDCPE_SPARE0: FDCPE port map (SPARE(0),SPARE_D(0),clk,rst,'0');
SPARE_D(0) <= ((NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NOT NIDAQLogiccomp/NIDAQSTATE_FFd3 AND NIDAQLogiccomp/NIDAQSTATE_FFd2)
OR (NOT NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NIDAQLogiccomp/NIDAQSTATE_FFd3 AND NIDAQLogiccomp/NIDAQSTATE_FFd2)
OR (NOT NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NOT NIDAQLogiccomp/NIDAQSTATE_FFd3 AND NOT NIDAQLogiccomp/NIDAQSTATE_FFd2));
FDCPE_SPARE1: FDCPE port map (SPARE(1),SPARE_D(1),clk,rst,'0');
SPARE_D(1) <= ((NIDAQLogiccomp/NIDAQSTATE_FFd3 AND
NOT NIDAQLogiccomp/NIDAQSTATE_FFd2)
OR (NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NOT NIDAQLogiccomp/NIDAQSTATE_FFd3 AND NIDAQLogiccomp/NIDAQSTATE_FFd2));
FDCPE_SPARE2: FDCPE port map (SPARE(2),SPARE_D(2),clk,rst,'0');
SPARE_D(2) <= ((NOT NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NIDAQLogiccomp/NIDAQSTATE_FFd3)
OR (NOT NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NIDAQLogiccomp/NIDAQSTATE_FFd2));
FDCPE_SPARE3: FDCPE port map (SPARE(3),NIDAQLogiccomp/cav,clk,rst,'0');
FDCPE_SPARE4: FDCPE port map (SPARE(4),SPARE_D(4),clk,rst,'0');
SPARE_D(4) <= (NOT NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NOT NIDAQLogiccomp/NIDAQSTATE_FFd3 AND NOT NIDAQLogiccomp/NIDAQSTATE_FFd2);
FDCPE_SPARE5: FDCPE port map (SPARE(5),NIDAQLogiccomp/NI_Interfacecomp/ack1_sync(2),NOT clk,rst,'0');
SPARE(6) <= ACK1;
FDCPE_SPARE7: FDCPE port map (SPARE(7),NIDAQLogiccomp/NI_Interfacecomp/p2state_FFd3,clk,rst,'0');
SPARE(8) <= ACK2;
FDCPE_SPARE9: FDCPE port map (SPARE(9),NIDAQLogiccomp/command_out(12),clk,rst,'0',SPARE_CE(9));
SPARE_CE(9) <= (NOT NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NIDAQLogiccomp/NIDAQSTATE_FFd3 AND NOT NIDAQLogiccomp/NIDAQSTATE_FFd2);
FDCPE_SPARE10: FDCPE port map (SPARE(10),NIDAQLogiccomp/command_out(13),clk,rst,'0',SPARE_CE(10));
SPARE_CE(10) <= (NOT NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NIDAQLogiccomp/NIDAQSTATE_FFd3 AND NOT NIDAQLogiccomp/NIDAQSTATE_FFd2);
FDCPE_SPARE11: FDCPE port map (SPARE(11),NIDAQLogiccomp/command_out(14),clk,rst,'0',SPARE_CE(11));
SPARE_CE(11) <= (NOT NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NIDAQLogiccomp/NIDAQSTATE_FFd3 AND NOT NIDAQLogiccomp/NIDAQSTATE_FFd2);
FDCPE_SPARE12: FDCPE port map (SPARE(12),NIDAQLogiccomp/command_out(15),clk,rst,'0',SPARE_CE(12));
SPARE_CE(12) <= (NOT NIDAQLogiccomp/NIDAQSTATE_FFd1 AND
NIDAQLogiccomp/NIDAQSTATE_FFd3 AND NOT NIDAQLogiccomp/NIDAQSTATE_FFd2);
STOPTRIG1 <= '1';
STOPTRIG2 <= '1';
FDCPE_SendDataCmdsig: FDCPE port map (SendDataCmdsig,MainLogiccomp/MAINSTATE_FFd1,clk,rst,'0');
FDCPE_StatusDatasig0: FDCPE port map (StatusDatasig(0),StatusDatasig_D(0),clk,rst,'0');
StatusDatasig_D(0) <= ((NOT MainLogiccomp/MAINSTATE_FFd1 AND StatusDatasig(0))
OR (MainLogiccomp/MAINSTATE_FFd1 AND
MainLogiccomp/MAINSTATE_FFd3 AND D(0))
OR (MainLogiccomp/MAINSTATE_FFd1 AND
NOT MainLogiccomp/MAINSTATE_FFd3 AND NOT EFn));
FDCPE_StatusDatasig1: FDCPE port map (StatusDatasig(1),StatusDatasig_D(1),clk,rst,'0');
StatusDatasig_D(1) <= ((NOT MainLogiccomp/MAINSTATE_FFd1 AND StatusDatasig(1))
OR (MainLogiccomp/MAINSTATE_FFd1 AND
MainLogiccomp/MAINSTATE_FFd3 AND D(1))
OR (MainLogiccomp/MAINSTATE_FFd1 AND
NOT MainLogiccomp/MAINSTATE_FFd3 AND NOT FFn));
FDCPE_StatusDatasig2: FDCPE port map (StatusDatasig(2),StatusDatasig_D(2),clk,rst,'0');
StatusDatasig_D(2) <= ((NOT MainLogiccomp/MAINSTATE_FFd1 AND StatusDatasig(2))
OR (MainLogiccomp/MAINSTATE_FFd1 AND
MainLogiccomp/MAINSTATE_FFd3 AND D(2))
OR (MainLogiccomp/MAINSTATE_FFd1 AND
NOT MainLogiccomp/MAINSTATE_FFd3 AND NOT HFn));
FDCPE_StatusDatasig3: FDCPE port map (StatusDatasig(3),StatusDatasig_D(3),clk,rst,'0');
StatusDatasig_D(3) <= ((NOT MainLogiccomp/MAINSTATE_FFd1 AND StatusDatasig(3))
OR (MainLogiccomp/MAINSTATE_FFd1 AND
MainLogiccomp/MAINSTATE_FFd3 AND D(3))
OR (MainLogiccomp/MAINSTATE_FFd1 AND
NOT MainLogiccomp/MAINSTATE_FFd3 AND DATAOK));
FDCPE_StatusDatasig4: FDCPE port map (StatusDatasig(4),StatusDatasig_D(4),clk,rst,'0');
StatusDatasig_D(4) <= ((NOT MainLogiccomp/MAINSTATE_FFd1 AND StatusDatasig(4))
OR (MainLogiccomp/MAINSTATE_FFd1 AND
MainLogiccomp/MAINSTATE_FFd3 AND D(4))
OR (MainLogiccomp/MAINSTATE_FFd1 AND
NOT MainLogiccomp/MAINSTATE_FFd3 AND RXREADY));
FDCPE_StatusDatasig5: FDCPE port map (StatusDatasig(5),StatusDatasig_D(5),clk,rst,'0');
StatusDatasig_D(5) <= ((NOT MainLogiccomp/MAINSTATE_FFd1 AND StatusDatasig(5))
OR (MainLogiccomp/MAINSTATE_FFd1 AND
MainLogiccomp/MAINSTATE_FFd3 AND D(5))
OR (MainLogiccomp/MAINSTATE_FFd1 AND
NOT MainLogiccomp/MAINSTATE_FFd3 AND RXDATA));
FDCPE_StatusDatasig6: FDCPE port map (StatusDatasig(6),StatusDatasig_D(6),clk,rst,'0');
StatusDatasig_D(6) <= ((NOT MainLogiccomp/MAINSTATE_FFd1 AND StatusDatasig(6))
OR (MainLogiccomp/MAINSTATE_FFd1 AND
MainLogiccomp/MAINSTATE_FFd3 AND D(6))
OR (MainLogiccomp/MAINSTATE_FFd1 AND
NOT MainLogiccomp/MAINSTATE_FFd3 AND RXERROR));
FDCPE_StatusDatasig7: FDCPE port map (StatusDatasig(7),StatusDatasig_D(7),clk,rst,'0');
StatusDatasig_D(7) <= ((NOT MainLogiccomp/MAINSTATE_FFd1 AND StatusDatasig(7))
OR (MainLogiccomp/MAINSTATE_FFd1 AND
MainLogiccomp/MAINSTATE_FFd3 AND D(7))
OR (MainLogiccomp/MAINSTATE_FFd1 AND
NOT MainLogiccomp/MAINSTATE_FFd3 AND EventReadysig));
FDCPE_StatusDatasig8: FDCPE port map (StatusDatasig(8),StatusDatasig_D(8),clk,rst,'0');
StatusDatasig_D(8) <= ((NOT MainLogiccomp/MAINSTATE_FFd1 AND StatusDatasig(8))
OR (MainLogiccomp/MAINSTATE_FFd1 AND
MainLogiccomp/MAINSTATE_FFd3 AND D(8)));
FDCPE_StatusDatasig9: FDCPE port map (StatusDatasig(9),StatusDatasig_D(9),clk,rst,'0');
StatusDatasig_D(9) <= ((NOT MainLogiccomp/MAINSTATE_FFd1 AND StatusDatasig(9))
OR (MainLogiccomp/MAINSTATE_FFd1 AND
MainLogiccomp/MAINSTATE_FFd3 AND D(9)));
FDCPE_StatusDatasig10: FDCPE port map (StatusDatasig(10),StatusDatasig_D(10),clk,rst,'0');
StatusDatasig_D(10) <= ((NOT MainLogiccomp/MAINSTATE_FFd1 AND StatusDatasig(10))
OR (MainLogiccomp/MAINSTATE_FFd1 AND
MainLogiccomp/MAINSTATE_FFd3 AND D(10)));
FDCPE_StatusDatasig11: FDCPE port map (StatusDatasig(11),StatusDatasig_D(11),clk,rst,'0');
StatusDatasig_D(11) <= ((NOT MainLogiccomp/MAINSTATE_FFd1 AND StatusDatasig(11))
OR (MainLogiccomp/MAINSTATE_FFd1 AND
MainLogiccomp/MAINSTATE_FFd3 AND D(11)));
FDCPE_StatusDatasig12: FDCPE port map (StatusDatasig(12),StatusDatasig_D(12),clk,rst,'0');
StatusDatasig_D(12) <= ((NOT MainLogiccomp/MAINSTATE_FFd1 AND StatusDatasig(12))
OR (MainLogiccomp/MAINSTATE_FFd1 AND
MainLogiccomp/MAINSTATE_FFd3 AND D(12)));
FDCPE_StatusDatasig13: FDCPE port map (StatusDatasig(13),StatusDatasig_D(13),clk,rst,'0');
StatusDatasig_D(13) <= ((NOT MainLogiccomp/MAINSTATE_FFd1 AND StatusDatasig(13))
OR (MainLogiccomp/MAINSTATE_FFd1 AND
MainLogiccomp/MAINSTATE_FFd3 AND D(13)));
FDCPE_StatusDatasig14: FDCPE port map (StatusDatasig(14),StatusDatasig_D(14),clk,rst,'0');
StatusDatasig_D(14) <= ((NOT MainLogiccomp/MAINSTATE_FFd1 AND StatusDatasig(14))
OR (MainLogiccomp/MAINSTATE_FFd1 AND
MainLogiccomp/MAINSTATE_FFd3 AND D(14)));
FDCPE_StatusDatasig15: FDCPE port map (StatusDatasig(15),StatusDatasig_D(15),clk,rst,'0');
StatusDatasig_D(15) <= ((NOT MainLogiccomp/MAINSTATE_FFd1 AND StatusDatasig(15))
OR (MainLogiccomp/MAINSTATE_FFd1 AND
MainLogiccomp/MAINSTATE_FFd3 AND D(15)));
WCLK <= clk;
FDCPE_WENn: FDCPE port map (WENn,WENn_D,clk,'0',rst);
WENn_D <= (
OpticalLogiccomp/RxDataLogiccomp/RXDATALOGICSTATE_FFd2 AND NOT OpticalLogiccomp/RxDataLogiccomp/GenDataDonesig);
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE);
FTCPE (Q,D,C,CLR,PRE,CE);
LDCP (Q,D,G,CLR,PRE);
****************************** Device Pin Out *****************************
Device : XC95288XL-6-TQ144
Pin Signal Pin Signal
No. Name No. Name
1 VCC 73 VCC
2 FIFO_D<8> 74 DIOA<5>
3 FIFO_D<9> 75 DIOA<4>
4 FIFO_D<10> 76 DIOA<3>
5 FIFO_D<11> 77 DIOA<2>
6 FIFO_D<12> 78 DIOA<1>
7 FIFO_D<13> 79 DIOA<0>
8 VCC 80 DIOB<7>
9 FIFO_D<14> 81 DIOB<6>
10 FIFO_D<15> 82 DIOB<5>
11 RCLK 83 DIOB<4>
12 RENn 84 VCC
13 OEn 85 DIOB<3>
14 RSTn 86 DIOB<2>
15 EFn 87 DIOB<1>
16 FIFO_Q<15> 88 DIOB<0>
17 FIFO_Q<14> 89 GND
18 GND 90 GND
19 FIFO_Q<13> 91 DIOC<7>
20 FIFO_Q<12> 92 DIOC<6>
21 FIFO_Q<11> 93 DIOC<5>
22 FIFO_Q<10> 94 DIOC<4>
23 FIFO_Q<9> 95 DIOC<3>
24 FIFO_Q<8> 96 DIOC<2>
25 FIFO_Q<7> 97 DIOC<1>
26 FIFO_Q<6> 98 DIOC<0>
27 FIFO_Q<5> 99 GND
28 FIFO_Q<4> 100 DIOD<7>
29 GND 101 DIOD<6>
30 clk 102 DIOD<5>
31 FIFO_Q<3> 103 DIOD<4>
32 SPARE<12> 104 DIOD<3>
33 FIFO_Q<2> 105 DIOD<2>
34 FIFO_Q<1> 106 DIOD<1>
35 FIFO_Q<0> 107 DIOD<0>
36 GND 108 GND
37 VCC 109 VCC
38 SPARE<11> 110 ACK2
39 D<15> 111 REQ2
40 D<14> 112 STOPTRIG1
41 D<13> 113 KPR
42 VCC 114 GND
43 D<12> 115 ACK1
44 D<11> 116 REQ1
45 D<10> 117 STOPTRIG2
46 D<9> 118 KPR
47 GND 119 SPARE<7>
48 D<8> 120 SPARE<6>
49 D<7> 121 SPARE<5>
50 D<6> 122 TDO
51 D<5> 123 GND
52 D<4> 124 SPARE<4>
53 D<3> 125 SPARE<3>
54 D<2> 126 SPARE<2>
55 VCC 127 VCC
56 D<1> 128 SPARE<1>
57 D<0> 129 SPARE<0>
58 DATAOK 130 HFn
59 RXREADY 131 FFn
60 RXDATA 132 WENn
61 RXERROR 133 WCLK
62 GND 134 FIFO_D<0>
63 TDI 135 FIFO_D<1>
64 CTRL 136 FIFO_D<2>
65 TMS 137 FIFO_D<3>
66 SPARE<10> 138 FIFO_D<4>
67 TCK 139 FIFO_D<5>
68 SPARE<9> 140 FIFO_D<6>
69 SPARE<8> 141 VCC
70 DIOA<7> 142 FIFO_D<7>
71 DIOA<6> 143 rst
72 GND 144 GND
Legend : NC = Not Connected, unbonded pin
PGND = Unused I/O configured as additional Ground pin
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
KPR = Unused I/O with weak keeper (leave unconnected)
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : xc95288xl-6-TQ144
Optimization Method : DENSITY
Multi-Level Logic Optimization : ON
Ignore Timing Specifications : OFF
Default Register Power Up Value : LOW
Keep User Location Constraints : ON
What-You-See-Is-What-You-Get : OFF
Exhaustive Fitting : OFF
Keep Unused Inputs : OFF
Slew Rate : FAST
Power Mode : STD
Ground on Unused IOs : OFF
Set I/O Pin Termination : KEEPER
Global Clock Optimization : ON
Global Set/Reset Optimization : ON
Global Ouput Enable Optimization : ON
Input Limit : 54
Pterm Limit : 90