----------------------------------------------------------------------------------
-- Company:				Lawrence Berkeley National Laboratory 
-- Engineer:			Jean-Marie Bussat 
-- 
-- Create Date:    	16:53:09 08/23/2006 
-- Design Name: 		Optical interface CPLD 
-- Module Name:    	top - Behavioral 
-- Project Name: 		SAO - Multiple Waveform Digitizer System
-- Target Devices:	XC95288TQ144-7 
-- Tool versions: 	Webpack 8.2i 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity top is
	Port (
		-- Global use signals
		clk : 			in  	STD_LOGIC;
		rst : 			in  	STD_LOGIC;
		-- National Instruments board signals
		DIOA : 			in  	STD_LOGIC_VECTOR (7 downto 0);
		DIOB : 			in  	STD_LOGIC_VECTOR (7 downto 0);
		DIOC : 			out  	STD_LOGIC_VECTOR (7 downto 0);
		DIOD : 			out  	STD_LOGIC_VECTOR (7 downto 0);
--		PCLK1 : 			in  	STD_LOGIC;
		STOPTRIG1 : 	out  	STD_LOGIC;
		REQ1 : 			out  	STD_LOGIC;
		ACK1 : 			in  	STD_LOGIC;
--		PCLK2 : 			in  	STD_LOGIC;
		STOPTRIG2 : 	out  	STD_LOGIC;
		REQ2 : 			out  	STD_LOGIC;
		ACK2 : 			in  	STD_LOGIC;
		-- For debug/upgrade
		SPARE : 			inout STD_LOGIC_VECTOR (12 downto 0);
		-- GLINK interface
		D : 				in  	STD_LOGIC_VECTOR (15 downto 0);
		DATAOK : 		in  	STD_LOGIC;
		RXREADY : 		in  	STD_LOGIC;
		RXDATA : 		in  	STD_LOGIC;
		RXERROR : 		in  	STD_LOGIC;
		-- Serial output to optical transmitter
		CTRL : 			out  	STD_LOGIC;
		-- FIFO interface
		FIFO_Q : 		in  	STD_LOGIC_VECTOR (15 downto 0);
		FIFO_D : 		out  	STD_LOGIC_VECTOR (15 downto 0);
		FFn : 			in  	STD_LOGIC;
		HFn : 			in  	STD_LOGIC;
		EFn : 			in  	STD_LOGIC;
		WCLK : 			out  	STD_LOGIC;
		WENn : 			out  	STD_LOGIC;
		RSTn : 			out  	STD_LOGIC;
		RCLK : 			out  	STD_LOGIC;
		RENn : 			out  	STD_LOGIC;
		OEn : 			out  	STD_LOGIC);
end top;

architecture Behavioral of top is

---------------------------------------------------
-- Component Declaration								 --
---------------------------------------------------
component MainLogic is
    Port (	rst 					: in  STD_LOGIC;
				clk 					: in  STD_LOGIC;
				-- FIFO interface
				FFn 					: in  STD_LOGIC;
				HFn 					: in  STD_LOGIC;
				EFn 					: in  STD_LOGIC;
				RSTn 					: out STD_LOGIC;
				--NIDAQ Logic
				NICMD_Ready			: in  STD_LOGIC;							--Goes high when a new command is present
				NICMD					: in  STD_LOGIC_VECTOR (7 downto 0);--command
				NICMD_Arg			: in  STD_LOGIC_VECTOR (7 downto 0);--command argument (if needed)
				NICMD_Ack			: out STD_LOGIC;							--command ack
				NILogicBusy			: in  STD_LOGIC;							--this module is busy				
				StatusData			: out STD_LOGIC_VECTOR (15 downto 0);--Data that will be sent to PC (status)
				SendDataCmd			: out STD_LOGIC;							--Command that tell this module to send the data
				-- GLINK interface
				D 						: in  STD_LOGIC_VECTOR (15 downto 0);
				DATAOK 				: in  STD_LOGIC;
				RXREADY 				: in  STD_LOGIC;
				RXDATA 				: in  STD_LOGIC;
				RXERROR 				: in  STD_LOGIC;
			  --Optical Logic
				OPTCMD_Ready		: out STD_LOGIC;							--Goes high when a new command is present
				OPTCMD				: out STD_LOGIC_VECTOR (7 downto 0);--command
				OPTCMD_Arg			: out STD_LOGIC_VECTOR (7 downto 0);--command argument (if needed)
				OPTCMD_Ack			: in  STD_LOGIC;							--command ack
				OPTLogicBusy		: in  STD_LOGIC;							--this module is busy
				--RXDatasig
				EventReady			: in  STD_LOGIC;							--One full event is stored in the FIFO
				--Main Logic output
				EventReadout		: out STD_LOGIC;							--Event was readout
				DataPackageSize	: out STD_LOGIC_VECTOR (15 downto 0) --size of the data package, typically 4096 words
			 );
end component;

component NIDAQLogic is
    Port ( 
				rst 				: in  STD_LOGIC;
				clk 				: in  STD_LOGIC;
				-- National Instruments board signals
				DIOA 				: in  STD_LOGIC_VECTOR (7 downto 0);
				DIOB 				: in  STD_LOGIC_VECTOR (7 downto 0);
				DIOC 				: out STD_LOGIC_VECTOR (7 downto 0);
				DIOD 				: out STD_LOGIC_VECTOR (7 downto 0);
--				PCLK1 			: in  STD_LOGIC;
				STOPTRIG1	 	: out STD_LOGIC;
				REQ1 				: out STD_LOGIC;
				ACK1 				: in  STD_LOGIC;
--				PCLK2 			: in  STD_LOGIC;
				STOPTRIG2 		: out STD_LOGIC;
				REQ2 				: out STD_LOGIC;
				ACK2 				: in  STD_LOGIC;
				-- FIFO interface
				FIFO_Q 			: in  STD_LOGIC_VECTOR (15 downto 0);
				EFn 				: in  STD_LOGIC;
				RCLK	 			: out STD_LOGIC;
				RENn 				: out STD_LOGIC;
				OEn 				: out STD_LOGIC;
				-- Main Logic
				NICMD_Ready		: out STD_LOGIC;							--Goes high when a new command is present
				NICMD				: out STD_LOGIC_VECTOR (7 downto 0);--command
				NICMD_Arg		: out STD_LOGIC_VECTOR (7 downto 0);--command argument (if needed)
				NICMD_Ack		: in  STD_LOGIC;							--command ack
				StatusData		: in  STD_LOGIC_VECTOR (15 downto 0);--Data that will be sent to PC (status)
				SendDataCmd		: in  STD_LOGIC;							--Command that tell this module to send the data
				NILogicBusy		: out STD_LOGIC;							--this module is busy
				EventReadout	: in  STD_LOGIC;							--Event was readout
				DataPackageSize: in  STD_LOGIC_VECTOR (15 downto 0);--size of the data package, typically 4096 words				
				NIStatus			: out STD_LOGIC_VECTOR ( 7 downto 0)
			  );
end component;

component OpticalLogic is
    Port ( 
				rst : in  STD_LOGIC;
				clk : in  STD_LOGIC;
				-- GLINK interface
				D 						: in  STD_LOGIC_VECTOR (15 downto 0);
				DATAOK 				: in  STD_LOGIC;
				RXREADY 				: in  STD_LOGIC;
				RXDATA 				: in  STD_LOGIC;
				RXERROR 				: in  STD_LOGIC;
				-- Serial output to optical transmitter
				CTRL 					: out	STD_LOGIC;
				-- FIFO interface
				FIFO_D 				: out STD_LOGIC_VECTOR (15 downto 0);
				FFn 					: in  STD_LOGIC;
				HFn 					: in  STD_LOGIC;
				EFn 					: in  STD_LOGIC;
				WCLK 					: out STD_LOGIC;
				WENn 					: out STD_LOGIC;
				--Main Logic
				CMD_Ready			: in  STD_LOGIC;--Goes high when a new command is present
				CMD					: in  STD_LOGIC_VECTOR (7 downto 0);--command
				CMD_Arg				: in  STD_LOGIC_VECTOR (7 downto 0);--command argument (if needed)
				CMD_Ack				: out STD_LOGIC;--command ack
				OPTLogicBusy		: out STD_LOGIC;--this module is busy
				--Main Logic: RXDatasig
				EventReady			: out STD_LOGIC;--One full event is stored in the FIFO
				EventReadout		: in  STD_LOGIC;--Event was readout
				DataPackageSize 	: in  STD_LOGIC_VECTOR (15 downto 0) --size of the data package, typically 4096 words
				
			 );
end component;

---------------------------------------------------
-- Signal Declaration								 	 --
---------------------------------------------------

--NIDAQ Logic
signal NICMD_Readysig		: STD_LOGIC;
signal NICMDsig				: STD_LOGIC_VECTOR ( 7 downto 0);
signal NICMD_Argsig			: STD_LOGIC_VECTOR ( 7 downto 0);
signal NICMD_Acksig			: STD_LOGIC;
signal NILogicBusysig		: STD_LOGIC;
signal StatusDatasig			: STD_LOGIC_VECTOR (15 downto 0);
signal SendDataCmdsig		: STD_LOGIC;
signal NIStatussig			: STD_LOGIC_VECTOR ( 7 downto 0);
signal REQ1sig, REQ2sig		: STD_LOGIC;
--Optical Logic
signal OPTCMD_Readysig		: STD_LOGIC;
signal OPTCMDsig				: STD_LOGIC_VECTOR ( 7 downto 0);
signal OPTCMD_Argsig			: STD_LOGIC_VECTOR ( 7 downto 0);
signal OPTCMD_Acksig			: STD_LOGIC;
signal OPTLogicBusysig		: STD_LOGIC;
--RXDatasig
signal EventReadysig			: STD_LOGIC;
--Main Logic output
signal EventReadoutsig		: STD_LOGIC;
signal DataPackageSizesig	: STD_LOGIC_VECTOR (15 downto 0);
signal RCLKsig					: STD_LOGIC;
--FIFO
signal FIFO_Dsig				: STD_LOGIC_VECTOR (15 downto 0);
signal WENnsig					: STD_LOGIC;

begin

RCLK <= RCLKsig;
FIFO_D <= FIFO_Dsig;
WENn <= WENnsig;
REQ1 <= REQ1sig;
REQ2 <= REQ2sig;
--SPARE (0) <= EFn;
--SPARE (1) <= FFn;
--SPARE (2) <= clk;
--SPARE (3) <= DATAOK;
--SPARE (4) <= RXREADY;
--SPARE (5) <= RXDATA;
--SPARE (6) <= RXERROR;
--SPARE (7) <= OPTLogicBusysig;
--SPARE (8) <= EventReadysig;
--SPARE (9) <= NICMD_Readysig;
--SPARE (10) <= SendDataCmdsig;
--SPARE (11) <= NILogicBusysig;
--SPARE (12) <= OPTCMD_Readysig;

SPARE (0) <= NIStatussig(0);--EFn;
SPARE (1) <= NIStatussig(1);--WENnsig;--FFn;
SPARE (2) <= NIStatussig(2);--clk;--NICMDsig(0); --clk
SPARE (3) <= NIStatussig(3);--cav
--SPARE (3) <= NICMD_Readysig;
SPARE (4) <= NILogicBusysig;
SPARE (5) <= REQ1sig;
SPARE (6) <= ACK1;
SPARE (7) <= REQ2sig;
SPARE (8) <= ACK2;
--SPARE ( 8 downto 5) <= FIFO_Dsig(3 downto 0);--OPTCMDsig;--NICMDsig;
SPARE (12 downto 9) <= NICMDsig(7 downto 4);--FIFO_Dsig(7 downto 0);--OPTCMDsig;--NICMDsig;
--SPARE (12 downto 0) <= (OTHERS => '1');

MainLogiccomp : MainLogic
    Port Map(	
					rst 					=> rst,
					clk 					=> clk,
					-- FIFO interface
					FFn 					=> FFn,
					HFn 					=> HFn,
					EFn 					=> EFn,
					RSTn 					=> RSTn,
					--NIDAQ Logic
					NICMD_Ready			=> NICMD_Readysig,
					NICMD					=> NICMDsig,
					NICMD_Arg			=> NICMD_Argsig,
					NICMD_Ack			=> NICMD_Acksig,
					NILogicBusy			=> NILogicBusysig,
					StatusData			=> StatusDatasig,
					SendDataCmd			=> SendDataCmdsig,
					-- GLINK interface
					D 						=> D,
					DATAOK 				=> DATAOK,
					RXREADY 				=> RXREADY,
					RXDATA 				=> RXDATA,
					RXERROR 				=> RXERROR,
				  --Optical Logic
					OPTCMD_Ready		=> OPTCMD_Readysig,
					OPTCMD				=> OPTCMDsig,
					OPTCMD_Arg			=> OPTCMD_Argsig,
					OPTCMD_Ack			=> OPTCMD_Acksig,
					OPTLogicBusy		=> OPTLogicBusysig,
					--RXDatasig
					EventReady			=> EventReadysig,
					--Main Logic output
					EventReadout		=> EventReadoutsig,
					DataPackageSize	=> DataPackageSizesig 
			 );

NIDAQLogiccomp : NIDAQLogic
    Port Map( 
					rst 				=> rst,
					clk 				=> clk,
					-- National Instruments board signals
					DIOA 				=> DIOA,
					DIOB 				=> DIOB,
					DIOC 				=> DIOC,
					DIOD 				=> DIOD,
--					PCLK1 			=> PCLK1,
					STOPTRIG1	 	=> STOPTRIG1,
					REQ1 				=> REQ1sig,
					ACK1 				=> ACK1,
--					PCLK2 			=> PCLK2,
					STOPTRIG2 		=> STOPTRIG2,
					REQ2 				=> REQ2sig,
					ACK2 				=> ACK2,
					-- FIFO interface
					FIFO_Q 			=> FIFO_Q,
					EFn 				=> EFn,
					RCLK	 			=> RCLKsig,
					RENn 				=> RENn,
					OEn 				=> OEn,
					-- Main Logic
					NICMD_Ready		=> NICMD_Readysig,
					NICMD				=> NICMDsig,
					NICMD_Arg		=> NICMD_Argsig,
					NICMD_Ack		=> NICMD_Acksig,
					StatusData		=> StatusDatasig,
					SendDataCmd		=> SendDataCmdsig,
					NILogicBusy		=> NILogicBusysig,
					EventReadout	=> EventReadoutsig,
					DataPackageSize=> DataPackageSizesig,
					NIStatus			=> NIStatussig
			  );


OpticalLogiccomp : OpticalLogic
    Port Map( 
					rst 					=> rst,
					clk 					=> clk,
					-- GLINK interface
					D 						=> D,
					DATAOK 				=> DATAOK,
					RXREADY 				=> RXREADY,
					RXDATA 				=> RXDATA,
					RXERROR 				=> RXERROR,
					-- Serial output to optical transmitter
					CTRL 					=> CTRL,
					-- FIFO interface
					FIFO_D 				=> FIFO_Dsig,
					FFn 					=> FFn,
					HFn 					=> HFn,
					EFn 					=> EFn,
					WCLK 					=> WCLK,
					WENn 					=> WENnsig,
					--Main Logic
					CMD_Ready			=> OPTCMD_Readysig,
					CMD					=> OPTCMDsig,
					CMD_Arg				=> OPTCMD_Argsig,
					CMD_Ack				=> OPTCMD_Acksig,
					OPTLogicBusy		=> OPTLogicBusysig,
					--Main Logic: RXDatasig
					EventReady			=> EventReadysig,
					EventReadout		=> EventReadoutsig,
					DataPackageSize 	=> DataPackageSizesig 
			 );

end Behavioral;