Release 8.2i - xst I.31 Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to ./xst/projnav.tmp CPU : 0.00 / 0.27 s | Elapsed : 0.00 / 0.00 s --> Parameter xsthdpdir set to ./xst CPU : 0.00 / 0.27 s | Elapsed : 0.00 / 0.00 s --> Reading design: top.prj TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) Design Hierarchy Analysis 4) HDL Analysis 5) HDL Synthesis 5.1) HDL Synthesis Report 6) Advanced HDL Synthesis 6.1) Advanced HDL Synthesis Report 7) Low Level Synthesis 8) Partition Report 9) Final Report ========================================================================= * Synthesis Options Summary * ========================================================================= ---- Source Parameters Input File Name : "top.prj" Input Format : mixed Ignore Synthesis Constraint File : NO ---- Target Parameters Output File Name : "top" Output Format : NGC Target Device : XC9500XL CPLDs ---- Source Options Top Module Name : top Automatic FSM Extraction : YES FSM Encoding Algorithm : Auto Mux Extraction : YES Resource Sharing : YES ---- Target Options Add IO Buffers : YES MACRO Preserve : YES XOR Preserve : YES Equivalent register Removal : YES ---- General Options Optimization Goal : Area Optimization Effort : 2 Keep Hierarchy : YES RTL Output : Yes Hierarchy Separator : / Bus Delimiter : <> Case Specifier : maintain ---- Other Options lso : top.lso verilog2001 : YES safe_implementation : No Clock Enable : YES wysiwyg : NO ========================================================================= ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file "//engfile3/ddoering/Projects/SAO/VHDL/SAORXBoard/RxDataLogic.vhd" in Library work. Entity compiled. Entity (Architecture ) compiled. Compiling vhdl file "//engfile3/ddoering/Projects/SAO/VHDL/SAORXBoard/TransmitCommand.vhd" in Library work. Architecture behavioral of Entity transmitcommand is up to date. Compiling vhdl file "//engfile3/ddoering/Projects/SAO/VHDL/SAORXBoard/NI_Interface.vhd" in Library work. Architecture behavioral of Entity ni_interface is up to date. Compiling vhdl file "//engfile3/ddoering/Projects/SAO/VHDL/SAORXBoard/MainLogic.vhd" in Library work. Architecture behavioral of Entity mainlogic is up to date. Compiling vhdl file "//engfile3/ddoering/Projects/SAO/VHDL/SAORXBoard/NIDAQLogic.vhd" in Library work. Architecture behavioral of Entity nidaqlogic is up to date. Compiling vhdl file "//engfile3/ddoering/Projects/SAO/VHDL/SAORXBoard/OpticalLogic.vhd" in Library work. Architecture behavioral of Entity opticallogic is up to date. Compiling vhdl file "//engfile3/ddoering/Projects/SAO/VHDL/SAORXBoard/top.vhd" in Library work. Architecture behavioral of Entity top is up to date. ========================================================================= * Design Hierarchy Analysis * ========================================================================= Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Building hierarchy successfully finished. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). INFO:Xst:1304 - Contents of register > in unit never changes during circuit operation. The register is replaced by logic. INFO:Xst:1304 - Contents of register > in unit never changes during circuit operation. The register is replaced by logic. INFO:Xst:1304 - Contents of register > in unit never changes during circuit operation. The register is replaced by logic. INFO:Xst:1304 - Contents of register > in unit never changes during circuit operation. The register is replaced by logic. Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). INFO:Xst:1304 - Contents of register in unit never changes during circuit operation. The register is replaced by logic. Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). INFO:Xst:1304 - Contents of register in unit never changes during circuit operation. The register is replaced by logic. Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Performing bidirectional port resolution... Synthesizing Unit . Related source file is "//engfile3/ddoering/Projects/SAO/VHDL/SAORXBoard/MainLogic.vhd". WARNING:Xst:647 - Input is never used. WARNING:Xst:647 - Input is never used. WARNING:Xst:647 - Input is never used. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 6 | | Transitions | 13 | | Inputs | 7 | | Outputs | 8 | | Clock | clk (rising_edge) | | Reset | rst (positive) | | Reset type | asynchronous | | Reset State | idle | | Power Up State | idle | | Encoding | automatic | | Implementation | automatic | ----------------------------------------------------------------------- Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 8-bit register for signal . Found 8-bit register for signal . Found 16-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 5 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is "//engfile3/ddoering/Projects/SAO/VHDL/SAORXBoard/NI_Interface.vhd". WARNING:Xst:646 - Signal > is assigned but never used. WARNING:Xst:1780 - Signal is never used or assigned. WARNING:Xst:1780 - Signal is never used or assigned. WARNING:Xst:646 - Signal is assigned but never used. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 5 | | Transitions | 9 | | Inputs | 3 | | Outputs | 3 | | Clock | clk (rising_edge) | | Reset | rst (positive) | | Reset type | asynchronous | | Reset State | idle | | Power Up State | idle | | Encoding | automatic | | Implementation | automatic | ----------------------------------------------------------------------- Found 16-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 3-bit register for signal >. Found 1-bit register for signal . Found 2-bit down counter for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 1 Counter(s). inferred 9 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is "//engfile3/ddoering/Projects/SAO/VHDL/SAORXBoard/RxDataLogic.vhd". WARNING:Xst:647 - Input is never used. WARNING:Xst:647 - Input is never used. WARNING:Xst:647 - Input is never used. WARNING:Xst:647 - Input is never used. WARNING:Xst:647 - Input is never used. WARNING:Xst:646 - Signal is assigned but never used. INFO:Xst:1799 - State datareceivedst is never reached in FSM . Found finite state machine for signal . ----------------------------------------------------------------------- | States | 4 | | Transitions | 10 | | Inputs | 5 | | Outputs | 4 | | Clock | clk (rising_edge) | | Reset | rst (positive) | | Reset type | asynchronous | | Reset State | idle | | Power Up State | idle | | Encoding | automatic | | Implementation | automatic | ----------------------------------------------------------------------- Found 1-bit register for signal . Found 1-bit register for signal . Found 16-bit comparator equal for signal <$cmp_eq0005> created at line 244. Found 1-bit register for signal . Found 1-bit register for signal . Found 16-bit up counter for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 16-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 1 Counter(s). inferred 6 D-type flip-flop(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is "//engfile3/ddoering/Projects/SAO/VHDL/SAORXBoard/TransmitCommand.vhd". Found 5-bit down counter for signal . Found 1-bit register for signal . Found 20-bit register for signal . Summary: inferred 1 Counter(s). inferred 21 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is "//engfile3/ddoering/Projects/SAO/VHDL/SAORXBoard/NIDAQLogic.vhd". WARNING:Xst:647 - Input is never used. WARNING:Xst:647 - Input is never used. WARNING:Xst:646 - Signal is assigned but never used. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 7 | | Transitions | 12 | | Inputs | 5 | | Outputs | 11 | | Clock | clk (rising_edge) | | Reset | rst (positive) | | Reset type | asynchronous | | Reset State | idle | | Power Up State | idle | | Encoding | automatic | | Implementation | automatic | ----------------------------------------------------------------------- Found 4x1-bit ROM for signal <$mux0028>. Found 1-bit register for signal . Found 4-bit register for signal >. Found 1-bit register for signal . Found 1-bit register for signal . Found 8-bit subtractor for signal <$addsub0000> created at line 174. Found 8-bit register for signal . Found 8-bit register for signal . Found 16-bit register for signal . Found 8-bit register for signal . Found 1-bit register for signal . Found 16-bit up counter for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 16-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 1 ROM(s). inferred 1 Counter(s). inferred 11 D-type flip-flop(s). inferred 1 Adder/Subtractor(s). Unit synthesized. Synthesizing Unit . Related source file is "//engfile3/ddoering/Projects/SAO/VHDL/SAORXBoard/OpticalLogic.vhd". WARNING:Xst:646 - Signal is assigned but never used. Register equivalent to has been removed Found finite state machine for signal . ----------------------------------------------------------------------- | States | 4 | | Transitions | 10 | | Inputs | 5 | | Outputs | 4 | | Clock | clk (rising_edge) | | Reset | rst (positive) | | Reset type | asynchronous | | Reset State | idle | | Power Up State | idle | | Encoding | automatic | | Implementation | automatic | ----------------------------------------------------------------------- Found 1-bit register for signal . Found 16-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 18 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is "//engfile3/ddoering/Projects/SAO/VHDL/SAORXBoard/top.vhd". WARNING:Xst:646 - Signal > is assigned but never used. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # ROMs : 1 4x1-bit ROM : 1 # Adders/Subtractors : 1 8-bit subtractor : 1 # Counters : 4 16-bit up counter : 2 2-bit down counter : 1 5-bit down counter : 1 # Registers : 80 1-bit register : 70 16-bit register : 5 8-bit register : 5 # Comparators : 1 16-bit comparator equal : 1 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Analyzing FSM for best encoding. Analyzing FSM for best encoding. Analyzing FSM for best encoding. Analyzing FSM for best encoding. Analyzing FSM for best encoding. Optimizing FSM on signal with gray encoding. -------------------------- State | Encoding -------------------------- idle | 00 gendatacmdst | 01 sendcmdst_0 | 10 sendcmdst_1 | 11 -------------------------- Optimizing FSM on signal with sequential encoding. ------------------------------- State | Encoding ------------------------------- idle | 000 cmdreceivedst | 001 readfifost | 011 waitsendpackagest | 010 sendpackagest | 100 senddatast | 110 waitwritest | 101 ------------------------------- Optimizing FSM on signal with compact encoding. ---------------------------- State | Encoding ---------------------------- idle | 00 gendatacmdst | 10 gendatast | 11 datareceivedst | unreached writefifost | 01 ---------------------------- Optimizing FSM on signal with sequential encoding. ---------------------- State | Encoding ---------------------- idle | 000 request | 001 req_low | 010 req_high | 011 done | 100 ---------------------- Optimizing FSM on signal with sequential encoding. ---------------------------- State | Encoding ---------------------------- idle | 000 readoutcmdst | 001 simuldatacmdst | 010 hwstatusst | 100 glinkdatast | 101 sendcommandst | 011 ---------------------------- WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . ========================================================================= Advanced HDL Synthesis Report Macro Statistics # FSMs : 3 # ROMs : 1 4x1-bit ROM : 1 # Adders/Subtractors : 1 8-bit subtractor : 1 # Counters : 4 16-bit up counter : 2 2-bit down counter : 1 5-bit down counter : 1 # Registers : 142 Flip-Flops : 142 # Comparators : 1 16-bit comparator equal : 1 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... implementation constraint: INIT=r : NIDAQSTATE_FFd3 implementation constraint: INIT=r : NIDAQSTATE_FFd2 implementation constraint: INIT=r : NIDAQSTATE_FFd1 Optimizing unit ... Optimizing unit ... implementation constraint: INIT=r : RXDATALOGICSTATE_FFd2 implementation constraint: INIT=r : RXDATALOGICSTATE_FFd1 Optimizing unit ... implementation constraint: INIT=r : p2state_FFd3 implementation constraint: INIT=r : p2state_FFd2 implementation constraint: INIT=r : p2state_FFd1 Optimizing unit ... implementation constraint: INIT=r : MAINSTATE_FFd3 implementation constraint: INIT=r : MAINSTATE_FFd1 implementation constraint: INIT=r : MAINSTATE_FFd2 Optimizing unit ... implementation constraint: INIT=r : OPTICALLOGICSTATE_FFd2 implementation constraint: INIT=r : OPTICALLOGICSTATE_FFd1 INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . ========================================================================= * Partition Report * ========================================================================= Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- ========================================================================= * Final Report * ========================================================================= Final Results RTL Top Level Output File Name : top.ngr Top Level Output File Name : top Output Format : NGC Optimization Goal : Area Keep Hierarchy : YES Target Technology : XC9500XL CPLDs Macro Preserve : YES XOR Preserve : YES Clock Enable : YES wysiwyg : NO Design Statistics # IOs : 115 Cell Usage : # BELS : 870 # AND2 : 348 # AND3 : 38 # AND4 : 1 # GND : 2 # INV : 251 # OR2 : 164 # OR3 : 4 # VCC : 3 # XOR2 : 59 # FlipFlops/Latches : 239 # FDC : 189 # FDCE : 42 # FDP : 3 # FDPE : 1 # FTC : 4 # IO Buffers : 115 # IBUF : 59 # OBUF : 56 ========================================================================= CPU : 60.25 / 60.53 s | Elapsed : 60.00 / 60.00 s --> Total memory usage is 133716 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 23 ( 0 filtered) Number of infos : 8 ( 0 filtered)