----------------------------------------------------------------------------------
-- Company:				Lawrence Berkeley National Laboratory 
-- Engineer:			Jean-Marie Bussat 
-- 
-- Create Date:    	12:35:39 08/10/2006 
-- Design Name: 		Optical interface CPLD
-- Module Name:    	TransmitCommand - Behavioral 
-- Project Name: 		SAO - Multiple Waveform Digitizer System
-- Target Devices:	XC95288TQ144-7 
-- Tool versions: 	Webpack 8.2i
-- Description:		Send a 16-bit command to the digitizer motherboard 
--							via the optical link.
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments:	Simulated and verified 08/10/06 
--                      Testbench is SimTransmitCommand.vhd
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity TransmitCommand is
	Port ( 
		rst 			: in  	STD_LOGIC;
		clk 			: in  	STD_LOGIC;
		command_in 	: in  	STD_LOGIC_VECTOR (15 downto 0);
		send 			: in 		STD_LOGIC;
		ser_out 		: out  	STD_LOGIC;
		done 			: out  	STD_LOGIC
	);
end TransmitCommand;

architecture Behavioral of TransmitCommand is

constant HEADER : std_logic_vector(3 downto 0) := "1011";

signal sr : std_logic_vector(19 downto 0);
signal sending : std_logic;
signal cnt : std_logic_vector(4 downto 0);

begin

	-- Implement the 20-bit shift register
	-- Shift data whenever sending is high
	-- otherwise, load the register with the data to send
	-- and add the header at the begining.
	SHIFT_REGISTER : process(rst,clk,sr,sending)
	begin
		if rst='1' then
			sr<=(others=>'0');
		else
			if clk'event and clk='1' then
				if sending='1' then
						sr(18 downto 0)<=sr(19 downto 1);
				else
					sr(19 downto 4)<=command_in;
					sr(3 downto 0)<=HEADER;
				end if;
			end if;
		end if;
	end process SHIFT_REGISTER;

	-- AND the serial output with the sending signal to make
	-- sure that we won't see any spurious change of the ser_out
	-- line when the shift register is loaded
	ser_out<=sr(0) and sending;
	
	-- 5-bit downcounter to count the number of bit sent out
	COUNTER : process(rst,clk,cnt,sending)
	begin
		if rst='1' then
			cnt<=(others=>'0');
		else
			if clk'event and clk='1' then
				if sending='0' then
					cnt<="10011";
				else
					cnt<=cnt-"00001";
				end if;
			end if;
		end if;
	end process COUNTER;

	-- Control the operation of the transmitter; Implement a 
	-- synchronized RS flip-flop.
	-- When send is at zero, the shift register is loaded, the
	-- transmission is inhibited and the counter loaded with 19.
	-- When send goes high, the transmission starts (sending goes
	-- high) and the counter decrements for each clock cycle.
	-- When the counter reaches 0, everything stops with sending
	-- going back to zero.
	CONTROL : process(rst,clk,cnt,send,sending)
	begin
		if rst='1' then
			sending<='0';
		else
			if clk'event and clk='1' then
				if send='1' then
					if cnt="00000" then
						sending<='0';
					else
						sending<='1';
					end if;
				else
					if cnt="00000" then
						sending<='0';
					end if;
				end if;
			end if;		
		end if;
	end process CONTROL;
	
	done<=not sending;

end Behavioral;