---------------------------------------------------------------------------------- -- Company: LBNL -- Engineer: Dionisio Doering -- -- Create Date: 15:51:12 12/06/2006 -- Design Name: Optical interface CPLD -- Module Name: OpticalLogic - Behavioral -- Project Name: SAO - Multiple Waveform Digitizer System -- Target Devices: XC95288TQ144-7 -- Tool versions: ISE 8.2 -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity OpticalLogic is Port ( rst : in STD_LOGIC; clk : in STD_LOGIC; -- GLINK interface D : in STD_LOGIC_VECTOR (15 downto 0); DATAOK : in STD_LOGIC; RXREADY : in STD_LOGIC; RXDATA : in STD_LOGIC; RXERROR : in STD_LOGIC; -- Serial output to optical transmitter CTRL : out STD_LOGIC; -- FIFO interface FIFO_D : out STD_LOGIC_VECTOR (15 downto 0); FFn : in STD_LOGIC; HFn : in STD_LOGIC; EFn : in STD_LOGIC; WCLK : out STD_LOGIC; WENn : out STD_LOGIC; --Main Logic CMD_Ready : in STD_LOGIC;--Goes high when a new command is present CMD : in STD_LOGIC_VECTOR (7 downto 0);--command CMD_Arg : in STD_LOGIC_VECTOR (7 downto 0);--command argument (if needed) CMD_Ack : out STD_LOGIC;--command ack OPTLogicBusy : out STD_LOGIC;--this module is busy --Main Logic: RXDatasig EventReady : out STD_LOGIC;--One full event is stored in the FIFO EventReadout : in STD_LOGIC;--Event was readout DataPackageSize : in STD_LOGIC_VECTOR (15 downto 0) --size of the data package, typically 4096 words ); end OpticalLogic; architecture Behavioral of OpticalLogic is --------------------------------------------------- -- Component Declaration -- --------------------------------------------------- component RxDataLogic is Port ( rst : in STD_LOGIC; --reset clk : in STD_LOGIC; --clock -- GLINK interface D : in STD_LOGIC_VECTOR (15 downto 0); DATAOK : in STD_LOGIC; RXREADY : in STD_LOGIC; RXDATA : in STD_LOGIC; RXERROR : in STD_LOGIC; -- FIFO interface FIFO_D : out STD_LOGIC_VECTOR (15 downto 0); FFn : in STD_LOGIC; HFn : in STD_LOGIC; EFn : in STD_LOGIC; WCLK : out STD_LOGIC; WENn : out STD_LOGIC; -- Control Logic Interface GenSimData : in STD_LOGIC;--tell the module to generate the simulated data, simdata has always 4096words Busy : out STD_LOGIC;--module is busy EventReady : out STD_LOGIC;--One full event is stored in the FIFO EventReadout : in STD_LOGIC;--Event was readout DataPackageSize : in STD_LOGIC_VECTOR (15 downto 0); --size of the data package, typically 4096 words ErrorFlag : out STD_LOGIC--if some error happend, like FIFO is FULL and trying to write more data ); end component; component TransmitCommand is Port ( rst : in STD_LOGIC; clk : in STD_LOGIC; command_in : in STD_LOGIC_VECTOR (15 downto 0); send : in STD_LOGIC; ser_out : out STD_LOGIC; done : out STD_LOGIC ); end component; --type OPTICALLOGICSTATE_TYPE is (IDLE, GENDATACMDST, SENDCMDST, SYNCMODECMDST,WAITSYNCMODEST,DATAMODECMDST, WAITDATAMODEST); type OPTICALLOGICSTATE_TYPE is (IDLE, GENDATACMDST, SENDCMDST,SENDSIMULCMDST); --------------------------------------------------- -- Signal Declaration -- --------------------------------------------------- signal OPTICALLOGICSTATE : OPTICALLOGICSTATE_TYPE; --state machine states --RXDATALOGICSIGNALS signal GenSimDatasig : STD_LOGIC; signal RxDataLogicBusysig : STD_LOGIC; --signal EventReadysig : STD_LOGIC; --signal EventReadoutsig : STD_LOGIC; --signal DataPackageSizesig : STD_LOGIC_VECTOR (15 downto 0); signal ErrorFlagsig : STD_LOGIC; --TRANSMITCOMMAND SIGNALS signal command_insig : STD_LOGIC_VECTOR (15 downto 0); signal sendsig : STD_LOGIC; signal donesig : STD_LOGIC; -- Internal signals signal OPTLogicBusysig : STD_LOGIC; begin --------------------------------------------------- -- Signal Connections -- --------------------------------------------------- --this module is busy if this or the lower modules are busy OPTLogicBusy <= OPTLogicBusysig or RxDataLogicBusysig; --------------------------------------------------- -- Component instantiation -- --------------------------------------------------- --state machine process -- -- RXDATALOGICSMproc : process (rst, clk,OPTICALLOGICSTATE, CMD_Ready) begin if (rst = '1') then GenSimDatasig <= '0'; OPTLogicBusysig <= '0'; CMD_Ack <= '0'; command_insig <= x"0000"; sendsig <= '1'; --next state logic OPTICALLOGICSTATE <= IDLE; elsif (clk'event and clk = '1') then case (OPTICALLOGICSTATE) is when GENDATACMDST => GenSimDatasig <= '1'; OPTLogicBusysig <= '1'; CMD_Ack <= '1'; command_insig <= command_insig; sendsig <= sendsig; --next state logic OPTICALLOGICSTATE <= IDLE; when SENDCMDST => GenSimDatasig <= '0'; OPTLogicBusysig <= '1'; CMD_Ack <= '1'; command_insig(15 downto 8) <= CMD; command_insig( 7 downto 0) <= CMD_ARG; sendsig <= sendsig; --next state logic OPTICALLOGICSTATE <= IDLE; when SENDSIMULCMDST => GenSimDatasig <= '0'; OPTLogicBusysig <= '1'; CMD_Ack <= '1'; command_insig(15 downto 8) <= CMD; command_insig( 7 downto 0) <= CMD_ARG; sendsig <= sendsig; --next state logic if donesig = '1' then command_insig(15 downto 8) <= x"0C"; OPTICALLOGICSTATE <= IDLE; end if; -- when SYNCMODECMDST => -- GenSimDatasig <= '0'; -- OPTLogicBusysig <= '1'; -- CMD_Ack <= '1'; -- command_insig <= command_insig; -- sendsig <= sendsig; -- --next state logic -- OPTICALLOGICSTATE <= IDLE; -- when WAITSYNCMODEST => -- GenSimDatasig <= '0'; -- OPTLogicBusysig <= '1'; -- CMD_Ack <= '1'; -- command_insig <= command_insig; -- sendsig <= sendsig; -- --next state logic -- OPTICALLOGICSTATE <= IDLE; -- when DATAMODECMDST => -- GenSimDatasig <= '0'; -- OPTLogicBusysig <= '1'; -- CMD_Ack <= '1'; -- command_insig <= command_insig; -- sendsig <= sendsig; -- --next state logic -- OPTICALLOGICSTATE <= IDLE; -- when WAITDATAMODEST => -- GenSimDatasig <= '0'; -- OPTLogicBusysig <= '1'; -- CMD_Ack <= '1'; -- command_insig <= command_insig; -- sendsig <= sendsig; -- --next state logic -- OPTICALLOGICSTATE <= IDLE; when others => --IDLE GenSimDatasig <= '0'; OPTLogicBusysig <= '0'; CMD_Ack <= '0'; command_insig <= command_insig; sendsig <= sendsig; --next state logic -- change state base on command received if (CMD_Ready = '1') then if(CMD = x"66") then -- generate simulated data in this board (102 decimal) OPTICALLOGICSTATE <= GENDATACMDST; elsif(CMD = x"67") then -- generate simulated data in this board (103 decimal) OPTICALLOGICSTATE <= SENDSIMULCMDST; elsif(CMD(7 downto 6) = "00") then -- generate simulated data in this board (102 decimal) OPTICALLOGICSTATE <= SENDCMDST;--unrecognized command end if; else OPTICALLOGICSTATE <= OPTICALLOGICSTATE; end if; end case; end if; end process; --------------------------------------------------- -- Component Instantiation -- --------------------------------------------------- RxDataLogiccomp : RxDataLogic Port Map( rst => rst, clk => clk, -- GLINK interface D => D, DATAOK => DATAOK, RXREADY => RXREADY, RXDATA => RXDATA, RXERROR => RXERROR, -- FIFO interface FIFO_D => FIFO_D, FFn => FFn, HFn => HFn, EFn => EFn, WCLK => WCLK, WENn => WENn, -- Control Logic Interface GenSimData => GenSimDatasig, Busy => RxDataLogicBusysig, EventReady => EventReady, EventReadout => EventReadout, DataPackageSize => DataPackageSize, ErrorFlag => ErrorFlagsig ); TransmitCommandcomp : TransmitCommand Port Map( rst => rst, clk => clk, command_in => command_insig, send => sendsig, ser_out => CTRL, done => donesig ); end Behavioral;